49 output dq,
// I/O pad (appears on the output 1/2 clk_div earlier, than DDR data) 50 input clk,
// free-running system clock, same frequency as iclk (shared for R/W) 51 input clk_div,
// free-running half clk frequency, front aligned to clk (shared for R/W) 53 input [
7:
0]
dly_data,
// delay value (3 LSB - fine delay) 54 input [
1:
0]
din,
// parallel data to be sent out 55 // input [1:0] tin, // tristate for data out (sent out earlier than data!) 56 input tin,
// tristate for data out (sent out earlier than data!) 57 input set_delay,
// clk_div synchronous load odelay value from dly_data 58 input ld_delay // clk_div synchronous set odealy value from loaded 67 .
clk(
clk),
// serial output clock 70 .
din(
din[
1:
0]),
// parallel data in 71 // .tin(tin[1:0]), // parallel tri-state in 72 .
tin(
tin),
// parallel tri-state in 74 .
dout_iob(),
// data out to be connected directly to the output buffer 75 .
tout_dly(),
// tristate out to be connected to odelay input 76 .
tout_iob(
dq_tri)
// tristate out to be connected directly to the tristate control of the output buffer
[MODE_DDR=="TRUE"?3:1:0] 11538din
6073HIGH_PERFORMANCE_MODE"FALSE"
dqs_out_dly_i odelay_fine_pipe
6068IODELAY_GRP"IODELAY_MEMORY"
[MODE_DDR=="TRUE"?3:0:0] 11539tin
real 6072REFCLK_FREQUENCY300.0
integer 6069ODELAY_VALUE0