43 parameter SENS_PHASE_WIDTH=
8,
// number of bits for te phase counter (depends on divisors) 45 parameter CLKIN_PERIOD_SENSOR =
3.000,
// input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps 47 parameter CLKFBOUT_PHASE_SENSOR =
0.000,
// CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) 56 parameter SENS_SS_EN =
"FALSE",
// Enables Spread Spectrum mode 57 parameter SENS_SS_MODE =
"CENTER_HIGH",
//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" 60 parameter IODELAY_GRP =
"IODELAY_SENSOR",
// may need different for different channels? 74 parameter HISPI_IOSTANDARD =
"DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA) 81 input load,
// only used when delay, not phase 88 output [
7:
0]
ps_out,
// output[7:0] reg 116 )
ibufds_ibufgds0_i (
130 )
ibufds_ibufgds0_i (
158 // generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock 159 // received from the sensor (may need to reset MMCM after resetting sensor) 172 .
CLKFBOUT_USE_FINE_PS(
"FALSE"),
173 .
CLKOUT0_USE_FINE_PS (
"TRUE"),
174 .
CLKOUT1_USE_FINE_PS (
"TRUE"),
177 .
COMPENSATION (
"ZHOLD"),
183 .
STARTUP_WAIT (
"FALSE")
228 .
STARTUP_WAIT (
"FALSE")
247 assign ps_out_w =
0;
// alternatively - register delay written
7164IODELAY_GRP"IODELAY_SENSOR"
7162SENS_SS_MODE"CENTER_HIGH"
7176HISPI_IFD_DELAY_VALUE"AUTO"
real 7166REFCLK_FREQUENCY200.0
integer 7165IDELAY_VALUE0
7191clkin_pxd_stopped_mmcm
clk_dly_i idelay_nofine[generate]
7171HISPI_DIFF_TERM"TRUE"
7151CLKIN_PERIOD_SENSOR3.000
7172HISPI_UNTUNED_SPLIT"FALSE"
7159SENS_REF_JITTER10.010
7168HISPI_DELAY_CLK"FALSE"
7175HISPI_IBUF_LOW_PWR"TRUE"
7152CLKFBOUT_MULT_SENSOR3
[PHASE_WIDTH-1:0] 11433ps_dout
7192clkfb_pxd_stopped_mmcm
[PHASE_WIDTH-1:0] 11431ps_din
7174HISPI_IBUF_DELAY_VALUE"0"
mmcm_or_pll_i mmcm_phase_cntr[generate]
7153CLKFBOUT_PHASE_SENSOR0.000
7163SENS_SS_MOD_PERIOD10000
7167HIGH_PERFORMANCE_MODE"FALSE"
7160SENS_REF_JITTER20.010
mmcm_or_pll_i pll_base[generate]
ibufds_ibufgds0_i ibufds_ibufgds_50[generate]
ibufds_ibufgds0_i ibufds_ibufgds[generate]
7177HISPI_IOSTANDARD"DIFF_SSTL18_I"
7150SENS_BANDWIDTH"OPTIMIZED"
7170HISPI_CAPACITANCE"DONT_CARE"