41 // all counters are two-clock cycle nets 43 parameter PHASE_WIDTH=
8,
// number of bits for te phase counter (depends on divisors) 44 parameter CLKIN_PERIOD =
0.000,
// input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps 45 parameter BANDWIDTH =
"OPTIMIZED",
//"OPTIMIZED", "HIGH","LOW" 46 parameter CLKFBOUT_MULT_F =
5.000,
// 2.0 to 64.0 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE 47 parameter CLKFBOUT_PHASE =
0.000,
// CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) 48 parameter CLKOUT0_PHASE =
0.000,
// CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000) 49 parameter CLKOUT1_PHASE =
0.000,
// Initial/static fine phase shift, 1/(56*Fvco) actual step 62 parameter CLKOUT4_CASCADE=
"FALSE",
// cascades the output6 divider to the input for output 4 63 parameter CLKFBOUT_USE_FINE_PS =
"FALSE",
// Enable variable fine pase shift. Enable 1/(56*Fvco) phase inceremnts, round-robin 64 parameter CLKOUT0_USE_FINE_PS =
"FALSE",
// Same fine phase shift for all outputs where this attribute is "TRUE" 72 parameter CLKOUT1_DIVIDE =
1,
// CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4) 78 parameter COMPENSATION=
"ZHOLD",
// "ZHOLD",BUF_IN","EXTERNAL","INTERNAL 79 // ZHOLD - provide negative hold time on I/O registers 80 // INTERNAL - using internal compensation no deley is compensated 81 // EXTERNAL - external to the FPGA network is being compensated 82 // BUF_IN - no compensation when clock input is driveen by BUFG/BUFH/BUFR or GT 83 parameter DIVCLK_DIVIDE =
1,
// Integer 1..106. Divides all outputs with respect to CLKIN 84 parameter REF_JITTER1 =
0.010,
// Expected jitter on CLKIN1 (0.000..0.999) 86 parameter SS_EN =
"FALSE",
// Enables Spread Spectrum mode 87 parameter SS_MODE =
"CENTER_HIGH",
//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" 88 parameter SS_MOD_PERIOD =
10000,
// integer 4000-40000 - SS modulation period in ns 89 parameter STARTUP_WAIT =
"FALSE" // Delays "DONE" signal until MMCM is locked 93 input clkin2,
// Alternative clock input 94 input sel_clk2,
// Clock input select (inverted from MMCME2_ADV !!!) 96 input rst,
// asynchronous reset input 98 input psclk,
// phase shift clock input 100 input ps_we,
// phase shift write eneble 105 output clkout0,
// output 0, HPC BUFR/BUFIO capable 106 output clkout1,
// output 1, HPC BUFR/BUFIO capable 107 output clkout2,
// output 2, HPC BUFR/BUFIO capable 108 output clkout3,
// output 3, HPC BUFR/BUFIO capable 109 output clkout4,
// output 4, HPC BUFR/BUFIO not capable 110 output clkout5,
// output 5, HPC BUFR/BUFIO not capable 111 output clkout6,
// output 6, HPC BUFR/BUFIO not capable 123 wire psen;
// phase shift enable input 124 reg psincdec;
// phase shift direction input (1 - increment, 0 - decrement) 125 wire psdone;
// phase shift done (12 clocks after psen 128 // TODO: find out why it was optimized out! 132 // made a difference, so it doesn't seem Vivado extends bits of operands "+", "-" 142 else if (
psen &&
psincdec)
ps_dout_r <=
ps_dout_r +
1;
//SuppressThisWarning ISExst Result of 9-bit expression is truncated to fit in 8-bit target. 143 else if (
psen && !
psincdec)
ps_dout_r <=
ps_dout_r -
1;
//SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 8-bit target. 196 // .IS_CLKINSEL_INVERTED (1'b0), // ISE does not have this parameter 197 // .IS_PSEN_INVERTED (1'b0), // ISE does not have this parameter 198 // .IS_PSINCDEC_INVERTED (1'b0), // ISE does not have this parameter 199 // .IS_PWRDWN_INVERTED (1'b0), // ISE does not have this parameter 200 // .IS_RST_INVERTED (1'b0), // ISE does not have this parameter 223 .
DO (),
// Dynamic reconfiguration output[15:0] 224 .
DRDY (),
// Dynamic reconfiguration output 225 .
LOCKED (
locked),
// output 226 .
PSDONE (
psdone),
// output 228 .
CLKIN1 (
clkin1),
// input 229 .
CLKIN2 (
clkin2),
// input 230 .
CLKINSEL (~
sel_clk2),
// input 0: Select CLKIN2, 1: Select CLKIN1 !!!!!!!!!!!!! 231 .
DADDR (
7'b0),
// Dynamic reconfiguration address (input[6:0]) 232 .
DCLK (
1'b0),
// Dynamic reconfiguration clock input 233 .
DEN (
1'b0),
// Dynamic reconfiguration enable input 234 .
DI (
16'b0),
// Dynamic reconfiguration data (input[15:0]) 235 .
DWE (
1'b0),
// Dynamic reconfiguration Write Enable input 236 .
PSCLK (
psclk),
// input 237 .
PSEN (
psen),
// input 239 .
PWRDWN (
pwrdwn),
// input
11392CLKOUT0_DUTY_CYCLE0.5
11394CLKOUT2_DUTY_CYCLE0.5
11458diffwire[PHASE_WIDTH:0]
11403CLKOUT2_USE_FINE_PS"FALSE"
11404CLKOUT3_USE_FINE_PS"FALSE"
11395CLKOUT3_DUTY_CYCLE0.5
11398CLKOUT6_DUTY_CYCLE0.5
11396CLKOUT4_DUTY_CYCLE0.5
11382BANDWIDTH"OPTIMIZED"
11450ps_dout_rreg[PHASE_WIDTH-1:0]
11400CLKFBOUT_USE_FINE_PS"FALSE"
11454ps_targetreg[PHASE_WIDTH-1:0]
11406CLKOUT5_USE_FINE_PS"FALSE"
11397CLKOUT5_DUTY_CYCLE0.5
[PHASE_WIDTH-1:0] 11433ps_dout
11402CLKOUT1_USE_FINE_PS"FALSE"
11420SS_MODE"CENTER_HIGH"
11401CLKOUT0_USE_FINE_PS"FALSE"
11399CLKOUT4_CASCADE"FALSE"
[PHASE_WIDTH-1:0] 11431ps_din
11408CLKOUT0_DIVIDE_F1.000
11383CLKFBOUT_MULT_F5.000
11393CLKOUT1_DUTY_CYCLE0.5
11405CLKOUT4_USE_FINE_PS"FALSE"
11407CLKOUT6_USE_FINE_PS"FALSE"