42 parameter CLKIN_PERIOD =
0.000,
// input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps 43 parameter BANDWIDTH =
"OPTIMIZED",
// "OPTIMIZED", "HIGH","LOW" 44 parameter CLKFBOUT_MULT =
1,
// integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE 45 parameter CLKFBOUT_PHASE =
0.000,
// CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) 46 parameter CLKOUT0_PHASE =
0.000,
// CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000) 47 parameter CLKOUT1_PHASE =
0.000,
// Initial/static fine phase shift, 1/(56*Fvco) actual step 59 parameter CLKOUT1_DIVIDE =
1,
// CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4) 64 parameter DIVCLK_DIVIDE =
1,
// Integer 1..106. Divides all outputs with respect to CLKIN 65 parameter REF_JITTER1 =
0.010,
// Expected jitter on CLKIN1 (0.000..0.999) 66 parameter STARTUP_WAIT =
"FALSE" // Delays "DONE" signal until MMCM is locked 69 input clkin,
// General clock input 71 input rst,
// asynchronous reset input 73 output clkout0,
// output 0, HPC BUFR/BUFIO capable 74 output clkout1,
// output 1, HPC BUFR/BUFIO capable 75 output clkout2,
// output 2, HPC BUFR/BUFIO capable 76 output clkout3,
// output 3, HPC BUFR/BUFIO capable 77 output clkout4,
// output 4, HPC BUFR/BUFIO not capable 78 output clkout5,
// output 5, HPC BUFR/BUFIO not capable 116 .
LOCKED (
locked),
// output 118 .
CLKIN1 (
clkin),
// input 119 .
PWRDWN (
pwrdwn),
// input 121 // Unused ports for advanced option 122 // Unused second clock input and select 123 .
CLKIN2 (
1'b0),
// input 124 .
CLKINSEL (
1'b1),
// input 126 .
DADDR (
7'b0),
// input[6:0] 127 .
DCLK (
1'b0),
// input 128 .
DEN (
1'b0),
// input 129 .
DI (
16'b0),
// input[15:0] 130 .
DO (),
// output[15:0]
11560CLKOUT3_DUTY_CYCLE0.5
11561CLKOUT4_DUTY_CYCLE0.5
11562CLKOUT5_DUTY_CYCLE0.5
11557CLKOUT0_DUTY_CYCLE0.5
11558CLKOUT1_DUTY_CYCLE0.5
11548BANDWIDTH"OPTIMIZED"
11559CLKOUT2_DUTY_CYCLE0.5