x393  1.0
FPGAcodeforElphelNC393camera
idelay_nofine Module Reference
Inheritance diagram for idelay_nofine:
Collaboration diagram for idelay_nofine:

Public Attributes

Inputs

clk  
rst  
set  
ld  
delay   [ 4 : 0 ]
data_in  

Outputs

data_out  

Parameters

IODELAY_GRP  "IODELAY_MEMORY"
DELAY_VALUE  integer 0
REFCLK_FREQUENCY  real 200 . 0
HIGH_PERFORMANCE_MODE  "FALSE"

Module Instances

IDELAYE2::idelay2_i   Module IDELAYE2

Detailed Description

Definition at line 41 of file idelay_nofine.v.

Member Data Documentation

IODELAY_GRP "IODELAY_MEMORY"
Parameter

Definition at line 43 of file idelay_nofine.v.

DELAY_VALUE 0
Parameter

Definition at line 44 of file idelay_nofine.v.

REFCLK_FREQUENCY 200 . 0
Parameter

Definition at line 45 of file idelay_nofine.v.

HIGH_PERFORMANCE_MODE "FALSE"
Parameter

Definition at line 46 of file idelay_nofine.v.

clk
Input

Definition at line 48 of file idelay_nofine.v.

rst
Input

Definition at line 49 of file idelay_nofine.v.

set
Input

Definition at line 50 of file idelay_nofine.v.

ld
Input

Definition at line 51 of file idelay_nofine.v.

delay [ 4 : 0 ]
Input

Definition at line 52 of file idelay_nofine.v.

data_in
Input

Definition at line 53 of file idelay_nofine.v.

data_out
Output

Definition at line 54 of file idelay_nofine.v.

IDELAYE2 idelay2_i
Module Instance

Definition at line 59 of file idelay_nofine.v.


The documentation for this Module was generated from the following files: