oddr_ds.v

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`timescale 1ns/1ps

module  oddr_ds # (
        parameter CAPACITANCE =  "DONT_CARE",
        parameter IOSTANDARD =   "DIFF_SSTL15",
        parameter SLEW =         "SLOW",
        parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
        parameter INIT         = 1'b0,
        parameter SRTYPE = "SYNC"
)(
    input  clk,
    input  ce,
    input  rst,
    input  set,
    input [1:0] din,
    input  tin, // tristate control
    output dq,
    output ndq
);
    wire idq;
    ODDR #(
        .DDR_CLK_EDGE(DDR_CLK_EDGE),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
    ) ODDR_i (
        .Q(idq), // output 
        .C(clk), // input 
        .CE(ce), // input 
        .D1(din[0]), // input 
        .D2(din[1]), // input 
        .R(rst), // input 
        .S(set) // input 
    );

    OBUFTDS #(
        .CAPACITANCE (CAPACITANCE),
        .IOSTANDARD  (IOSTANDARD),
        .SLEW        (SLEW)
    ) OBUFDS_i (
        .O  (dq), // output 
        .OB (ndq), // output 
        .I  (idq), // input 
        .T  (tin) // input 
    );

endmodule