byte_lane Module Reference

Inheritance diagram for byte_lane:

Collaboration diagram for byte_lane:

Static Public Member Functions

Always Constructs
ALWAYS_314	( clk_div )

Public Attributes

Inputs
clk
clk_div
inv_clk_div
rst
dci_disable_dqs
dci_disable_dq
din	[ 31 : 0 ]
din_dm	[ 3 : 0 ]
tin_dq	[ 3 : 0 ]
din_dqs	[ 3 : 0 ]
tin_dqs	[ 3 : 0 ]
dly_data	[ 7 : 0 ]
dly_addr	[ 4 : 0 ]
ld_delay
set

Inouts
dq	[ 7 : 0 ]
dqs
ndqs

Outputs
dm
dout	[ 31 : 0 ]

Parameters
IODELAY_GRP	"IODELAY_MEMORY"
IBUF_LOW_PWR	"TRUE"
IOSTANDARD_DQ	"SSTL15_T_DCI"
IOSTANDARD_DM	"SSTL15"
IOSTANDARD_DQS	"DIFF_SSTL15_T_DCI"
SLEW_DQ	"SLOW"
SLEW_DQS	"SLOW"
REFCLK_FREQUENCY	real 300 . 0
HIGH_PERFORMANCE_MODE	"FALSE"

GENERATE
GENERATE [148]

Signals
wire	dqs_read
wire	iclk
reg[ 31 : 0 ]	din_r
reg[ 3 : 0 ]	din_dm_r
reg[ 3 : 0 ]	din_dqs_r
reg[ 3 : 0 ]	tin_dq_r
reg[ 3 : 0 ]	tin_dqs_r
reg[ 7 : 0 ]	dly_data_r
reg	set_r
reg	dci_disable_dqs_r
reg	dci_disable_dq_r
reg[ 7 : 0 ]	ld_odly
reg[ 7 : 0 ]	ld_idly
reg	ld_odly_dqs
reg	ld_idly_dqs
reg	ld_odly_dm
wire[ 9 : 0 ]	decode_sel

Module Instances
BUFR::iclk_i	Module BUFR
dq_single::dq_i	Module dq_single [generate]
dm_single::dm_i	Module dm_single
dqs_single::dqs_i	Module dqs_single

Detailed Description

Definition at line 43 of file byte_lane.v.

Member Function Documentation

ALWAYS_314 (   clk_div   )

Always Construct

Definition at line 133 of file byte_lane.v.

Member Data Documentation

IODELAY_GRP "IODELAY_MEMORY"

Parameter

Definition at line 44 of file byte_lane.v.

IBUF_LOW_PWR "TRUE"

Parameter

Definition at line 45 of file byte_lane.v.

IOSTANDARD_DQ "SSTL15_T_DCI"

Parameter

Definition at line 46 of file byte_lane.v.

IOSTANDARD_DM "SSTL15"

Parameter

Definition at line 47 of file byte_lane.v.

IOSTANDARD_DQS "DIFF_SSTL15_T_DCI"

Parameter

Definition at line 48 of file byte_lane.v.

SLEW_DQ "SLOW"

Parameter

Definition at line 49 of file byte_lane.v.

SLEW_DQS "SLOW"

Parameter

Definition at line 50 of file byte_lane.v.

REFCLK_FREQUENCY 300 . 0

Parameter

Definition at line 51 of file byte_lane.v.

HIGH_PERFORMANCE_MODE "FALSE"

Parameter

Definition at line 52 of file byte_lane.v.

dq [ 7 : 0 ]

Inout

Definition at line 54 of file byte_lane.v.

dm

Output

Definition at line 56 of file byte_lane.v.

dqs

Inout

Definition at line 57 of file byte_lane.v.

ndqs

Inout

Definition at line 58 of file byte_lane.v.

clk

Input

Definition at line 59 of file byte_lane.v.

clk_div

Input

Definition at line 60 of file byte_lane.v.

inv_clk_div

Input

Definition at line 61 of file byte_lane.v.

rst

Input

Definition at line 62 of file byte_lane.v.

dci_disable_dqs

Input

Definition at line 63 of file byte_lane.v.

dci_disable_dq

Input

Definition at line 64 of file byte_lane.v.

din [ 31 : 0 ]

Input

Definition at line 65 of file byte_lane.v.

din_dm [ 3 : 0 ]

Input

Definition at line 66 of file byte_lane.v.

tin_dq [ 3 : 0 ]

Input

Definition at line 67 of file byte_lane.v.

din_dqs [ 3 : 0 ]

Input

Definition at line 68 of file byte_lane.v.

tin_dqs [ 3 : 0 ]

Input

Definition at line 69 of file byte_lane.v.

dout [ 31 : 0 ]

Output

Definition at line 70 of file byte_lane.v.

dly_data [ 7 : 0 ]

Input

Definition at line 71 of file byte_lane.v.

dly_addr [ 4 : 0 ]

Input

Definition at line 72 of file byte_lane.v.

ld_delay

Input

Definition at line 73 of file byte_lane.v.

set

Input

Definition at line 74 of file byte_lane.v.

dqs_read

Signal

Definition at line 77 of file byte_lane.v.

iclk

Signal

Definition at line 78 of file byte_lane.v.

din_r

Signal

Definition at line 79 of file byte_lane.v.

din_dm_r

Signal

Definition at line 84 of file byte_lane.v.

din_dqs_r

Signal

Definition at line 84 of file byte_lane.v.

tin_dq_r

Signal

Definition at line 84 of file byte_lane.v.

tin_dqs_r

Signal

Definition at line 84 of file byte_lane.v.

dly_data_r

Signal

Definition at line 88 of file byte_lane.v.

set_r

Signal

Definition at line 92 of file byte_lane.v.

dci_disable_dqs_r

Signal

Definition at line 96 of file byte_lane.v.

dci_disable_dq_r

Signal

Definition at line 96 of file byte_lane.v.

ld_odly

Signal

Definition at line 97 of file byte_lane.v.

ld_idly

Signal

Definition at line 97 of file byte_lane.v.

ld_odly_dqs

Signal

Definition at line 98 of file byte_lane.v.

ld_idly_dqs

Signal

Definition at line 98 of file byte_lane.v.

ld_odly_dm

Signal

Definition at line 98 of file byte_lane.v.

decode_sel

Signal

Definition at line 120 of file byte_lane.v.

BUFR iclk_i

Module Instance

Definition at line 100 of file byte_lane.v.

dm_single dm_i

Module Instance

Definition at line 178 of file byte_lane.v.

dq_single dq_i

Module Instance

Definition at line 151 of file byte_lane.v.

dqs_single dqs_i

Module Instance

Definition at line 199 of file byte_lane.v.

GENERATE [148]

GENERATE

Definition at line 148 of file byte_lane.v.

---

The documentation for this Module was generated from the following files:

• memctrl/phy/byte_lane.v