42 parameter FULL_HEIGHT =
0,
// number of lines in a frame. If 0 - wait to the VACT end, if > 0 - output immediately 50 parameter EMBED_LINES =
2,
// number of first lines containing embedded (non-image) data 52 parameter FIFO_LOGDEPTH =
12 // line FIFO address bits (includes sync+latency overhead) 58 input hact_in,
// should be multiple of 4 pixels 69 // localparam SYNC_EMBED = 4; 72 integer pre_lines;
// Number of lines left with "embedded" (not image) data 73 reg [
1:
0]
lane_pcntr;
// count input pixels to extend hact to 4*n if needed 78 reg [
48:
0]
fifo_di;
// msb: 0 - data,1 sync 82 reg next_line_pclk;
// triggers serial output of a line (generated at SOL and EOF, wait full line) 85 // wire pre_fifo_we_sof_sol_w = vact_d && ((FULL_HEIGHT > 0) ? ((next_sof && hact && !hact_d) || (hact_d && ! hact && (lines_left > 1))) 91 always @(
posedge pclk)
begin 96 always @(
posedge pclk)
begin 100 // pxd_d <= {pxd_d[35:0],pxd}; 138 // generate output clock (normally multiplier first, but in simulation there will be less calculations if division is first) 149 )
simul_clk_div_mult_i (
157 )
pulse_cross_clock_sof_sol_i (
168 )
pulse_cross_clock_sof_i (
181 wire [
3:
0]
rdy ;
// all lanes operate at the same time, only one rdy bit is used 193 for (
i=
0;
i <
4;
i=
i+
1)
begin:
cmprs_channel_block 201 )
par12_hispi_psp4l_lane_i (
211 // TODO: Add delays and diff out here? 214 reg [
1:
0]
frames_open;
// number of frames that are already started on input, but not yet finished on output //next_frame_oclk 234 )
sim_frac_clk_delay0_i (
243 )
sim_frac_clk_delay1_i (
251 )
sim_frac_clk_delay2_i (
259 )
sim_frac_clk_delay3_i (
274 )
sim_frac_clk_delay_clk_i (
293 parameter [
11:
0]
IDL =
12'h800,
316 // wire pause = seq_eol_sol[4] && !next_line; 320 always @ (
posedge clk)
begin 357 // else if (bcntr == 0) sr_in_av <= (|seq_sof[3:1]) || (|seq_eof[3:1]) || ((|seq_eol_sol[7:1]) && !pause);
[0:FIFO_DEPTH-1] 8762fifo_ramreg[48:0]
8760pre_fifo_we_data_wwire
8763fifo_wareg[FIFO_LOGDEPTH-1:0]
8758pre_fifo_we_eof_wwire
8740FIFO_DEPTH1 << FIFO_LOGDEPTH
simul_clk_div_mult_i simul_clk_mult_div
sim_frac_clk_delay_clk_i sim_frac_clk_delay
par12_hispi_psp4l_lane_i par12_hispi_psp4l_lane[generate]
8776lines_availablereg[1:0]
8772fifo_rareg[FIFO_LOGDEPTH-1:0]
8759pre_fifo_we_sof_sol_wwire
pulse_cross_clock_sof_i pulse_cross_clock