x393
1.0
FPGAcodeforElphelNC393camera
simul_clk_mult_div.v
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1
39
`timescale 1ns/1ps
40
41
module
simul_clk_mult_div
#(
42
parameter
MULTIPLIER
=
3
,
43
parameter
DIVISOR
=
5
,
44
parameter
SKIP_FIRST
=
5
45
) (
46
input
clk_in
,
47
input
en
,
48
output
clk_out
49
);
50
wire
clk_int
;
51
generate
52
if
(
MULTIPLIER
>
1
)
53
simul_clk_mult
#(
54
.
MULTIPLIER
(
MULTIPLIER
),
55
.
SKIP_FIRST
(
SKIP_FIRST
)
56
)
simul_clk_mult_i
(
57
.
clk_in
(
clk_in
),
// input
58
.
en
(
en
),
// input
59
.
clk_out
(
clk_int
)
// output
60
);
61
else
62
assign
clk_int
=
clk_in
;
63
endgenerate
64
generate
65
if
(
DIVISOR
>
1
)
66
sim_clk_div
#(
67
.
DIVISOR
(
DIVISOR
)
68
)
sim_clk_div_i
(
69
.
clk_in
(
clk_int
),
// input
70
.
en
(
en
),
// input
71
.
clk_out
(
clk_out
)
// output
72
);
73
else
74
assign
clk_out
=
clk_int
;
75
endgenerate
76
endmodule
77
simul_clk_mult_div
Definition:
simul_clk_mult_div.v:41
simul_clk_mult_div.9208clk_in
9208clk_in
Definition:
simul_clk_mult_div.v:46
simul_clk_mult_div.simul_clk_mult
simul_clk_mult_i simul_clk_mult[generate]
Definition:
simul_clk_mult_div.v:53
simul_clk_mult.9197en
9197en
Definition:
simul_clk_mult.v:46
simul_clk_mult_div.9209en
9209en
Definition:
simul_clk_mult_div.v:47
sim_clk_div.8810en
8810en
Definition:
sim_clk_div.v:45
simul_clk_mult.9196clk_in
9196clk_in
Definition:
simul_clk_mult.v:45
sim_clk_div.8811clk_out
8811clk_out
Definition:
sim_clk_div.v:46
simul_clk_mult.9198clk_out
9198clk_out
Definition:
simul_clk_mult.v:47
simul_clk_mult_div.9207SKIP_FIRST
9207SKIP_FIRST5
Definition:
simul_clk_mult_div.v:44
simul_clk_mult_div.9206DIVISOR
9206DIVISOR5
Definition:
simul_clk_mult_div.v:43
simul_clk_mult_div.9205MULTIPLIER
9205MULTIPLIER3
Definition:
simul_clk_mult_div.v:42
sim_clk_div.8809clk_in
8809clk_in
Definition:
sim_clk_div.v:44
simul_clk_mult_div.9211clk_int
9211clk_intwire
Definition:
simul_clk_mult_div.v:50
simul_clk_mult_div.sim_clk_div
sim_clk_div_i sim_clk_div[generate]
Definition:
simul_clk_mult_div.v:66
simul_clk_mult_div.9210clk_out
9210clk_out
Definition:
simul_clk_mult_div.v:48
simulation_modules
simul_clk_mult_div.v
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