huffman_snglclk.v

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  // This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES

  `define SYSTEM_DEFINES

  // TODO: Later compare instantiate/infer

  `define INSTANTIATE_DSP48E1

  `define DEBUG_DCT1D// undefine after debugging is over //  `define USE_OLD_DCT

  
// Parameters from x393_sata project

  `define USE_DRP

  `define ALIGN_CLOCKS

//  `define STRAIGHT_XCLK

  `define USE_DATASCOPE

//  `define DATASCOPE_INCOMING_RAW

  `define PRELOAD_BRAMS

//  `define AHCI_SATA 1

//  `define DEBUG_ELASTIC  

// End of parameters from x393_sata project

  
  `define PRELOAD_BRAMS

  `define DISPLAY_COMPRESSED_DATA    // if HISPI is not defined, parallel sensor interface is used for all channels

  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************///    `define USE_OLD_XDCT393  

//  `define USE_PCLK2X

//  `define USE_XCLK2X

  `define REVERSE_LANES 1  `define DEBUG_RING 1  `define USE_HARD_CURPARAMS// Adjustment of actual hardware may break simulation //  `define DEBUG_SENS_MEM_PAGES 1   

//  `define MCLK_VCO_MULT 16

// DDR3 memory speed grade and density

    `define sg25 1//  `define sg15E  1

//  `define sg187E  1

  `define den4096Mb 1    
  `define MCLK_VCO_MULT 16//  `define MCLK_VCO_MULT 18

//  `define MCLK_VCO_MULT 20

    
  `define MEMBRIDGE_DEBUG_WRITE 1// Enviroment-dependent options

  `ifdef IVERILOG

    `define SIMULATION

    `define OPEN_SOURCE_ONLY

  `endif

  
  `ifdef COCOTB

    `define SIMULATION

    `define OPEN_SOURCE_ONLY

  `endif

  
  `ifdef CVC

    `define SIMULATION

    `define OPEN_SOURCE_ONLY

  `endif // CVC

  
// will not use simultaneous reset in shift registers, just and input data with ~rst  

 `define SHREG_SEQUENTIAL_RESET 1// synthesis does to recognize global clock as G input of the primitive latch 

 `undef INFER_LATCHES

 // define when using CDC - it does not support them

 `undef IGNORE_ATTR

//`define MEMBRIDGE_DEBUG_READ 1

  `define use200Mhz 1  `define USE_CMD_ENCOD_TILED_32_RD 1    // chn 0 is read from memory and write to memory

 `define def_enable_mem_chn0

 `define def_read_mem_chn0

 `define def_write_mem_chn0

 `undef  def_scanline_chn0

 `undef  def_tiled_chn0

 
  // chn 1 is scanline r+w

 `define  def_enable_mem_chn1

 `define  def_read_mem_chn1

 `define  def_write_mem_chn1

 `define  def_scanline_chn1

 `undef   def_tiled_chn1


  // chn 2 is tiled r+w

 `define  def_enable_mem_chn2

 `define  def_read_mem_chn2

 `define  def_write_mem_chn2

 `undef   def_scanline_chn2

 `define  def_tiled_chn2


  // chn 3 is scanline r+w (reuse later)

 `define  def_enable_mem_chn3

 `define  def_read_mem_chn3

 `define  def_write_mem_chn3

 `define  def_scanline_chn3

 `undef   def_tiled_chn3


  // chn 4 is tiled r+w (reuse later)

 `define  def_enable_mem_chn4

 `define  def_read_mem_chn4

 `define  def_write_mem_chn4

 `undef   def_scanline_chn4

 `define  def_tiled_chn4


  // chn 5 is disabled

 `undef def_enable_mem_chn5


  // chn 6 is disabled

 `undef  def_enable_mem_chn6

 
  // chn 7 is disabled

 `undef  def_enable_mem_chn7

 
  // chn 8 is scanline w (sensor channel 0)

 `define  def_enable_mem_chn8

 `undef   def_read_mem_chn8

 `define  def_write_mem_chn8

 `define  def_scanline_chn8

 `undef   def_tiled_chn8


  // chn 9 is scanline w (sensor channel 1)

 `define  def_enable_mem_chn9

 `undef   def_read_mem_chn9

 `define  def_write_mem_chn9

 `define  def_scanline_chn9

 `undef   def_tiled_chn9


  // chn 10 is scanline w (sensor channel 2)

 `define  def_enable_mem_chn10

 `undef   def_read_mem_chn10

 `define  def_write_mem_chn10

 `define  def_scanline_chn10

 `undef   def_tiled_chn10


  // chn 11 is scanline w (sensor channel 3)

 `define  def_enable_mem_chn11

 `undef   def_read_mem_chn11

 `define  def_write_mem_chn11

 `define  def_scanline_chn11

 `undef   def_tiled_chn11


  // chn 12 is tiled read (compressor channel 0)

 `define  def_enable_mem_chn12

 `define  def_read_mem_chn12

 `undef   def_write_mem_chn12

 `undef   def_scanline_chn12

 `define  def_tiled_chn12

 
  // chn 12 is tiled read (compressor channel 1)

 `define  def_enable_mem_chn13

 `define  def_read_mem_chn13

 `undef   def_write_mem_chn13

 `undef   def_scanline_chn13

 `define  def_tiled_chn13

 
  // chn 12 is tiled read (compressor channel 2)

 `define  def_enable_mem_chn14

 `define  def_read_mem_chn14

 `undef   def_write_mem_chn14

 `undef   def_scanline_chn14

 `define  def_tiled_chn14

 
  // chn 12 is tiled read (compressor channel 3)

 `define  def_enable_mem_chn15

 `define  def_read_mem_chn15

 `undef   def_write_mem_chn15

 `undef   def_scanline_chn15

 `define  def_tiled_chn15

`endif
  
module huffman_snglclk    (
    input             xclk,            // pixel clock, sync to incoming data
    input             rst,             // @xclk
// Interface to program Huffman tables
    input             mclk,            // system clock to write tables
    input             tser_we,         // enable write to a  table
    input             tser_a_not_d,    // address/not data distributed to submodules
    input      [ 7:0] tser_d,          // byte-wide serialized tables address/data to submodules
    
// Input data     
    input      [15:0] di,              // [15:0]    specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
    input             ds,              // di valid strobe  (sync to xclk)
// Output data    
    output     [26:0] do27,            // [26:0]    output data, MSB aligned
    output     [ 4:0] dl,              // [4:0] data length 
    output            dv,              // output data valid
    
    output            flush,           // last block done - flush the rest bits
    output            last_block,
    output reg        test_lbw,
    output            gotLastBlock,    // last block done - flush the rest bits
    input             clk_flush,      // other clock to generate synchronized 1-cycle flush_clk output   
    output            flush_clk,       // 1-cycle flush output @ clk_flush
    output            fifo_or_full     // FIFO output register full - just for debuging
);

// A small input FIFO, only needed for RLL >16 that require several clock cycles to output

    reg         fifo_re_r;
    wire        fifo_rdy;
    wire        fifo_re = fifo_re_r && fifo_rdy;
    wire [15:0] fifo_out;
    fifo_same_clock #(
        .DATA_WIDTH(16),
        .DATA_DEPTH(4)
    ) fifo_same_clock_i (
        .rst       (1'b0), // input
        .clk       (xclk), // input
        .sync_rst  (rst), // input
        .we        (ds), // input
        .re        (fifo_re), // input
        .data_in   (di), // input[15:0] 
        .data_out  (fifo_out), // output[15:0] 
        .nempty    (fifo_rdy), // output
        .half_full () // output reg 
    );
    assign fifo_or_full = fifo_rdy;
    wire gotDC=           fifo_out[15] &&  fifo_out[14];
    wire gotAC=           fifo_out[15] && !fifo_out[14];
    wire gotRLL=         !fifo_out[15] && !fifo_out[12];
    wire gotEOB=         !fifo_out[15] &&  fifo_out[12];
    assign gotLastBlock=  fifo_out[15] &&  fifo_out[14] && fifo_out[12] && fifo_re;
    wire gotLastWord=    !fifo_out[14] &&  fifo_out[12] && fifo_re;    // (AC or RLL) and last bit set
    wire gotColor=        fifo_out[13];
    reg     [5:0] rll;      // 2 MSBs - counter to send "f0" codes
//    reg     [3:0] rll1;     // valid at cycle "1"
    wire    [3:0] rll_late; // match AC's length timing
    reg     [2:0] gotAC_r;
    reg     [2:0] gotDC_r;
    reg     [2:0] gotEOB_r;
    reg     [2:0] gotColor_r;
    reg     [2:1] gotF0_r;    
    
    reg    [11:0] sval;    // signed input value
    wire    [3:0] val_length;
    wire   [10:0] val_literal;
    reg     [8:0] htable_addr;     // address to huffman table
    reg     [2:0] htable_re;       // Huffman table memory re, regen, out valid
    wire   [31:0] htable_out;      // Only [19:0] are used
    wire    [3:0] val_length_late; // delay by 3 clocks to match Huffman table output
    wire   [10:0] val_literal_late;// delay by 3 clocks to match Huffman table output

    reg           ready_to_flush;
    
    reg            flush_r;           // last block done - flush the rest bits
    reg            last_block_r;
    reg     [9:0]  active_r;
    wire           active = fifo_re || active_r[0];
    
    assign flush =        flush_r;
    assign last_block =   last_block_r;
    assign fifo_or_full = fifo_rdy;
    
    always @(posedge xclk) begin
        if (rst) fifo_re_r <= 0;
        else     fifo_re_r <= fifo_rdy && !(fifo_re && gotRLL && (|fifo_out[5:4])) && !(|rll[5:4]);
    
        if (rst) gotAC_r <= 0;
        else     gotAC_r <= {gotAC_r[1:0], gotAC && fifo_re};
    
        if (rst) gotDC_r <= 0;
        else     gotDC_r <= {gotDC_r[1:0], gotDC && fifo_re};

        if (rst) gotEOB_r <= 0;
        else     gotEOB_r <= {gotEOB_r[1:0], gotEOB && fifo_re};

        if (rst) gotColor_r <= 0;
        else     gotColor_r <= {gotColor_r[1:0], (gotDC && fifo_re) ? gotColor : gotColor_r[0] };

        if      (rst)               rll[5:4] <= 0;
        else if (fifo_re && gotRLL) rll[5:4] <= fifo_out[5:4];
        else if (gotAC_r[0])        rll[5:4] <= 0; // combine with !en?
        else if (|rll[5:4])         rll[5:4] <=rll[5:4] - 1;
        
        if      (rst)               rll[3:0] <= 0;
        else if (fifo_re)           rll[3:0] <= gotRLL ? fifo_out[3:0] : 4'b0;
        
//        rll1 <= rll[3:0];
//        rll_late <= rll1;
        
        if (rst) gotF0_r[2:1] <= 0;
        else     gotF0_r[2:1] <= {gotF0_r[1], (|rll[5:4])};
        
//        if (fifo_re) sval[11:0] <= fifo_out[11:0];
        sval[11:0] <= fifo_out[11:0];
        
        htable_addr[8] <= gotColor_r[2];  // switch Huffman tables
        htable_addr[7:0] <= ({8{gotEOB_r[2]}} & 8'h0 )   | // generate 00 code (end of block)
                      ({8{gotF0_r[2]}}  & 8'hf0 )  | // generate f0 code (16 zeros)
                      ({8{gotDC_r[2]}}  & {val_length[3:0], 4'hf}) |
                      ({8{gotAC_r[2]}}  & {rll_late[3:0],       val_length[3:0]});
       
       if (rst)  htable_re <= 0;
       else      htable_re <= {htable_re[1:0], gotEOB_r[2] | gotF0_r[2] | gotDC_r[2] | gotAC_r[2]};

       // other signals
       
       if    (rst || flush_r)                 last_block_r <= 0;
       else if (gotLastBlock)                 last_block_r <= 1;
       
       if      (rst || flush_r)               ready_to_flush <= 0;
       else if (last_block_r &&  gotLastWord) ready_to_flush <= 1;

       test_lbw <= last_block &&  gotLastWord;
       
        if      (rst)     active_r <= 0;
        else if (fifo_re) active_r <= 10'h3ff;
        else              active_r <= active_r >> 1;
        
        if (rst) flush_r <= 0;
        else     flush_r <= ready_to_flush && !active && !flush_r;
        
    end

    varlen_encode_snglclk varlen_encode_snglclk_i (
        .clk     (xclk),       // input
        .d       (sval),       // input[11:0] 
        .l       (val_length), // output[3:0] reg 
        .q       (val_literal) // output[10:0] reg 
    );

    wire          twe;
    wire  [15:0]  tdi;
    wire  [22:0]  ta;
    
  
     table_ad_receive #(
        .MODE_16_BITS (1),
        .NUM_CHN      (1)
    ) table_ad_receive_i (
        .clk       (mclk),              // input
        .a_not_d   (tser_a_not_d),      // input
        .ser_d     (tser_d),            // input[7:0] 
        .dv        (tser_we),           // input
        .ta        (ta),                // output[22:0] 
        .td        (tdi),               // output[15:0] 
        .twe       (twe)                // output
    );

    ram18_var_w_var_r #(
        .REGISTERS(1),
        .LOG2WIDTH_WR(4),
        .LOG2WIDTH_RD(5),
        .DUMMY(0)
`ifdef PRELOAD_BRAMS, .INIT_00 (256'h000800F8000700780005001A0004000B0003000400020001000200000004000A)
, .INIT_01 (256'h00020000000000000000000000000000000000000010FF830010FF82000A03F6)
, .INIT_02 (256'h0010FF850010FF84000B07F6000901F6000700790005001B0004000C00000000)
, .INIT_03 (256'h00030002000000000000000000000000000000000010FF880010FF870010FF86)
, .INIT_04 (256'h0010FF8B0010FF8A0010FF89000C0FF4000A03F7000800F90005001C00000000)
, .INIT_05 (256'h00030003000000000000000000000000000000000010FF8E0010FF8D0010FF8C)
, .INIT_06 (256'h0010FF920010FF910010FF900010FF8F000C0FF5000901F70006003A00000000)
, .INIT_07 (256'h00030004000000000000000000000000000000000010FF950010FF940010FF93)
, .INIT_08 (256'h0010FF9A0010FF990010FF980010FF970010FF96000A03F80006003B00000000)
, .INIT_09 (256'h00030005000000000000000000000000000000000010FF9D0010FF9C0010FF9B)
, .INIT_0A (256'h0010FFA20010FFA10010FFA00010FF9F0010FF9E000B07F70007007A00000000)
, .INIT_0B (256'h00030006000000000000000000000000000000000010FFA50010FFA40010FFA3)
, .INIT_0C (256'h0010FFAA0010FFA90010FFA80010FFA70010FFA6000C0FF60007007B00000000)
, .INIT_0D (256'h0004000E000000000000000000000000000000000010FFAD0010FFAC0010FFAB)
, .INIT_0E (256'h0010FFB20010FFB10010FFB00010FFAF0010FFAE000C0FF7000800FA00000000)
, .INIT_0F (256'h0005001E000000000000000000000000000000000010FFB50010FFB40010FFB3)
, .INIT_10 (256'h0010FFBA0010FFB90010FFB80010FFB70010FFB6000F7FC0000901F800000000)
, .INIT_11 (256'h0006003E000000000000000000000000000000000010FFBD0010FFBC0010FFBB)
, .INIT_12 (256'h0010FFC30010FFC20010FFC10010FFC00010FFBF0010FFBE000901F900000000)
, .INIT_13 (256'h0007007E000000000000000000000000000000000010FFC60010FFC50010FFC4)
, .INIT_14 (256'h0010FFCC0010FFCB0010FFCA0010FFC90010FFC80010FFC7000901FA00000000)
, .INIT_15 (256'h000800FE000000000000000000000000000000000010FFCF0010FFCE0010FFCD)
, .INIT_16 (256'h0010FFD50010FFD40010FFD30010FFD20010FFD10010FFD0000A03F900000000)
, .INIT_17 (256'h000901FE000000000000000000000000000000000010FFD80010FFD70010FFD6)
, .INIT_18 (256'h0010FFDE0010FFDD0010FFDC0010FFDB0010FFDA0010FFD9000A03FA00000000)
, .INIT_19 (256'h00000000000000000000000000000000000000000010FFE10010FFE00010FFDF)
, .INIT_1A (256'h0010FFE70010FFE60010FFE50010FFE40010FFE30010FFE2000B07F800000000)
, .INIT_1B (256'h00000000000000000000000000000000000000000010FFEA0010FFE90010FFE8)
, .INIT_1C (256'h0010FFF10010FFF00010FFEF0010FFEE0010FFED0010FFEC0010FFEB00000000)
, .INIT_1D (256'h00000000000000000000000000000000000000000010FFF40010FFF30010FFF2)
, .INIT_1E (256'h0010FFFB0010FFFA0010FFF90010FFF80010FFF70010FFF60010FFF5000B07F9)
, .INIT_1F (256'h00000000000000000000000000000000000000000010FFFE0010FFFD0010FFFC)
, .INIT_20 (256'h000700780006003800050019000500180004000A000300040002000100020000)
, .INIT_21 (256'h0002000000000000000000000000000000000000000C0FF4000A03F6000901F4)
, .INIT_22 (256'h0010FF88000C0FF5000B07F6000901F5000800F6000600390004000B00000000)
, .INIT_23 (256'h00020001000000000000000000000000000000000010FF8B0010FF8A0010FF89)
, .INIT_24 (256'h0010FF8D0010FF8C000F7FC2000C0FF6000A03F7000800F70005001A00000000)
, .INIT_25 (256'h00020002000000000000000000000000000000000010FF900010FF8F0010FF8E)
, .INIT_26 (256'h0010FF930010FF920010FF91000C0FF7000A03F8000800F80005001B00000000)
, .INIT_27 (256'h00030006000000000000000000000000000000000010FF960010FF950010FF94)
, .INIT_28 (256'h0010FF9B0010FF9A0010FF990010FF980010FF97000901F60006003A00000000)
, .INIT_29 (256'h0004000E000000000000000000000000000000000010FF9E0010FF9D0010FF9C)
, .INIT_2A (256'h0010FFA30010FFA20010FFA10010FFA00010FF9F000A03F90006003B00000000)
, .INIT_2B (256'h0005001E000000000000000000000000000000000010FFA60010FFA50010FFA4)
, .INIT_2C (256'h0010FFAB0010FFAA0010FFA90010FFA80010FFA7000B07F70007007900000000)
, .INIT_2D (256'h0006003E000000000000000000000000000000000010FFAE0010FFAD0010FFAC)
, .INIT_2E (256'h0010FFB30010FFB20010FFB10010FFB00010FFAF000B07F80007007A00000000)
, .INIT_2F (256'h0007007E000000000000000000000000000000000010FFB60010FFB50010FFB4)
, .INIT_30 (256'h0010FFBC0010FFBB0010FFBA0010FFB90010FFB80010FFB7000800F900000000)
, .INIT_31 (256'h000800FE000000000000000000000000000000000010FFBF0010FFBE0010FFBD)
, .INIT_32 (256'h0010FFC50010FFC40010FFC30010FFC20010FFC10010FFC0000901F700000000)
, .INIT_33 (256'h000901FE000000000000000000000000000000000010FFC80010FFC70010FFC6)
, .INIT_34 (256'h0010FFCE0010FFCD0010FFCC0010FFCB0010FFCA0010FFC9000901F800000000)
, .INIT_35 (256'h000A03FE000000000000000000000000000000000010FFD10010FFD00010FFCF)
, .INIT_36 (256'h0010FFD70010FFD60010FFD50010FFD40010FFD30010FFD2000901F900000000)
, .INIT_37 (256'h000B07FE000000000000000000000000000000000010FFDA0010FFD90010FFD8)
, .INIT_38 (256'h0010FFE00010FFDF0010FFDE0010FFDD0010FFDC0010FFDB000901FA00000000)
, .INIT_39 (256'h00000000000000000000000000000000000000000010FFE30010FFE20010FFE1)
, .INIT_3A (256'h0010FFE90010FFE80010FFE70010FFE60010FFE50010FFE4000B07F900000000)
, .INIT_3B (256'h00000000000000000000000000000000000000000010FFEC0010FFEB0010FFEA)
, .INIT_3C (256'h0010FFF20010FFF10010FFF00010FFEF0010FFEE0010FFED000E3FE000000000)
, .INIT_3D (256'h00000000000000000000000000000000000000000010FFF50010FFF40010FFF3)
, .INIT_3E (256'h0010FFFB0010FFFA0010FFF90010FFF80010FFF70010FFF6000F7FC3000A03FA)
, .INIT_3F (256'h00000000000000000000000000000000000000000010FFFE0010FFFD0010FFFC)

`endif
    ) i_htab (
        .rclk      (xclk),             // input
        .raddr     (htable_addr[8:0]), // input[8:0] 
        .ren       (htable_re[0]),     // input
        .regen     (htable_re[1]),     // input
        .data_out  (htable_out),       // output[31:0] 
        .wclk      (mclk),             // input
        .waddr     (ta[9:0]),          // input[9:0] 
        .we        (twe),              // input
        .web       (4'hf),             // input[3:0] 
        .data_in   (tdi[15:0])         // input[15:0] 
    );

    dly_16 #(
        .WIDTH(11)
    ) dly_16_val_literal_i (
        .clk      (xclk),              // input
        .rst      (rst),              // input
        .dly      (4'h2),             // input[3:0] 
        .din      (val_literal),      // input[0:0] 
        .dout     (val_literal_late)  // output[0:0] 
    );

    dly_16 #(
        .WIDTH(4)
    ) dly_16_val_length_i (
        .clk      (xclk),                                            // input
        .rst      (rst),                                             // input
        .dly      (4'h2),                                            // input[3:0] 
        .din      ((gotEOB_r[2] | gotF0_r[2]) ? 4'b0 :  val_length), // input[0:0] 
        .dout     (val_length_late)                                  // output[0:0] 
    );

    dly_16 #(
        .WIDTH(4)
    ) dly_16_rll_late_i (
        .clk      (xclk),                                            // input
        .rst      (rst),                                             // input
        .dly      (4'h2),                                            // input[3:0] 
        .din      (rll[3:0]),                                        // input[0:0] 
        .dout     (rll_late)                                         // output[0:0] 
    );

    huffman_merge_code_literal huffman_merge_code_literal_i (
        .clk           (xclk),              // input
        .in_valid      (htable_re[2]),      // input
        .huff_code     (htable_out[15:0]),  // input[15:0] 
        .huff_code_len (htable_out[19:16]), // input[3:0] 
        .literal       (val_literal_late),  // input[10:0] 
        .literal_len   (val_length_late),   // input[3:0] 
        .out_valid     (dv),                // output reg 
        .out_bits      (do27),              // output[26:0] reg 
        .out_len       (dl)                 // output[4:0] reg 
    );
    pulse_cross_clock flush_clk_i (
        .rst       (rst),
        .src_clk   (xclk),
        .dst_clk   (clk_flush),
        .in_pulse  (flush),
        .out_pulse (flush_clk),
        .busy      ());
endmodule