varlen_encode_snglclk Module Reference

Inheritance diagram for varlen_encode_snglclk:

Static Public Member Functions

Always Constructs
ALWAYS_196	( clk )

Public Attributes

Inputs
clk
d	[ 11 : 0 ]

Outputs
l	reg [ 3 : 0 ]
q	reg [ 10 : 0 ]

Signals
reg[ 11 : 0 ]	d1
wire	this0
wire	this1
wire	this2
wire[ 1 : 0 ]	codel0
wire[ 1 : 0 ]	codel1
wire[ 1 : 0 ]	codel2
wire[ 3 : 0 ]	codel

Detailed Description

Definition at line 40 of file varlen_encode_snglclk.v.

Member Function Documentation

ALWAYS_196 (   clk   )

Always Construct

Definition at line 58 of file varlen_encode_snglclk.v.

Member Data Documentation

clk

Input

Definition at line 41 of file varlen_encode_snglclk.v.

d [ 11 : 0 ]

Input

Definition at line 42 of file varlen_encode_snglclk.v.

l reg [ 3 : 0 ]

Output

Definition at line 43 of file varlen_encode_snglclk.v.

q reg [ 10 : 0 ]

Output

Definition at line 44 of file varlen_encode_snglclk.v.

d1

Signal

Definition at line 46 of file varlen_encode_snglclk.v.

this0

Signal

Definition at line 48 of file varlen_encode_snglclk.v.

this1

Signal

Definition at line 49 of file varlen_encode_snglclk.v.

this2

Signal

Definition at line 50 of file varlen_encode_snglclk.v.

codel0

Signal

Definition at line 51 of file varlen_encode_snglclk.v.

codel1

Signal

Definition at line 52 of file varlen_encode_snglclk.v.

codel2

Signal

Definition at line 53 of file varlen_encode_snglclk.v.

codel

Signal

Definition at line 54 of file varlen_encode_snglclk.v.

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The documentation for this Module was generated from the following files:

• compressor_jp/varlen_encode_snglclk.v