mcntrl393 Member List

This is the complete list of members for mcntrl393, including all inherited members.

WIDTH	fifo_2regs	Parameter
mrst	fifo_2regs	Input
clk	fifo_2regs	Input
din	fifo_2regs	Input
wr	fifo_2regs	Input
rd	fifo_2regs	Input
srst	fifo_2regs	Input
dout	fifo_2regs	Output
full_out	fifo_2regs	Signal
full_in	fifo_2regs	Signal
reg_out	fifo_2regs	Signal
reg_in	fifo_2regs	Signal
DATA_WIDTH	fifo_same_clock	Parameter
DATA_DEPTH	fifo_same_clock	Parameter
rst	fifo_same_clock	Input
clk	fifo_same_clock	Input
sync_rst	fifo_same_clock	Input
we	fifo_same_clock	Input
re	fifo_same_clock	Input
data_in	fifo_same_clock	Input
data_out	fifo_same_clock	Output
nempty	fifo_same_clock	Output
half_full	fifo_same_clock	Output
DATA_2DEPTH	fifo_same_clock	Parameter
fill	fifo_same_clock	Signal
inreg	fifo_same_clock	Signal
outreg	fifo_same_clock	Signal
ra	fifo_same_clock	Signal
wa	fifo_same_clock	Signal
wem	fifo_same_clock	Signal
rem	fifo_same_clock	Signal
out_full	fifo_same_clock	Signal
ram	fifo_same_clock	Signal
ram_nempty	fifo_same_clock	Signal
mcntrl_tiled_rw.STATUS_REG_ADDR	status_generate	Parameter
mcntrl_ps_pio.STATUS_REG_ADDR	status_generate	Parameter
memctrl16.status_generate.STATUS_REG_ADDR	status_generate	Parameter
memctrl16.mcontr_sequencer.STATUS_REG_ADDR	status_generate	Parameter
mcntrl_tiled_rw.PAYLOAD_BITS	status_generate	Parameter
mcntrl_ps_pio.PAYLOAD_BITS	status_generate	Parameter
memctrl16.status_generate.PAYLOAD_BITS	status_generate	Parameter
memctrl16.mcontr_sequencer.PAYLOAD_BITS	status_generate	Parameter
mcntrl_tiled_rw.REGISTER_STATUS	status_generate	Parameter
mcntrl_ps_pio.REGISTER_STATUS	status_generate	Parameter
memctrl16.status_generate.REGISTER_STATUS	status_generate	Parameter
memctrl16.mcontr_sequencer.REGISTER_STATUS	status_generate	Parameter
mcntrl_tiled_rw.EXTRA_WORDS	status_generate	Parameter
mcntrl_ps_pio.EXTRA_WORDS	status_generate	Parameter
memctrl16.status_generate.EXTRA_WORDS	status_generate	Parameter
memctrl16.mcontr_sequencer.EXTRA_WORDS	status_generate	Parameter
mcntrl_tiled_rw.EXTRA_REG_ADDR	status_generate	Parameter
mcntrl_ps_pio.EXTRA_REG_ADDR	status_generate	Parameter
memctrl16.status_generate.EXTRA_REG_ADDR	status_generate	Parameter
memctrl16.mcontr_sequencer.EXTRA_REG_ADDR	status_generate	Parameter
mcntrl_tiled_rw.rst	status_generate	Input
mcntrl_ps_pio.rst	status_generate	Input
memctrl16.status_generate.rst	status_generate	Input
memctrl16.mcontr_sequencer.rst	status_generate	Input
mcntrl_tiled_rw.clk	status_generate	Input
mcntrl_ps_pio.clk	status_generate	Input
memctrl16.status_generate.clk	status_generate	Input
memctrl16.mcontr_sequencer.clk	status_generate	Input
mcntrl_tiled_rw.srst	status_generate	Input
mcntrl_ps_pio.srst	status_generate	Input
memctrl16.status_generate.srst	status_generate	Input
memctrl16.mcontr_sequencer.srst	status_generate	Input
mcntrl_tiled_rw.we	status_generate	Input
mcntrl_ps_pio.we	status_generate	Input
memctrl16.status_generate.we	status_generate	Input
memctrl16.mcontr_sequencer.we	status_generate	Input
mcntrl_tiled_rw.wd	status_generate	Input
mcntrl_ps_pio.wd	status_generate	Input
memctrl16.status_generate.wd	status_generate	Input
memctrl16.mcontr_sequencer.wd	status_generate	Input
mcntrl_tiled_rw.status	status_generate	Input
mcntrl_ps_pio.status	status_generate	Input
memctrl16.status_generate.status	status_generate	Input
memctrl16.mcontr_sequencer.status	status_generate	Input
mcntrl_tiled_rw.ad	status_generate	Output
mcntrl_ps_pio.ad	status_generate	Output
memctrl16.status_generate.ad	status_generate	Output
memctrl16.mcontr_sequencer.ad	status_generate	Output
mcntrl_tiled_rw.rq	status_generate	Output
mcntrl_ps_pio.rq	status_generate	Output
memctrl16.status_generate.rq	status_generate	Output
memctrl16.mcontr_sequencer.rq	status_generate	Output
mcntrl_tiled_rw.start	status_generate	Input
mcntrl_ps_pio.start	status_generate	Input
memctrl16.status_generate.start	status_generate	Input
memctrl16.mcontr_sequencer.start	status_generate	Input
mcntrl_tiled_rw.STATUS_BITS	status_generate	Parameter
mcntrl_ps_pio.STATUS_BITS	status_generate	Parameter
memctrl16.status_generate.STATUS_BITS	status_generate	Parameter
memctrl16.mcontr_sequencer.STATUS_BITS	status_generate	Parameter
mcntrl_tiled_rw.ALL_BITS	status_generate	Parameter
mcntrl_ps_pio.ALL_BITS	status_generate	Parameter
memctrl16.status_generate.ALL_BITS	status_generate	Parameter
memctrl16.mcontr_sequencer.ALL_BITS	status_generate	Parameter
rst	status_router16	Input
clk	status_router16	Input
srst	status_router16	Input
db_in0	status_router16	Input
rq_in0	status_router16	Input
start_in0	status_router16	Output
db_in1	status_router16	Input
rq_in1	status_router16	Input
start_in1	status_router16	Output
db_in2	status_router16	Input
rq_in2	status_router16	Input
start_in2	status_router16	Output
db_in3	status_router16	Input
rq_in3	status_router16	Input
start_in3	status_router16	Output
db_in4	status_router16	Input
rq_in4	status_router16	Input
start_in4	status_router16	Output
db_in5	status_router16	Input
rq_in5	status_router16	Input
start_in5	status_router16	Output
db_in6	status_router16	Input
rq_in6	status_router16	Input
start_in6	status_router16	Output
db_in7	status_router16	Input
rq_in7	status_router16	Input
start_in7	status_router16	Output
db_in8	status_router16	Input
rq_in8	status_router16	Input
start_in8	status_router16	Output
db_in9	status_router16	Input
rq_in9	status_router16	Input
start_in9	status_router16	Output
db_in10	status_router16	Input
rq_in10	status_router16	Input
start_in10	status_router16	Output
db_in11	status_router16	Input
rq_in11	status_router16	Input
start_in11	status_router16	Output
db_in12	status_router16	Input
rq_in12	status_router16	Input
start_in12	status_router16	Output
db_in13	status_router16	Input
rq_in13	status_router16	Input
start_in13	status_router16	Output
db_in14	status_router16	Input
rq_in14	status_router16	Input
start_in14	status_router16	Output
db_in15	status_router16	Input
rq_in15	status_router16	Input
start_in15	status_router16	Output
db_out	status_router16	Output
rq_out	status_router16	Output
start_out	status_router16	Input
db_int	status_router16	Signal
rq_int	status_router16	Signal
start_int	status_router16	Signal
FIFO_TYPE	status_router2	Parameter
rst	status_router2	Input
clk	status_router2	Input
srst	status_router2	Input
db_in0	status_router2	Input
rq_in0	status_router2	Input
start_in0	status_router2	Output
db_in1	status_router2	Input
rq_in1	status_router2	Input
start_in1	status_router2	Output
db_out	status_router2	Output
rq_out	status_router2	Output
start_out	status_router2	Input
rq_in	status_router2	Signal
start_rcv	status_router2	Signal
rcv_rest_r	status_router2	Signal
fifo_half_full	status_router2	Signal
fifo0_out	status_router2	Signal
fifo1_out	status_router2	Signal
fifo_last_byte	status_router2	Signal
fifo_nempty_pre	status_router2	Signal
fifo_nempty	status_router2	Signal
fifo_re	status_router2	Signal
next_chn	status_router2	Signal
current_chn_r	status_router2	Signal
snd_rest_r	status_router2	Signal
snd_pre_start	status_router2	Signal
snd_last_byte	status_router2	Signal
chn_sel_w	status_router2	Signal
early_chn	status_router2	Signal
set_other_only_w	status_router2	Signal
mcntrl_buf_wr.REGISTERS	ram_var_w_var_r	Parameter
mcntrl_ps_pio.REGISTERS	ram_var_w_var_r	Parameter
mcntrl_buf_wr.LOG2WIDTH_WR	ram_var_w_var_r	Parameter
mcntrl_ps_pio.LOG2WIDTH_WR	ram_var_w_var_r	Parameter
mcntrl_buf_wr.LOG2WIDTH_RD	ram_var_w_var_r	Parameter
mcntrl_ps_pio.LOG2WIDTH_RD	ram_var_w_var_r	Parameter
mcntrl_buf_wr.11862	ram_var_w_var_r	Parameter
mcntrl_ps_pio.11862	ram_var_w_var_r	Parameter
mcntrl_buf_wr.rclk	ram_var_w_var_r	Input
mcntrl_ps_pio.rclk	ram_var_w_var_r	Input
mcntrl_buf_wr.raddr	ram_var_w_var_r	Input
mcntrl_ps_pio.raddr	ram_var_w_var_r	Input
mcntrl_buf_wr.ren	ram_var_w_var_r	Input
mcntrl_ps_pio.ren	ram_var_w_var_r	Input
mcntrl_buf_wr.regen	ram_var_w_var_r	Input
mcntrl_ps_pio.regen	ram_var_w_var_r	Input
mcntrl_buf_wr.data_out	ram_var_w_var_r	Output
mcntrl_ps_pio.data_out	ram_var_w_var_r	Output
mcntrl_buf_wr.wclk	ram_var_w_var_r	Input
mcntrl_ps_pio.wclk	ram_var_w_var_r	Input
mcntrl_buf_wr.waddr	ram_var_w_var_r	Input
mcntrl_ps_pio.waddr	ram_var_w_var_r	Input
mcntrl_buf_wr.we	ram_var_w_var_r	Input
mcntrl_ps_pio.we	ram_var_w_var_r	Input
mcntrl_buf_wr.web	ram_var_w_var_r	Input
mcntrl_ps_pio.web	ram_var_w_var_r	Input
mcntrl_buf_wr.data_in	ram_var_w_var_r	Input
mcntrl_ps_pio.data_in	ram_var_w_var_r	Input
mrst	cmd_encod_4mux	Input
clk	cmd_encod_4mux	Input
start0	cmd_encod_4mux	Input
enc_cmd0	cmd_encod_4mux	Input
enc_wr0	cmd_encod_4mux	Input
enc_done0	cmd_encod_4mux	Input
start1	cmd_encod_4mux	Input
enc_cmd1	cmd_encod_4mux	Input
enc_wr1	cmd_encod_4mux	Input
enc_done1	cmd_encod_4mux	Input
start2	cmd_encod_4mux	Input
enc_cmd2	cmd_encod_4mux	Input
enc_wr2	cmd_encod_4mux	Input
enc_done2	cmd_encod_4mux	Input
start3	cmd_encod_4mux	Input
enc_cmd3	cmd_encod_4mux	Input
enc_wr3	cmd_encod_4mux	Input
enc_done3	cmd_encod_4mux	Input
start	cmd_encod_4mux	Output
enc_cmd	cmd_encod_4mux	Output
enc_wr	cmd_encod_4mux	Output
enc_done	cmd_encod_4mux	Output
select	cmd_encod_4mux	Signal
start_w	cmd_encod_4mux	Signal
ADDRESS_NUMBER	cmd_encod_linear_mux	Parameter
COLADDR_NUMBER	cmd_encod_linear_mux	Parameter
clk	cmd_encod_linear_mux	Input
bank1	cmd_encod_linear_mux	Input
row1	cmd_encod_linear_mux	Input
start_col1	cmd_encod_linear_mux	Input
num128_1	cmd_encod_linear_mux	Input
partial1	cmd_encod_linear_mux	Input
start1_rd	cmd_encod_linear_mux	Input
start1_wr	cmd_encod_linear_mux	Input
bank3	cmd_encod_linear_mux	Input
row3	cmd_encod_linear_mux	Input
start_col3	cmd_encod_linear_mux	Input
num128_3	cmd_encod_linear_mux	Input
partial3	cmd_encod_linear_mux	Input
start3_rd	cmd_encod_linear_mux	Input
start3_wr	cmd_encod_linear_mux	Input
bank8	cmd_encod_linear_mux	Input
row8	cmd_encod_linear_mux	Input
start_col8	cmd_encod_linear_mux	Input
num128_8	cmd_encod_linear_mux	Input
partial8	cmd_encod_linear_mux	Input
start8_wr	cmd_encod_linear_mux	Input
bank9	cmd_encod_linear_mux	Input
row9	cmd_encod_linear_mux	Input
start_col9	cmd_encod_linear_mux	Input
num128_9	cmd_encod_linear_mux	Input
partial9	cmd_encod_linear_mux	Input
start9_wr	cmd_encod_linear_mux	Input
bank10	cmd_encod_linear_mux	Input
row10	cmd_encod_linear_mux	Input
start_col10	cmd_encod_linear_mux	Input
num128_10	cmd_encod_linear_mux	Input
partial10	cmd_encod_linear_mux	Input
start10_wr	cmd_encod_linear_mux	Input
bank11	cmd_encod_linear_mux	Input
row11	cmd_encod_linear_mux	Input
start_col11	cmd_encod_linear_mux	Input
num128_11	cmd_encod_linear_mux	Input
partial11	cmd_encod_linear_mux	Input
start11_wr	cmd_encod_linear_mux	Input
bank	cmd_encod_linear_mux	Output
row	cmd_encod_linear_mux	Output
start_col	cmd_encod_linear_mux	Output
num128	cmd_encod_linear_mux	Output
partial	cmd_encod_linear_mux	Output
start_rd	cmd_encod_linear_mux	Output
start_wr	cmd_encod_linear_mux	Output
bank_r	cmd_encod_linear_mux	Signal
row_r	cmd_encod_linear_mux	Signal
start_col_r	cmd_encod_linear_mux	Signal
num128_r	cmd_encod_linear_mux	Signal
partial_r	cmd_encod_linear_mux	Signal
start_rd_r	cmd_encod_linear_mux	Signal
start_wr_r	cmd_encod_linear_mux	Signal
bank_w	cmd_encod_linear_mux	Signal
row_w	cmd_encod_linear_mux	Signal
start_col_w	cmd_encod_linear_mux	Signal
num128_w	cmd_encod_linear_mux	Signal
partial_w	cmd_encod_linear_mux	Signal
start_rd_w	cmd_encod_linear_mux	Signal
start_wr_w	cmd_encod_linear_mux	Signal
PAR_WIDTH	cmd_encod_linear_mux	Parameter
PAR_DEFAULT	cmd_encod_linear_mux	Parameter
ADDRESS_NUMBER	cmd_encod_linear_rw	Parameter
COLADDR_NUMBER	cmd_encod_linear_rw	Parameter
NUM_XFER_BITS	cmd_encod_linear_rw	Parameter
CMD_PAUSE_BITS	cmd_encod_linear_rw	Parameter
CMD_DONE_BIT	cmd_encod_linear_rw	Parameter
RSEL	cmd_encod_linear_rw	Parameter
WSEL	cmd_encod_linear_rw	Parameter
mrst	cmd_encod_linear_rw	Input
clk	cmd_encod_linear_rw	Input
bank_in	cmd_encod_linear_rw	Input
row_in	cmd_encod_linear_rw	Input
start_col	cmd_encod_linear_rw	Input
num128_in	cmd_encod_linear_rw	Input
skip_next_page_in	cmd_encod_linear_rw	Input
start_rd	cmd_encod_linear_rw	Input
start_wr	cmd_encod_linear_rw	Input
start	cmd_encod_linear_rw	Output
enc_cmd	cmd_encod_linear_rw	Output
enc_wr	cmd_encod_linear_rw	Output
enc_done	cmd_encod_linear_rw	Output
enc_cmd_rd	cmd_encod_linear_rw	Signal
enc_wr_rd	cmd_encod_linear_rw	Signal
enc_done_rd	cmd_encod_linear_rw	Signal
enc_cmd_wr	cmd_encod_linear_rw	Signal
enc_wr_wr	cmd_encod_linear_rw	Signal
enc_done_wr	cmd_encod_linear_rw	Signal
select_wr	cmd_encod_linear_rw	Signal
ADDRESS_NUMBER	cmd_encod_tiled_32_rw	Parameter
COLADDR_NUMBER	cmd_encod_tiled_32_rw	Parameter
CMD_PAUSE_BITS	cmd_encod_tiled_32_rw	Parameter
CMD_DONE_BIT	cmd_encod_tiled_32_rw	Parameter
FRAME_WIDTH_BITS	cmd_encod_tiled_32_rw	Parameter
RSEL	cmd_encod_tiled_32_rw	Parameter
WSEL	cmd_encod_tiled_32_rw	Parameter
mrst	cmd_encod_tiled_32_rw	Input
clk	cmd_encod_tiled_32_rw	Input
start_bank	cmd_encod_tiled_32_rw	Input
start_row	cmd_encod_tiled_32_rw	Input
start_col	cmd_encod_tiled_32_rw	Input
rowcol_inc_in	cmd_encod_tiled_32_rw	Input
num_rows_in_m1	cmd_encod_tiled_32_rw	Input
num_cols_in_m1	cmd_encod_tiled_32_rw	Input
keep_open_in	cmd_encod_tiled_32_rw	Input
skip_next_page_in	cmd_encod_tiled_32_rw	Input
start_rd	cmd_encod_tiled_32_rw	Input
start_wr	cmd_encod_tiled_32_rw	Input
start	cmd_encod_tiled_32_rw	Output
enc_cmd	cmd_encod_tiled_32_rw	Output
enc_wr	cmd_encod_tiled_32_rw	Output
enc_done	cmd_encod_tiled_32_rw	Output
enc_cmd_rd	cmd_encod_tiled_32_rw	Signal
enc_wr_rd	cmd_encod_tiled_32_rw	Signal
enc_done_rd	cmd_encod_tiled_32_rw	Signal
enc_cmd_wr	cmd_encod_tiled_32_rw	Signal
enc_wr_wr	cmd_encod_tiled_32_rw	Signal
enc_done_wr	cmd_encod_tiled_32_rw	Signal
select_wr	cmd_encod_tiled_32_rw	Signal
ADDRESS_NUMBER	cmd_encod_tiled_mux	Parameter
COLADDR_NUMBER	cmd_encod_tiled_mux	Parameter
FRAME_WIDTH_BITS	cmd_encod_tiled_mux	Parameter
MAX_TILE_WIDTH	cmd_encod_tiled_mux	Parameter
MAX_TILE_HEIGHT	cmd_encod_tiled_mux	Parameter
clk	cmd_encod_tiled_mux	Input
bank2	cmd_encod_tiled_mux	Input
row2	cmd_encod_tiled_mux	Input
col2	cmd_encod_tiled_mux	Input
rowcol_inc2	cmd_encod_tiled_mux	Input
num_rows2	cmd_encod_tiled_mux	Input
num_cols2	cmd_encod_tiled_mux	Input
keep_open2	cmd_encod_tiled_mux	Input
partial2	cmd_encod_tiled_mux	Input
start2_rd	cmd_encod_tiled_mux	Input
start2_rd32	cmd_encod_tiled_mux	Input
start2_wr	cmd_encod_tiled_mux	Input
start2_wr32	cmd_encod_tiled_mux	Input
bank4	cmd_encod_tiled_mux	Input
row4	cmd_encod_tiled_mux	Input
col4	cmd_encod_tiled_mux	Input
rowcol_inc4	cmd_encod_tiled_mux	Input
num_rows4	cmd_encod_tiled_mux	Input
num_cols4	cmd_encod_tiled_mux	Input
keep_open4	cmd_encod_tiled_mux	Input
partial4	cmd_encod_tiled_mux	Input
start4_rd	cmd_encod_tiled_mux	Input
start4_rd32	cmd_encod_tiled_mux	Input
start4_wr	cmd_encod_tiled_mux	Input
start4_wr32	cmd_encod_tiled_mux	Input
bank12	cmd_encod_tiled_mux	Input
row12	cmd_encod_tiled_mux	Input
col12	cmd_encod_tiled_mux	Input
rowcol_inc12	cmd_encod_tiled_mux	Input
num_rows12	cmd_encod_tiled_mux	Input
num_cols12	cmd_encod_tiled_mux	Input
keep_open12	cmd_encod_tiled_mux	Input
partial12	cmd_encod_tiled_mux	Input
start12_rd	cmd_encod_tiled_mux	Input
start12_rd32	cmd_encod_tiled_mux	Input
bank13	cmd_encod_tiled_mux	Input
row13	cmd_encod_tiled_mux	Input
col13	cmd_encod_tiled_mux	Input
rowcol_inc13	cmd_encod_tiled_mux	Input
num_rows13	cmd_encod_tiled_mux	Input
num_cols13	cmd_encod_tiled_mux	Input
keep_open13	cmd_encod_tiled_mux	Input
partial13	cmd_encod_tiled_mux	Input
start13_rd	cmd_encod_tiled_mux	Input
start13_rd32	cmd_encod_tiled_mux	Input
bank14	cmd_encod_tiled_mux	Input
row14	cmd_encod_tiled_mux	Input
col14	cmd_encod_tiled_mux	Input
rowcol_inc14	cmd_encod_tiled_mux	Input
num_rows14	cmd_encod_tiled_mux	Input
num_cols14	cmd_encod_tiled_mux	Input
keep_open14	cmd_encod_tiled_mux	Input
partial14	cmd_encod_tiled_mux	Input
start14_rd	cmd_encod_tiled_mux	Input
start14_rd32	cmd_encod_tiled_mux	Input
bank15	cmd_encod_tiled_mux	Input
row15	cmd_encod_tiled_mux	Input
col15	cmd_encod_tiled_mux	Input
rowcol_inc15	cmd_encod_tiled_mux	Input
num_rows15	cmd_encod_tiled_mux	Input
num_cols15	cmd_encod_tiled_mux	Input
keep_open15	cmd_encod_tiled_mux	Input
partial15	cmd_encod_tiled_mux	Input
start15_rd	cmd_encod_tiled_mux	Input
start15_rd32	cmd_encod_tiled_mux	Input
bank	cmd_encod_tiled_mux	Output
row	cmd_encod_tiled_mux	Output
col	cmd_encod_tiled_mux	Output
rowcol_inc	cmd_encod_tiled_mux	Output
num_rows	cmd_encod_tiled_mux	Output
num_cols	cmd_encod_tiled_mux	Output
keep_open	cmd_encod_tiled_mux	Output
partial	cmd_encod_tiled_mux	Output
start_rd	cmd_encod_tiled_mux	Output
start_wr	cmd_encod_tiled_mux	Output
start_rd32	cmd_encod_tiled_mux	Output
start_wr32	cmd_encod_tiled_mux	Output
bank_r	cmd_encod_tiled_mux	Signal
row_r	cmd_encod_tiled_mux	Signal
col_r	cmd_encod_tiled_mux	Signal
rowcol_inc_r	cmd_encod_tiled_mux	Signal
num_rows_r	cmd_encod_tiled_mux	Signal
num_cols_r	cmd_encod_tiled_mux	Signal
keep_open_r	cmd_encod_tiled_mux	Signal
partial_r	cmd_encod_tiled_mux	Signal
start_rd_r	cmd_encod_tiled_mux	Signal
start_wr_r	cmd_encod_tiled_mux	Signal
start_rd32_r	cmd_encod_tiled_mux	Signal
start_wr32_r	cmd_encod_tiled_mux	Signal
bank_w	cmd_encod_tiled_mux	Signal
row_w	cmd_encod_tiled_mux	Signal
col_w	cmd_encod_tiled_mux	Signal
rowcol_inc_w	cmd_encod_tiled_mux	Signal
num_rows_w	cmd_encod_tiled_mux	Signal
num_cols_w	cmd_encod_tiled_mux	Signal
keep_open_w	cmd_encod_tiled_mux	Signal
partial_w	cmd_encod_tiled_mux	Signal
start_rd_w	cmd_encod_tiled_mux	Signal
start_wr_w	cmd_encod_tiled_mux	Signal
start_rd32_w	cmd_encod_tiled_mux	Signal
start_wr32_w	cmd_encod_tiled_mux	Signal
PAR_WIDTH	cmd_encod_tiled_mux	Parameter
PAR_DEFAULT	cmd_encod_tiled_mux	Parameter
ADDRESS_NUMBER	cmd_encod_tiled_rw	Parameter
COLADDR_NUMBER	cmd_encod_tiled_rw	Parameter
CMD_PAUSE_BITS	cmd_encod_tiled_rw	Parameter
CMD_DONE_BIT	cmd_encod_tiled_rw	Parameter
FRAME_WIDTH_BITS	cmd_encod_tiled_rw	Parameter
RSEL	cmd_encod_tiled_rw	Parameter
WSEL	cmd_encod_tiled_rw	Parameter
mrst	cmd_encod_tiled_rw	Input
clk	cmd_encod_tiled_rw	Input
start_bank	cmd_encod_tiled_rw	Input
start_row	cmd_encod_tiled_rw	Input
start_col	cmd_encod_tiled_rw	Input
rowcol_inc_in	cmd_encod_tiled_rw	Input
num_rows_in_m1	cmd_encod_tiled_rw	Input
num_cols_in_m1	cmd_encod_tiled_rw	Input
keep_open_in	cmd_encod_tiled_rw	Input
skip_next_page_in	cmd_encod_tiled_rw	Input
start_rd	cmd_encod_tiled_rw	Input
start_wr	cmd_encod_tiled_rw	Input
start	cmd_encod_tiled_rw	Output
enc_cmd	cmd_encod_tiled_rw	Output
enc_wr	cmd_encod_tiled_rw	Output
enc_done	cmd_encod_tiled_rw	Output
enc_cmd_rd	cmd_encod_tiled_rw	Signal
enc_wr_rd	cmd_encod_tiled_rw	Signal
enc_done_rd	cmd_encod_tiled_rw	Signal
enc_cmd_wr	cmd_encod_tiled_rw	Signal
enc_wr_wr	cmd_encod_tiled_rw	Signal
enc_done_wr	cmd_encod_tiled_rw	Signal
select_wr	cmd_encod_tiled_rw	Signal
MCONTR_SENS_BASE	mcntrl393
MCONTR_SENS_INC	mcntrl393
MCONTR_CMPRS_BASE	mcntrl393
MCONTR_CMPRS_INC	mcntrl393
MCONTR_SENS_STATUS_BASE	mcntrl393
MCONTR_SENS_STATUS_INC	mcntrl393
MCONTR_CMPRS_STATUS_BASE	mcntrl393
MCONTR_CMPRS_STATUS_INC	mcntrl393
MCONTR_WR_MASK	mcntrl393
MCONTR_RD_MASK	mcntrl393
MCONTR_CMD_WR_ADDR	mcntrl393
MCONTR_BUF0_RD_ADDR	mcntrl393
MCONTR_BUF0_WR_ADDR	mcntrl393
MCONTR_BUF2_RD_ADDR	mcntrl393
MCONTR_BUF2_WR_ADDR	mcntrl393
MCONTR_BUF3_RD_ADDR	mcntrl393
MCONTR_BUF3_WR_ADDR	mcntrl393
MCONTR_BUF4_RD_ADDR	mcntrl393
MCONTR_BUF4_WR_ADDR	mcntrl393
AXI_WR_ADDR_BITS	mcntrl393
AXI_RD_ADDR_BITS	mcntrl393
DLY_LD	mcntrl393
DLY_LD_MASK	mcntrl393
MCONTR_PHY_0BIT_ADDR	mcntrl393
MCONTR_PHY_0BIT_ADDR_MASK	mcntrl393
MCONTR_PHY_0BIT_DLY_SET	mcntrl393
MCONTR_PHY_0BIT_CMDA_EN	mcntrl393
MCONTR_PHY_0BIT_SDRST_ACT	mcntrl393
MCONTR_PHY_0BIT_CKE_EN	mcntrl393
MCONTR_PHY_0BIT_DCI_RST	mcntrl393
MCONTR_PHY_0BIT_DLY_RST	mcntrl393
MCONTR_TOP_0BIT_ADDR	mcntrl393
MCONTR_TOP_0BIT_ADDR_MASK	mcntrl393
MCONTR_TOP_0BIT_MCONTR_EN	mcntrl393
MCONTR_TOP_0BIT_REFRESH_EN	mcntrl393
MCONTR_PHY_16BIT_ADDR	mcntrl393
MCONTR_PHY_16BIT_ADDR_MASK	mcntrl393
MCONTR_PHY_16BIT_PATTERNS	mcntrl393
MCONTR_PHY_16BIT_PATTERNS_TRI	mcntrl393
MCONTR_PHY_16BIT_WBUF_DELAY	mcntrl393
MCONTR_PHY_16BIT_EXTRA	mcntrl393
MCONTR_PHY_STATUS_CNTRL	mcntrl393
MCONTR_ARBIT_ADDR	mcntrl393
MCONTR_ARBIT_ADDR_MASK	mcntrl393
MCONTR_TOP_16BIT_ADDR	mcntrl393
MCONTR_TOP_16BIT_ADDR_MASK	mcntrl393
MCONTR_TOP_16BIT_CHN_EN	mcntrl393
MCONTR_TOP_16BIT_REFRESH_PERIOD	mcntrl393
MCONTR_TOP_16BIT_REFRESH_ADDRESS	mcntrl393
MCONTR_TOP_16BIT_STATUS_CNTRL	mcntrl393
MCONTR_PHY_STATUS_REG_ADDR	mcntrl393
MCONTR_TOP_STATUS_REG_ADDR	mcntrl393
CHNBUF_READ_LATENCY	mcntrl393
DFLT_DQS_PATTERN	mcntrl393
DFLT_DQM_PATTERN	mcntrl393
DFLT_DQ_TRI_ON_PATTERN	mcntrl393
DFLT_DQ_TRI_OFF_PATTERN	mcntrl393
DFLT_DQS_TRI_ON_PATTERN	mcntrl393
DFLT_DQS_TRI_OFF_PATTERN	mcntrl393
DFLT_WBUF_DELAY	mcntrl393
DFLT_INV_CLK_DIV	mcntrl393
DFLT_CHN_EN	mcntrl393
DFLT_REFRESH_ADDR	mcntrl393
DFLT_REFRESH_PERIOD	mcntrl393
ADDRESS_NUMBER	mcntrl393
COLADDR_NUMBER	mcntrl393
PHASE_WIDTH	mcntrl393
SLEW_DQ	mcntrl393
SLEW_DQS	mcntrl393
SLEW_CMDA	mcntrl393
SLEW_CLK	mcntrl393
IBUF_LOW_PWR	mcntrl393
REFCLK_FREQUENCY	mcntrl393
HIGH_PERFORMANCE_MODE	mcntrl393
CLKIN_PERIOD	mcntrl393
CLKFBOUT_MULT	mcntrl393
DIVCLK_DIVIDE	mcntrl393
CLKFBOUT_USE_FINE_PS	mcntrl393
CLKFBOUT_PHASE	mcntrl393
SDCLK_PHASE	mcntrl393
CLK_PHASE	mcntrl393
CLK_DIV_PHASE	mcntrl393
MCLK_PHASE	mcntrl393
REF_JITTER1	mcntrl393
SS_EN	mcntrl393
SS_MODE	mcntrl393
SS_MOD_PERIOD	mcntrl393
CMD_PAUSE_BITS	mcntrl393
CMD_DONE_BIT	mcntrl393
MCNTRL_PS_ADDR	mcntrl393
MCNTRL_PS_MASK	mcntrl393
MCNTRL_PS_STATUS_REG_ADDR	mcntrl393
MCNTRL_PS_EN_RST	mcntrl393
MCNTRL_PS_CMD	mcntrl393
MCNTRL_PS_STATUS_CNTRL	mcntrl393
NUM_XFER_BITS	mcntrl393
FRAME_WIDTH_BITS	mcntrl393
FRAME_HEIGHT_BITS	mcntrl393
LAST_FRAME_BITS	mcntrl393
MCNTRL_SCANLINE_CHN1_ADDR	mcntrl393
MCNTRL_SCANLINE_CHN3_ADDR	mcntrl393
MCNTRL_SCANLINE_MASK	mcntrl393
MCNTRL_SCANLINE_MODE	mcntrl393
MCNTRL_SCANLINE_STATUS_CNTRL	mcntrl393
MCNTRL_SCANLINE_STARTADDR	mcntrl393
MCNTRL_SCANLINE_FRAME_SIZE	mcntrl393
MCNTRL_SCANLINE_FRAME_LAST	mcntrl393
MCNTRL_SCANLINE_FRAME_FULL_WIDTH	mcntrl393
MCNTRL_SCANLINE_WINDOW_WH	mcntrl393
MCNTRL_SCANLINE_WINDOW_X0Y0	mcntrl393
MCNTRL_SCANLINE_WINDOW_STARTXY	mcntrl393
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR	mcntrl393
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR	mcntrl393
MCNTRL_SCANLINE_PENDING_CNTR_BITS	mcntrl393
MCNTRL_SCANLINE_FRAME_PAGE_RESET	mcntrl393
MAX_TILE_WIDTH	mcntrl393
MAX_TILE_HEIGHT	mcntrl393
MCNTRL_TILED_CHN2_ADDR	mcntrl393
MCNTRL_TILED_CHN4_ADDR	mcntrl393
MCNTRL_TILED_MASK	mcntrl393
MCNTRL_TILED_MODE	mcntrl393
MCNTRL_TILED_STATUS_CNTRL	mcntrl393
MCNTRL_TILED_STARTADDR	mcntrl393
MCNTRL_TILED_FRAME_SIZE	mcntrl393
MCNTRL_TILED_FRAME_LAST	mcntrl393
MCNTRL_TILED_FRAME_FULL_WIDTH	mcntrl393
MCNTRL_TILED_WINDOW_WH	mcntrl393
MCNTRL_TILED_WINDOW_X0Y0	mcntrl393
MCNTRL_TILED_WINDOW_STARTXY	mcntrl393
MCNTRL_TILED_TILE_WHS	mcntrl393
MCNTRL_TILED_STATUS_REG_CHN2_ADDR	mcntrl393
MCNTRL_TILED_STATUS_REG_CHN4_ADDR	mcntrl393
MCNTRL_TILED_PENDING_CNTR_BITS	mcntrl393
MCNTRL_TILED_FRAME_PAGE_RESET	mcntrl393
BUFFER_DEPTH32	mcntrl393
RSEL	mcntrl393
WSEL	mcntrl393
MCONTR_LINTILE_NRESET	mcntrl393
MCONTR_LINTILE_EN	mcntrl393
MCONTR_LINTILE_WRITE	mcntrl393
MCONTR_LINTILE_EXTRAPG	mcntrl393
MCONTR_LINTILE_EXTRAPG_BITS	mcntrl393
MCONTR_LINTILE_KEEP_OPEN	mcntrl393
MCONTR_LINTILE_BYTE32	mcntrl393
MCONTR_LINTILE_RST_FRAME	mcntrl393
MCONTR_LINTILE_SINGLE	mcntrl393
MCONTR_LINTILE_REPEAT	mcntrl393
MCONTR_LINTILE_DIS_NEED	mcntrl393
MCONTR_LINTILE_SKIP_LATE	mcntrl393
rst_in	mcntrl393
clk_in	mcntrl393
mclk	mcntrl393
mrst	mcntrl393
locked	mcntrl393
ref_clk	mcntrl393
idelay_ctrl_reset	mcntrl393
cmd_ad	mcntrl393
cmd_stb	mcntrl393
status_ad	mcntrl393
status_rq	mcntrl393
status_start	mcntrl393
axi_clk	mcntrl393
axiwr_pre_awaddr	mcntrl393
axiwr_start_burst	mcntrl393
axiwr_waddr	mcntrl393
axiwr_wen	mcntrl393
axiwr_data	mcntrl393
axird_pre_araddr	mcntrl393
axird_start_burst	mcntrl393
axird_raddr	mcntrl393
axird_ren	mcntrl393
axird_regen	mcntrl393
axird_rdata	mcntrl393
axird_selected	mcntrl393
sens_sof	mcntrl393
sens_frame_run	mcntrl393
sens_rpage_set	mcntrl393
sens_rpage_next	mcntrl393
sens_buf_rd	mcntrl393
sens_buf_dout	mcntrl393
sens_page_written	mcntrl393
sens_xfer_skipped	mcntrl393
sens_first_wr_in_frame	mcntrl393
cmprs_xfer_reset_page_rd	mcntrl393
cmprs_buf_wpage_nxt	mcntrl393
cmprs_buf_we	mcntrl393
cmprs_buf_din	mcntrl393
cmprs_page_ready	mcntrl393
cmprs_next_page	mcntrl393
cmprs_first_rd_in_frame	mcntrl393
cmprs_frame_start_dst	mcntrl393
cmprs_line_unfinished_src	mcntrl393
cmprs_frame_number_src	mcntrl393
cmprs_frame_done_src	mcntrl393
cmprs_line_unfinished_dst	mcntrl393
cmprs_frame_number_dst	mcntrl393
cmprs_frame_done_dst	mcntrl393
cmprs_suspend	mcntrl393
frame_start_chn1	mcntrl393
next_page_chn1	mcntrl393
cmd_wrmem_chn1	mcntrl393
page_ready_chn1	mcntrl393
frame_done_chn1	mcntrl393
line_unfinished_chn1	mcntrl393
suspend_chn1	mcntrl393
xfer_reset_page1_rd	mcntrl393
buf_wpage_nxt_chn1	mcntrl393
buf_wr_chn1	mcntrl393
buf_wdata_chn1	mcntrl393
xfer_reset_page1_wr	mcntrl393
rpage_nxt_chn1	mcntrl393
buf_rd_chn1	mcntrl393
buf_rdata_chn1	mcntrl393
frame_start_chn2	mcntrl393
next_page_chn2	mcntrl393
page_ready_chn2	mcntrl393
frame_done_chn2	mcntrl393
line_unfinished_chn2	mcntrl393
frame_number_chn2	mcntrl393
suspend_chn2	mcntrl393
frame_start_chn3	mcntrl393
next_page_chn3	mcntrl393
page_ready_chn3	mcntrl393
frame_done_chn3	mcntrl393
line_unfinished_chn3	mcntrl393
frame_number_chn3	mcntrl393
suspend_chn3	mcntrl393
frame_start_chn4	mcntrl393
next_page_chn4	mcntrl393
page_ready_chn4	mcntrl393
frame_done_chn4	mcntrl393
line_unfinished_chn4	mcntrl393
frame_number_chn4	mcntrl393
suspend_chn4	mcntrl393
SDRST	mcntrl393
SDCLK	mcntrl393
SDNCLK	mcntrl393
SDA	mcntrl393
SDBA	mcntrl393
SDWE	mcntrl393
SDRAS	mcntrl393
SDCAS	mcntrl393
SDCKE	mcntrl393
SDODT	mcntrl393
SDD	mcntrl393
SDDML	mcntrl393
DQSL	mcntrl393
NDQSL	mcntrl393
SDDMU	mcntrl393
DQSU	mcntrl393
NDQSU	mcntrl393
tmp_debug	mcntrl393
COL_WDTH	mcntrl393
FRAME_WBP1	mcntrl393
want_rq0	mcntrl393
need_rq0	mcntrl393
channel_pgm_en0	mcntrl393
reject0	mcntrl393
seq_data0	mcntrl393
seq_set0	mcntrl393
seq_done0	mcntrl393
buf_wr_chn0	mcntrl393
buf_wpage_nxt_chn0	mcntrl393
buf_run0	mcntrl393
buf_wdata_chn0	mcntrl393
buf_wrun0	mcntrl393
buf_rd_chn0	mcntrl393
buf_rpage_nxt_chn0	mcntrl393
buf_rdata_chn0	mcntrl393
want_rq1	mcntrl393
need_rq1	mcntrl393
channel_pgm_en1	mcntrl393
reject1	mcntrl393
seq_done1	mcntrl393
want_rq2	mcntrl393
need_rq2	mcntrl393
channel_pgm_en2	mcntrl393
reject2	mcntrl393
seq_done2	mcntrl393
buf_wr_chn2	mcntrl393
buf_wpage_nxt_chn2	mcntrl393
buf_wdata_chn2	mcntrl393
buf_rd_chn2	mcntrl393
rpage_nxt_chn2	mcntrl393
buf_rdata_chn2	mcntrl393
want_rq3	mcntrl393
need_rq3	mcntrl393
channel_pgm_en3	mcntrl393
reject3	mcntrl393
seq_done3	mcntrl393
buf_wr_chn3	mcntrl393
buf_wpage_nxt_chn3	mcntrl393
buf_wdata_chn3	mcntrl393
buf_rd_chn3	mcntrl393
rpage_nxt_chn3	mcntrl393
buf_rdata_chn3	mcntrl393
want_rq4	mcntrl393
need_rq4	mcntrl393
channel_pgm_en4	mcntrl393
reject4	mcntrl393
seq_done4	mcntrl393
buf_wr_chn4	mcntrl393
buf_wpage_nxt_chn4	mcntrl393
buf_wdata_chn4	mcntrl393
buf_rd_chn4	mcntrl393
rpage_nxt_chn4	mcntrl393
buf_rdata_chn4	mcntrl393
cmd_mcontr_ad	mcntrl393
cmd_mcontr_stb	mcntrl393
cmd_ps_pio_ad	mcntrl393
cmd_ps_pio_stb	mcntrl393
cmd_scanline_chn1_ad	mcntrl393
cmd_scanline_chn1_stb	mcntrl393
cmd_scanline_chn3_ad	mcntrl393
cmd_scanline_chn3_stb	mcntrl393
cmd_tiled_chn2_ad	mcntrl393
cmd_tiled_chn2_stb	mcntrl393
cmd_tiled_chn4_ad	mcntrl393
cmd_tiled_chn4_stb	mcntrl393
cmd_sens_ad	mcntrl393
cmd_sens_stb	mcntrl393
cmd_cmprs_ad	mcntrl393
cmd_cmprs_stb	mcntrl393
status_mcontr_ad	mcntrl393
status_mcontr_rq	mcntrl393
status_mcontr_start	mcntrl393
status_ps_pio_ad	mcntrl393
status_ps_pio_rq	mcntrl393
status_ps_pio_start	mcntrl393
status_scanline_chn1_ad	mcntrl393
status_scanline_chn1_rq	mcntrl393
status_scanline_chn1_start	mcntrl393
status_scanline_chn3_ad	mcntrl393
status_scanline_chn3_rq	mcntrl393
status_scanline_chn3_start	mcntrl393
status_tiled_chn2_ad	mcntrl393
status_tiled_chn2_rq	mcntrl393
status_tiled_chn2_start	mcntrl393
status_tiled_chn4_ad	mcntrl393
status_tiled_chn4_rq	mcntrl393
status_tiled_chn4_start	mcntrl393
status_sens_ad	mcntrl393
status_sens_rq	mcntrl393
status_sens_start	mcntrl393
status_cmprs_ad	mcntrl393
status_cmprs_rq	mcntrl393
status_cmprs_start	mcntrl393
sens_want	mcntrl393
sens_need	mcntrl393
cmprs_want	mcntrl393
cmprs_need	mcntrl393
sens_channel_pgm_en	mcntrl393
sens_reject	mcntrl393
sens_start_wr	mcntrl393
sens_bank	mcntrl393
sens_row	mcntrl393
sens_col	mcntrl393
sens_num128	mcntrl393
sens_partial	mcntrl393
sens_seq_done	mcntrl393
cmprs_channel_pgm_en	mcntrl393
cmprs_reject	mcntrl393
cmprs_start_rd16	mcntrl393
cmprs_start_rd32	mcntrl393
cmprs_bank	mcntrl393
cmprs_row	mcntrl393
cmprs_col	mcntrl393
cmprs_rowcol_inc	mcntrl393
cmprs_num_rows_m1	mcntrl393
cmprs_num_cols_m1	mcntrl393
cmprs_keep_open	mcntrl393
cmprs_partial	mcntrl393
cmprs_seq_done	mcntrl393
select_cmd0_w	mcntrl393
select_buf0rd_w	mcntrl393
select_buf0wr_w	mcntrl393
select_buf2rd_w	mcntrl393
select_buf2wr_w	mcntrl393
select_buf3rd_w	mcntrl393
select_buf3wr_w	mcntrl393
select_buf4rd_w	mcntrl393
select_buf4wr_w	mcntrl393
select_cmd0	mcntrl393
select_buf0rd	mcntrl393
select_buf0wr	mcntrl393
select_buf2rd	mcntrl393
select_buf2wr	mcntrl393
select_buf3rd	mcntrl393
select_buf3wr	mcntrl393
select_buf4rd	mcntrl393
select_buf4wr	mcntrl393
select_buf0rd_d	mcntrl393
select_buf2rd_d	mcntrl393
select_buf3rd_d	mcntrl393
select_buf4rd_d	mcntrl393
axird_selected_r	mcntrl393
buf_waddr	mcntrl393
buf_wdata	mcntrl393
cmd_we	mcntrl393
buf0wr_we	mcntrl393
buf2wr_we	mcntrl393
buf3wr_we	mcntrl393
buf4wr_we	mcntrl393
buf_raddr	mcntrl393
buf0_data	mcntrl393
buf2rd_data	mcntrl393
buf3rd_data	mcntrl393
buf4rd_data	mcntrl393
buf0_rd	mcntrl393
buf0_regen	mcntrl393
buf2rd_rd	mcntrl393
buf2rd_regen	mcntrl393
buf3rd_rd	mcntrl393
buf3rd_regen	mcntrl393
buf4rd_rd	mcntrl393
buf4rd_regen	mcntrl393
lin_rw_bank	mcntrl393
lin_rw_row	mcntrl393
lin_rw_col	mcntrl393
lin_rw_num128	mcntrl393
lin_rw_xfer_partial	mcntrl393
lin_rw_start_rd	mcntrl393
lin_rw_start_wr	mcntrl393
lin_rw_chn1_bank	mcntrl393
lin_rw_chn1_row	mcntrl393
lin_rw_chn1_col	mcntrl393
lin_rw_chn1_num128	mcntrl393
lin_rw_chn1_partial	mcntrl393
lin_rw_chn1_start_rd	mcntrl393
lin_rw_chn1_start_wr	mcntrl393
lin_rw_chn3_bank	mcntrl393
lin_rw_chn3_row	mcntrl393
lin_rw_chn3_col	mcntrl393
lin_rw_chn3_num128	mcntrl393
lin_rw_chn3_partial	mcntrl393
lin_rw_chn3_start_rd	mcntrl393
lin_rw_chn3_start_wr	mcntrl393
xfer_reset_page3_wr	mcntrl393
xfer_reset_page3_rd	mcntrl393
tiled_rw_bank	mcntrl393
tiled_rw_row	mcntrl393
tiled_rw_col	mcntrl393
tiled_rw_rowcol_inc	mcntrl393
tiled_rw_num_rows_m1	mcntrl393
tiled_rw_num_cols_m1	mcntrl393
tiled_rw_keep_open	mcntrl393
tiled_rw_xfer_partial	mcntrl393
tiled_rw_chn2_bank	mcntrl393
tiled_rw_chn2_row	mcntrl393
tiled_rw_chn2_col	mcntrl393
tiled_rw_chn2_rowcol_inc	mcntrl393
tiled_rw_chn2_num_rows_m1	mcntrl393
tiled_rw_chn2_num_cols_m1	mcntrl393
tiled_rw_chn2_keep_open	mcntrl393
tiled_rw_chn2_xfer_partial	mcntrl393
tiled_rw_chn2_start_rd16	mcntrl393
tiled_rw_chn2_start_wr16	mcntrl393
tiled_rw_chn2_start_rd32	mcntrl393
tiled_rw_chn2_start_wr32	mcntrl393
xfer_reset_page2_wr	mcntrl393
xfer_reset_page2_rd	mcntrl393
tiled_rw_chn4_bank	mcntrl393
tiled_rw_chn4_row	mcntrl393
tiled_rw_chn4_col	mcntrl393
tiled_rw_chn4_rowcol_inc	mcntrl393
tiled_rw_chn4_num_rows_m1	mcntrl393
tiled_rw_chn4_num_cols_m1	mcntrl393
tiled_rw_chn4_keep_open	mcntrl393
tiled_rw_chn4_xfer_partial	mcntrl393
tiled_rw_chn4_start_rd16	mcntrl393
tiled_rw_chn4_start_wr16	mcntrl393
tiled_rw_chn4_start_rd32	mcntrl393
tiled_rw_chn4_start_wr32	mcntrl393
xfer_reset_page4_wr	mcntrl393
xfer_reset_page4_rd	mcntrl393
seq_data	mcntrl393
seq_wr	mcntrl393
seq_set	mcntrl393
encod_linear_start_out	mcntrl393
encod_linear_cmd	mcntrl393
encod_linear_wr	mcntrl393
encod_linear_done	mcntrl393
encod_tiled16_start_out	mcntrl393
encod_tiled16_cmd	mcntrl393
encod_tiled16_wr	mcntrl393
encod_tiled16_done	mcntrl393
encod_tiled32_start_out	mcntrl393
encod_tiled32_cmd	mcntrl393
encod_tiled32_wr	mcntrl393
encod_tiled32_done	mcntrl393
tiled_rw_start_rd16	mcntrl393
tiled_rw_start_wr16	mcntrl393
tiled_rw_start_rd32	mcntrl393
tiled_rw_start_wr32	mcntrl393
sens_first_wr_pending_r	mcntrl393
cmprs_first_rd_pending_r	mcntrl393
mcntrl_buf_rd.LOG2WIDTH_RD	mcntrl_buf_rd	Parameter
mcntrl_ps_pio.LOG2WIDTH_RD	mcntrl_buf_rd	Parameter
mcntrl_buf_rd.ext_clk	mcntrl_buf_rd	Input
mcntrl_ps_pio.ext_clk	mcntrl_buf_rd	Input
mcntrl_buf_rd.ext_raddr	mcntrl_buf_rd	Input
mcntrl_ps_pio.ext_raddr	mcntrl_buf_rd	Input
mcntrl_buf_rd.ext_rd	mcntrl_buf_rd	Input
mcntrl_ps_pio.ext_rd	mcntrl_buf_rd	Input
mcntrl_buf_rd.ext_regen	mcntrl_buf_rd	Input
mcntrl_ps_pio.ext_regen	mcntrl_buf_rd	Input
mcntrl_buf_rd.ext_data_out	mcntrl_buf_rd	Output
mcntrl_ps_pio.ext_data_out	mcntrl_buf_rd	Output
mcntrl_buf_rd.wclk	mcntrl_buf_rd	Input
mcntrl_ps_pio.wclk	mcntrl_buf_rd	Input
mcntrl_buf_rd.wpage_in	mcntrl_buf_rd	Input
mcntrl_ps_pio.wpage_in	mcntrl_buf_rd	Input
mcntrl_buf_rd.wpage_set	mcntrl_buf_rd	Input
mcntrl_ps_pio.wpage_set	mcntrl_buf_rd	Input
mcntrl_buf_rd.page_next	mcntrl_buf_rd	Input
mcntrl_ps_pio.page_next	mcntrl_buf_rd	Input
mcntrl_buf_rd.page	mcntrl_buf_rd	Output
mcntrl_ps_pio.page	mcntrl_buf_rd	Output
mcntrl_buf_rd.we	mcntrl_buf_rd	Input
mcntrl_ps_pio.we	mcntrl_buf_rd	Input
mcntrl_buf_rd.data_in	mcntrl_buf_rd	Input
mcntrl_ps_pio.data_in	mcntrl_buf_rd	Input
mcntrl_buf_rd.page_r	mcntrl_buf_rd	Signal
mcntrl_ps_pio.page_r	mcntrl_buf_rd	Signal
mcntrl_buf_rd.waddr	mcntrl_buf_rd	Signal
mcntrl_ps_pio.waddr	mcntrl_buf_rd	Signal
mcntrl_buf_wr.LOG2WIDTH_WR	mcntrl_buf_wr	Parameter
mcntrl_ps_pio.LOG2WIDTH_WR	mcntrl_buf_wr	Parameter
mcntrl_buf_wr.ext_clk	mcntrl_buf_wr	Input
mcntrl_ps_pio.ext_clk	mcntrl_buf_wr	Input
mcntrl_buf_wr.ext_waddr	mcntrl_buf_wr	Input
mcntrl_ps_pio.ext_waddr	mcntrl_buf_wr	Input
mcntrl_buf_wr.ext_we	mcntrl_buf_wr	Input
mcntrl_ps_pio.ext_we	mcntrl_buf_wr	Input
mcntrl_buf_wr.ext_data_in	mcntrl_buf_wr	Input
mcntrl_ps_pio.ext_data_in	mcntrl_buf_wr	Input
mcntrl_buf_wr.rclk	mcntrl_buf_wr	Input
mcntrl_ps_pio.rclk	mcntrl_buf_wr	Input
mcntrl_buf_wr.rpage_in	mcntrl_buf_wr	Input
mcntrl_ps_pio.rpage_in	mcntrl_buf_wr	Input
mcntrl_buf_wr.rpage_set	mcntrl_buf_wr	Input
mcntrl_ps_pio.rpage_set	mcntrl_buf_wr	Input
mcntrl_buf_wr.page_next	mcntrl_buf_wr	Input
mcntrl_ps_pio.page_next	mcntrl_buf_wr	Input
mcntrl_buf_wr.page	mcntrl_buf_wr	Output
mcntrl_ps_pio.page	mcntrl_buf_wr	Output
mcntrl_buf_wr.rd	mcntrl_buf_wr	Input
mcntrl_ps_pio.rd	mcntrl_buf_wr	Input
mcntrl_buf_wr.data_out	mcntrl_buf_wr	Output
mcntrl_ps_pio.data_out	mcntrl_buf_wr	Output
mcntrl_buf_wr.page_r	mcntrl_buf_wr	Signal
mcntrl_ps_pio.page_r	mcntrl_buf_wr	Signal
mcntrl_buf_wr.raddr	mcntrl_buf_wr	Signal
mcntrl_ps_pio.raddr	mcntrl_buf_wr	Signal
mcntrl_buf_wr.regen	mcntrl_buf_wr	Signal
mcntrl_ps_pio.regen	mcntrl_buf_wr	Signal
ADDRESS_NUMBER	mcntrl_linear_rw	Parameter
COLADDR_NUMBER	mcntrl_linear_rw	Parameter
NUM_XFER_BITS	mcntrl_linear_rw	Parameter
FRAME_WIDTH_BITS	mcntrl_linear_rw	Parameter
FRAME_HEIGHT_BITS	mcntrl_linear_rw	Parameter
LAST_FRAME_BITS	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_ADDR	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_MASK	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_MODE	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_STATUS_CNTRL	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_STARTADDR	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_FRAME_SIZE	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_FRAME_LAST	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_FRAME_FULL_WIDTH	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_WINDOW_WH	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_WINDOW_X0Y0	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_WINDOW_STARTXY	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_STATUS_REG_ADDR	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_PENDING_CNTR_BITS	mcntrl_linear_rw	Parameter
MCNTRL_SCANLINE_FRAME_PAGE_RESET	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_NRESET	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_EN	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_WRITE	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_EXTRAPG	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_EXTRAPG_BITS	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_RST_FRAME	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_SINGLE	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_REPEAT	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_DIS_NEED	mcntrl_linear_rw	Parameter
MCONTR_LINTILE_SKIP_LATE	mcntrl_linear_rw	Parameter
mrst	mcntrl_linear_rw	Input
mclk	mcntrl_linear_rw	Input
cmd_ad	mcntrl_linear_rw	Input
cmd_stb	mcntrl_linear_rw	Input
status_ad	mcntrl_linear_rw	Output
status_rq	mcntrl_linear_rw	Output
status_start	mcntrl_linear_rw	Input
frame_start	mcntrl_linear_rw	Input
frame_run	mcntrl_linear_rw	Output
next_page	mcntrl_linear_rw	Input
frame_done	mcntrl_linear_rw	Output
frame_finished	mcntrl_linear_rw	Output
line_unfinished	mcntrl_linear_rw	Output
suspend	mcntrl_linear_rw	Input
frame_number	mcntrl_linear_rw	Output
xfer_want	mcntrl_linear_rw	Output
xfer_need	mcntrl_linear_rw	Output
xfer_grant	mcntrl_linear_rw	Input
xfer_reject	mcntrl_linear_rw	Output
xfer_start_rd	mcntrl_linear_rw	Output
xfer_start_wr	mcntrl_linear_rw	Output
xfer_bank	mcntrl_linear_rw	Output
xfer_row	mcntrl_linear_rw	Output
xfer_col	mcntrl_linear_rw	Output
xfer_num128	mcntrl_linear_rw	Output
xfer_partial	mcntrl_linear_rw	Output
xfer_done	mcntrl_linear_rw	Input
xfer_page_rst_wr	mcntrl_linear_rw	Output
xfer_page_rst_rd	mcntrl_linear_rw	Output
xfer_skipped	mcntrl_linear_rw	Output
cmd_wrmem	mcntrl_linear_rw	Output
NUM_RC_BURST_BITS	mcntrl_linear_rw	Parameter
MPY_WIDTH	mcntrl_linear_rw	Parameter
PAR_MOD_LATENCY	mcntrl_linear_rw	Parameter
curr_x	mcntrl_linear_rw	Signal
curr_y	mcntrl_linear_rw	Signal
next_y	mcntrl_linear_rw	Signal
line_start_addr	mcntrl_linear_rw	Signal
frame_y	mcntrl_linear_rw	Signal
frame_x	mcntrl_linear_rw	Signal
frame_y8_r	mcntrl_linear_rw	Signal
frame_full_width_r	mcntrl_linear_rw	Signal
mul_rslt	mcntrl_linear_rw	Signal
start_addr_r	mcntrl_linear_rw	Signal
bank_reg	mcntrl_linear_rw	Signal
mul_rslt_w	mcntrl_linear_rw	Signal
row_left	mcntrl_linear_rw	Signal
last_in_row	mcntrl_linear_rw	Signal
mem_page_left	mcntrl_linear_rw	Signal
line_start_page_left	mcntrl_linear_rw	Signal
lim_by_xfer	mcntrl_linear_rw	Signal
remainder_in_xfer	mcntrl_linear_rw	Signal
continued_xfer	mcntrl_linear_rw	Signal
leftover	mcntrl_linear_rw	Signal
xfer_num128_r	mcntrl_linear_rw	Signal
pgm_param_w	mcntrl_linear_rw	Signal
xfer_start_r	mcntrl_linear_rw	Signal
xfer_start_rd_r	mcntrl_linear_rw	Signal
xfer_start_wr_r	mcntrl_linear_rw	Signal
par_mod_r	mcntrl_linear_rw	Signal
recalc_r	mcntrl_linear_rw	Signal
calc_valid	mcntrl_linear_rw	Signal
chn_en	mcntrl_linear_rw	Signal
chn_rst	mcntrl_linear_rw	Signal
chn_rst_d	mcntrl_linear_rw	Signal
xfer_page_rst_r	mcntrl_linear_rw	Signal
xfer_page_rst_pos	mcntrl_linear_rw	Signal
xfer_page_rst_neg	mcntrl_linear_rw	Signal
page_cntr	mcntrl_linear_rw	Signal
cmd_extra_pages	mcntrl_linear_rw	Signal
skip_too_late	mcntrl_linear_rw	Signal
disable_need	mcntrl_linear_rw	Signal
repeat_frames	mcntrl_linear_rw	Signal
single_frame_w	mcntrl_linear_rw	Signal
rst_frame_num_w	mcntrl_linear_rw	Signal
single_frame_r	mcntrl_linear_rw	Signal
rst_frame_num_r	mcntrl_linear_rw	Signal
frame_en	mcntrl_linear_rw	Signal
busy_r	mcntrl_linear_rw	Signal
want_r	mcntrl_linear_rw	Signal
need_r	mcntrl_linear_rw	Signal
frame_done_r	mcntrl_linear_rw	Signal
frame_finished_r	mcntrl_linear_rw	Signal
last_in_row_w	mcntrl_linear_rw	Signal
last_row_w	mcntrl_linear_rw	Signal
last_block	mcntrl_linear_rw	Signal
pending_xfers	mcntrl_linear_rw	Signal
row_col_r	mcntrl_linear_rw	Signal
line_unfinished_relw_r	mcntrl_linear_rw	Signal
line_unfinished_r	mcntrl_linear_rw	Signal
pre_want	mcntrl_linear_rw	Signal
pre_want_r1	mcntrl_linear_rw	Signal
status_data	mcntrl_linear_rw	Signal
cmd_a	mcntrl_linear_rw	Signal
cmd_data	mcntrl_linear_rw	Signal
cmd_we	mcntrl_linear_rw	Signal
set_mode_w	mcntrl_linear_rw	Signal
set_status_w	mcntrl_linear_rw	Signal
set_start_addr_w	mcntrl_linear_rw	Signal
set_frame_size_w	mcntrl_linear_rw	Signal
set_last_frame_w	mcntrl_linear_rw	Signal
set_frame_width_w	mcntrl_linear_rw	Signal
set_window_wh_w	mcntrl_linear_rw	Signal
set_window_x0y0_w	mcntrl_linear_rw	Signal
set_window_start_w	mcntrl_linear_rw	Signal
lsw13_zero	mcntrl_linear_rw	Signal
msw_zero	mcntrl_linear_rw	Signal
mode_reg	mcntrl_linear_rw	Signal
start_range_addr	mcntrl_linear_rw	Signal
frame_size	mcntrl_linear_rw	Signal
last_frame_number	mcntrl_linear_rw	Signal
start_addr	mcntrl_linear_rw	Signal
next_frame_start_addr	mcntrl_linear_rw	Signal
frame_number_cntr	mcntrl_linear_rw	Signal
frame_number_current	mcntrl_linear_rw	Signal
is_last_frame	mcntrl_linear_rw	Signal
frame_start_r	mcntrl_linear_rw	Signal
frame_full_width	mcntrl_linear_rw	Signal
window_width	mcntrl_linear_rw	Signal
window_height	mcntrl_linear_rw	Signal
window_x0	mcntrl_linear_rw	Signal
window_y0	mcntrl_linear_rw	Signal
start_x	mcntrl_linear_rw	Signal
start_y	mcntrl_linear_rw	Signal
xfer_done_d	mcntrl_linear_rw	Signal
EXTRA_BITS	mcntrl_linear_rw	Parameter
i	mcntrl_linear_rw	Signal
xfer_limited_by_mem_page	mcntrl_linear_rw	Signal
xfer_limited_by_mem_page_r	mcntrl_linear_rw	Signal
start_skip_w	mcntrl_linear_rw	Signal
start_skip_r	mcntrl_linear_rw	Signal
skip_run	mcntrl_linear_rw	Signal
xfer_reject_r	mcntrl_linear_rw	Signal
frame_start_pending	mcntrl_linear_rw	Signal
frame_start_pending_long	mcntrl_linear_rw	Signal
xfer_done_skipped	mcntrl_linear_rw	Signal
frame_start_delayed	mcntrl_linear_rw	Signal
frame_start_mod	mcntrl_linear_rw	Signal
start_not_partial	mcntrl_linear_rw	Signal
MCNTRL_PS_ADDR	mcntrl_ps_pio	Parameter
MCNTRL_PS_MASK	mcntrl_ps_pio	Parameter
MCNTRL_PS_STATUS_REG_ADDR	mcntrl_ps_pio	Parameter
MCNTRL_PS_EN_RST	mcntrl_ps_pio	Parameter
MCNTRL_PS_CMD	mcntrl_ps_pio	Parameter
MCNTRL_PS_STATUS_CNTRL	mcntrl_ps_pio	Parameter
mrst	mcntrl_ps_pio	Input
mclk	mcntrl_ps_pio	Input
cmd_ad	mcntrl_ps_pio	Input
cmd_stb	mcntrl_ps_pio	Input
status_ad	mcntrl_ps_pio	Output
status_rq	mcntrl_ps_pio	Output
status_start	mcntrl_ps_pio	Input
port0_clk	mcntrl_ps_pio	Input
port0_re	mcntrl_ps_pio	Input
port0_regen	mcntrl_ps_pio	Input
port0_addr	mcntrl_ps_pio	Input
port0_data	mcntrl_ps_pio	Output
port1_clk	mcntrl_ps_pio	Input
port1_we	mcntrl_ps_pio	Input
port1_addr	mcntrl_ps_pio	Input
port1_data	mcntrl_ps_pio	Input
want_rq	mcntrl_ps_pio	Output
need_rq	mcntrl_ps_pio	Output
channel_pgm_en	mcntrl_ps_pio	Input
seq_data	mcntrl_ps_pio	Output
seq_set	mcntrl_ps_pio	Output
seq_done	mcntrl_ps_pio	Input
buf_wr	mcntrl_ps_pio	Input
buf_wpage_nxt	mcntrl_ps_pio	Input
buf_run	mcntrl_ps_pio	Input
buf_wrun	mcntrl_ps_pio	Input
buf_wdata	mcntrl_ps_pio	Input
buf_rpage_nxt	mcntrl_ps_pio	Input
buf_rd	mcntrl_ps_pio	Input
buf_rdata	mcntrl_ps_pio	Output
CMD_WIDTH	mcntrl_ps_pio	Parameter
CMD_FIFO_DEPTH	mcntrl_ps_pio	Parameter
PAGE_FIFO_DEPTH	mcntrl_ps_pio	Parameter
PAGE_CNTR_BITS	mcntrl_ps_pio	Parameter
pending_pages	mcntrl_ps_pio	Signal
cmd_a	mcntrl_ps_pio	Signal
cmd_data	mcntrl_ps_pio	Signal
cmd_we	mcntrl_ps_pio	Signal
status_data	mcntrl_ps_pio	Signal
cmd_out	mcntrl_ps_pio	Signal
cmd_nempty	mcntrl_ps_pio	Signal
cmd_half_full	mcntrl_ps_pio	Signal
set_cmd_w	mcntrl_ps_pio	Signal
set_status_w	mcntrl_ps_pio	Signal
set_en_rst	mcntrl_ps_pio	Signal
en_reset	mcntrl_ps_pio	Signal
chn_rst	mcntrl_ps_pio	Signal
chn_en	mcntrl_ps_pio	Signal
busy	mcntrl_ps_pio	Signal
short_busy	mcntrl_ps_pio	Signal
start	mcntrl_ps_pio	Signal
cmd_set_d	mcntrl_ps_pio	Signal
cmd_seq_a	mcntrl_ps_pio	Signal
cmd_page	mcntrl_ps_pio	Signal
cmd_need	mcntrl_ps_pio	Signal
cmd_wr	mcntrl_ps_pio	Signal
cmd_wait	mcntrl_ps_pio	Signal
cmd_set	mcntrl_ps_pio	Signal
cmd_wait_r	mcntrl_ps_pio	Signal
page_out	mcntrl_ps_pio	Signal
nreset_page_fifo	mcntrl_ps_pio	Signal
nreset_page_fifo_neg	mcntrl_ps_pio	Signal
cmd_wr_out	mcntrl_ps_pio	Signal
page_out_r	mcntrl_ps_pio	Signal
page_out_r_negedge	mcntrl_ps_pio	Signal
page_r_set	mcntrl_ps_pio	Signal
page_w_set_early	mcntrl_ps_pio	Signal
page_w_set_early_negedge	mcntrl_ps_pio	Signal
en_page_w_set	mcntrl_ps_pio	Signal
page_w_set_negedge	mcntrl_ps_pio	Signal
ADDRESS_NUMBER	mcntrl_tiled_rw	Parameter
COLADDR_NUMBER	mcntrl_tiled_rw	Parameter
FRAME_WIDTH_BITS	mcntrl_tiled_rw	Parameter
FRAME_HEIGHT_BITS	mcntrl_tiled_rw	Parameter
MAX_TILE_WIDTH	mcntrl_tiled_rw	Parameter
MAX_TILE_HEIGHT	mcntrl_tiled_rw	Parameter
LAST_FRAME_BITS	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_ADDR	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_MASK	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_MODE	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_STATUS_CNTRL	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_STARTADDR	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_FRAME_SIZE	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_FRAME_LAST	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_FRAME_FULL_WIDTH	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_WINDOW_WH	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_WINDOW_X0Y0	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_WINDOW_STARTXY	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_TILE_WHS	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_STATUS_REG_ADDR	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_PENDING_CNTR_BITS	mcntrl_tiled_rw	Parameter
MCNTRL_TILED_FRAME_PAGE_RESET	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_NRESET	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_EN	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_WRITE	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_EXTRAPG	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_EXTRAPG_BITS	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_KEEP_OPEN	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_BYTE32	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_RST_FRAME	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_SINGLE	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_REPEAT	mcntrl_tiled_rw	Parameter
MCONTR_LINTILE_DIS_NEED	mcntrl_tiled_rw	Parameter
mrst	mcntrl_tiled_rw	Input
mclk	mcntrl_tiled_rw	Input
cmd_ad	mcntrl_tiled_rw	Input
cmd_stb	mcntrl_tiled_rw	Input
status_ad	mcntrl_tiled_rw	Output
status_rq	mcntrl_tiled_rw	Output
status_start	mcntrl_tiled_rw	Input
frame_start	mcntrl_tiled_rw	Input
next_page	mcntrl_tiled_rw	Input
frame_done	mcntrl_tiled_rw	Output
frame_finished	mcntrl_tiled_rw	Output
line_unfinished	mcntrl_tiled_rw	Output
suspend	mcntrl_tiled_rw	Input
frame_number	mcntrl_tiled_rw	Output
xfer_want	mcntrl_tiled_rw	Output
xfer_need	mcntrl_tiled_rw	Output
xfer_grant	mcntrl_tiled_rw	Input
xfer_start_rd	mcntrl_tiled_rw	Output
xfer_start_wr	mcntrl_tiled_rw	Output
xfer_start32_rd	mcntrl_tiled_rw	Output
xfer_start32_wr	mcntrl_tiled_rw	Output
xfer_bank	mcntrl_tiled_rw	Output
xfer_row	mcntrl_tiled_rw	Output
xfer_col	mcntrl_tiled_rw	Output
rowcol_inc	mcntrl_tiled_rw	Output
num_rows_m1	mcntrl_tiled_rw	Output
num_cols_m1	mcntrl_tiled_rw	Output
keep_open	mcntrl_tiled_rw	Output
xfer_partial	mcntrl_tiled_rw	Output
xfer_page_done	mcntrl_tiled_rw	Input
xfer_page_rst_wr	mcntrl_tiled_rw	Output
xfer_page_rst_rd	mcntrl_tiled_rw	Output
NUM_RC_BURST_BITS	mcntrl_tiled_rw	Parameter
MPY_WIDTH	mcntrl_tiled_rw	Parameter
PAR_MOD_LATENCY	mcntrl_tiled_rw	Parameter
curr_x	mcntrl_tiled_rw	Signal
curr_y	mcntrl_tiled_rw	Signal
next_y	mcntrl_tiled_rw	Signal
line_start_addr	mcntrl_tiled_rw	Signal
line_start_page_left	mcntrl_tiled_rw	Signal
frame_y	mcntrl_tiled_rw	Signal
frame_x	mcntrl_tiled_rw	Signal
frame_y8_r	mcntrl_tiled_rw	Signal
frame_full_width_r	mcntrl_tiled_rw	Signal
mul_rslt	mcntrl_tiled_rw	Signal
start_addr_r	mcntrl_tiled_rw	Signal
bank_reg	mcntrl_tiled_rw	Signal
mul_rslt_w	mcntrl_tiled_rw	Signal
row_left	mcntrl_tiled_rw	Signal
last_in_row	mcntrl_tiled_rw	Signal
mem_page_left	mcntrl_tiled_rw	Signal
lim_by_tile_width	mcntrl_tiled_rw	Signal
remainder_tile_width	mcntrl_tiled_rw	Signal
continued_tile	mcntrl_tiled_rw	Signal
leftover_cols	mcntrl_tiled_rw	Signal
pgm_param_w	mcntrl_tiled_rw	Signal
xfer_start_r	mcntrl_tiled_rw	Signal
xfer_start_rd_r	mcntrl_tiled_rw	Signal
xfer_start_wr_r	mcntrl_tiled_rw	Signal
xfer_start32_rd_r	mcntrl_tiled_rw	Signal
xfer_start32_wr_r	mcntrl_tiled_rw	Signal
par_mod_r	mcntrl_tiled_rw	Signal
recalc_r	mcntrl_tiled_rw	Signal
calc_valid	mcntrl_tiled_rw	Signal
chn_en	mcntrl_tiled_rw	Signal
chn_rst	mcntrl_tiled_rw	Signal
chn_rst_d	mcntrl_tiled_rw	Signal
xfer_page_rst_r	mcntrl_tiled_rw	Signal
xfer_page_rst_pos	mcntrl_tiled_rw	Signal
xfer_page_rst_neg	mcntrl_tiled_rw	Signal
page_cntr	mcntrl_tiled_rw	Signal
cmd_wrmem	mcntrl_tiled_rw	Signal
cmd_extra_pages	mcntrl_tiled_rw	Signal
byte32	mcntrl_tiled_rw	Signal
disable_need	mcntrl_tiled_rw	Signal
repeat_frames	mcntrl_tiled_rw	Signal
single_frame_w	mcntrl_tiled_rw	Signal
rst_frame_num_w	mcntrl_tiled_rw	Signal
single_frame_r	mcntrl_tiled_rw	Signal
rst_frame_num_r	mcntrl_tiled_rw	Signal
frame_en	mcntrl_tiled_rw	Signal
busy_r	mcntrl_tiled_rw	Signal
want_r	mcntrl_tiled_rw	Signal
need_r	mcntrl_tiled_rw	Signal
frame_done_r	mcntrl_tiled_rw	Signal
frame_finished_r	mcntrl_tiled_rw	Signal
last_in_row_w	mcntrl_tiled_rw	Signal
last_row_w	mcntrl_tiled_rw	Signal
last_block	mcntrl_tiled_rw	Signal
pending_xfers	mcntrl_tiled_rw	Signal
row_col_r	mcntrl_tiled_rw	Signal
line_unfinished_relw_r	mcntrl_tiled_rw	Signal
line_unfinished_r	mcntrl_tiled_rw	Signal
pre_want	mcntrl_tiled_rw	Signal
status_data	mcntrl_tiled_rw	Signal
cmd_a	mcntrl_tiled_rw	Signal
cmd_data	mcntrl_tiled_rw	Signal
cmd_we	mcntrl_tiled_rw	Signal
set_mode_w	mcntrl_tiled_rw	Signal
set_status_w	mcntrl_tiled_rw	Signal
set_start_addr_w	mcntrl_tiled_rw	Signal
set_frame_size_w	mcntrl_tiled_rw	Signal
set_last_frame_w	mcntrl_tiled_rw	Signal
set_frame_width_w	mcntrl_tiled_rw	Signal
set_window_wh_w	mcntrl_tiled_rw	Signal
set_window_x0y0_w	mcntrl_tiled_rw	Signal
set_window_start_w	mcntrl_tiled_rw	Signal
set_tile_whs_w	mcntrl_tiled_rw	Signal
lsw13_zero	mcntrl_tiled_rw	Signal
msw_zero	mcntrl_tiled_rw	Signal
tile_width_zero	mcntrl_tiled_rw	Signal
tile_height_zero	mcntrl_tiled_rw	Signal
tile_vstep_zero	mcntrl_tiled_rw	Signal
mode_reg	mcntrl_tiled_rw	Signal
start_range_addr	mcntrl_tiled_rw	Signal
frame_size	mcntrl_tiled_rw	Signal
last_frame_number	mcntrl_tiled_rw	Signal
start_addr	mcntrl_tiled_rw	Signal
next_frame_start_addr	mcntrl_tiled_rw	Signal
frame_number_cntr	mcntrl_tiled_rw	Signal
frame_number_current	mcntrl_tiled_rw	Signal
is_last_frame	mcntrl_tiled_rw	Signal
frame_start_r	mcntrl_tiled_rw	Signal
tile_cols	mcntrl_tiled_rw	Signal
tile_rows	mcntrl_tiled_rw	Signal
tile_vstep	mcntrl_tiled_rw	Signal
num_cols_r	mcntrl_tiled_rw	Signal
num_cols_m1_w	mcntrl_tiled_rw	Signal
num_rows_m1_w	mcntrl_tiled_rw	Signal
frame_full_width	mcntrl_tiled_rw	Signal
window_width	mcntrl_tiled_rw	Signal
window_height	mcntrl_tiled_rw	Signal
window_x0	mcntrl_tiled_rw	Signal
window_y0	mcntrl_tiled_rw	Signal
start_x	mcntrl_tiled_rw	Signal
start_y	mcntrl_tiled_rw	Signal
xfer_page_done_d	mcntrl_tiled_rw	Signal
i	mcntrl_tiled_rw	Signal
EXTRA_BITS	mcntrl_tiled_rw	Parameter
xfer_limited_by_mem_page	mcntrl_tiled_rw	Signal
xfer_limited_by_mem_page_r	mcntrl_tiled_rw	Signal
start_not_partial	mcntrl_tiled_rw	Signal
DLY_LD	memctrl16	Parameter
DLY_LD_MASK	memctrl16	Parameter
MCONTR_PHY_0BIT_ADDR	memctrl16	Parameter
MCONTR_PHY_0BIT_ADDR_MASK	memctrl16	Parameter
MCONTR_PHY_0BIT_DLY_SET	memctrl16	Parameter
MCONTR_PHY_0BIT_CMDA_EN	memctrl16	Parameter
MCONTR_PHY_0BIT_SDRST_ACT	memctrl16	Parameter
MCONTR_PHY_0BIT_CKE_EN	memctrl16	Parameter
MCONTR_PHY_0BIT_DCI_RST	memctrl16	Parameter
MCONTR_PHY_0BIT_DLY_RST	memctrl16	Parameter
MCONTR_TOP_0BIT_ADDR	memctrl16	Parameter
MCONTR_TOP_0BIT_ADDR_MASK	memctrl16	Parameter
MCONTR_TOP_0BIT_MCONTR_EN	memctrl16	Parameter
MCONTR_TOP_0BIT_REFRESH_EN	memctrl16	Parameter
MCONTR_PHY_16BIT_ADDR	memctrl16	Parameter
MCONTR_PHY_16BIT_ADDR_MASK	memctrl16	Parameter
MCONTR_PHY_16BIT_PATTERNS	memctrl16	Parameter
MCONTR_PHY_16BIT_PATTERNS_TRI	memctrl16	Parameter
MCONTR_PHY_16BIT_WBUF_DELAY	memctrl16	Parameter
MCONTR_PHY_16BIT_EXTRA	memctrl16	Parameter
MCONTR_PHY_STATUS_CNTRL	memctrl16	Parameter
MCONTR_ARBIT_ADDR	memctrl16	Parameter
MCONTR_ARBIT_ADDR_MASK	memctrl16	Parameter
MCONTR_TOP_16BIT_ADDR	memctrl16	Parameter
MCONTR_TOP_16BIT_ADDR_MASK	memctrl16	Parameter
MCONTR_TOP_16BIT_CHN_EN	memctrl16	Parameter
MCONTR_TOP_16BIT_REFRESH_PERIOD	memctrl16	Parameter
MCONTR_TOP_16BIT_REFRESH_ADDRESS	memctrl16	Parameter
MCONTR_TOP_16BIT_STATUS_CNTRL	memctrl16	Parameter
MCONTR_PHY_STATUS_REG_ADDR	memctrl16	Parameter
MCONTR_TOP_STATUS_REG_ADDR	memctrl16	Parameter
CHNBUF_READ_LATENCY	memctrl16	Parameter
DFLT_DQS_PATTERN	memctrl16	Parameter
DFLT_DQM_PATTERN	memctrl16	Parameter
DFLT_DQ_TRI_ON_PATTERN	memctrl16	Parameter
DFLT_DQ_TRI_OFF_PATTERN	memctrl16	Parameter
DFLT_DQS_TRI_ON_PATTERN	memctrl16	Parameter
DFLT_DQS_TRI_OFF_PATTERN	memctrl16	Parameter
DFLT_WBUF_DELAY	memctrl16	Parameter
DFLT_INV_CLK_DIV	memctrl16	Parameter
DFLT_CHN_EN	memctrl16	Parameter
DFLT_REFRESH_ADDR	memctrl16	Parameter
DFLT_REFRESH_PERIOD	memctrl16	Parameter
ADDRESS_NUMBER	memctrl16	Parameter
PHASE_WIDTH	memctrl16	Parameter
SLEW_DQ	memctrl16	Parameter
SLEW_DQS	memctrl16	Parameter
SLEW_CMDA	memctrl16	Parameter
SLEW_CLK	memctrl16	Parameter
IBUF_LOW_PWR	memctrl16	Parameter
REFCLK_FREQUENCY	memctrl16	Parameter
HIGH_PERFORMANCE_MODE	memctrl16	Parameter
CLKIN_PERIOD	memctrl16	Parameter
CLKFBOUT_MULT	memctrl16	Parameter
DIVCLK_DIVIDE	memctrl16	Parameter
CLKFBOUT_USE_FINE_PS	memctrl16	Parameter
CLKFBOUT_PHASE	memctrl16	Parameter
SDCLK_PHASE	memctrl16	Parameter
CLK_PHASE	memctrl16	Parameter
CLK_DIV_PHASE	memctrl16	Parameter
MCLK_PHASE	memctrl16	Parameter
REF_JITTER1	memctrl16	Parameter
SS_EN	memctrl16	Parameter
SS_MODE	memctrl16	Parameter
SS_MOD_PERIOD	memctrl16	Parameter
CMD_PAUSE_BITS	memctrl16	Parameter
CMD_DONE_BIT	memctrl16	Parameter
rst_in	memctrl16	Input
clk_in	memctrl16	Input
mclk	memctrl16	Output
mrst	memctrl16	Input
locked	memctrl16	Output
ref_clk	memctrl16	Input
idelay_ctrl_reset	memctrl16	Output
cmd_ad	memctrl16	Input
cmd_stb	memctrl16	Input
status_ad	memctrl16	Output
status_rq	memctrl16	Output
status_start	memctrl16	Input
cmd0_clk	memctrl16	Input
cmd0_we	memctrl16	Input
cmd0_addr	memctrl16	Input
cmd0_data	memctrl16	Input
seq_data	memctrl16	Input
seq_wr	memctrl16	Input
seq_set	memctrl16	Input
want_rq0	memctrl16	Input
need_rq0	memctrl16	Input
channel_pgm_en0	memctrl16	Output
reject0	memctrl16	Input
seq_done0	memctrl16	Output
page_nxt_chn0	memctrl16	Output
buf_run0	memctrl16	Output
buf_wr_chn0	memctrl16	Output
buf_wpage_nxt_chn0	memctrl16	Output
buf_wdata_chn0	memctrl16	Output
buf_wrun0	memctrl16	Output
buf_rd_chn0	memctrl16	Output
buf_rpage_nxt_chn0	memctrl16	Output
buf_rdata_chn0	memctrl16	Input
want_rq1	memctrl16	Input
need_rq1	memctrl16	Input
channel_pgm_en1	memctrl16	Output
reject1	memctrl16	Input
seq_done1	memctrl16	Output
page_nxt_chn1	memctrl16	Output
buf_run1	memctrl16	Output
buf_wr_chn1	memctrl16	Output
buf_wpage_nxt_chn1	memctrl16	Output
buf_wdata_chn1	memctrl16	Output
buf_wrun1	memctrl16	Output
buf_rd_chn1	memctrl16	Output
buf_rpage_nxt_chn1	memctrl16	Output
buf_rdata_chn1	memctrl16	Input
want_rq2	memctrl16	Input
need_rq2	memctrl16	Input
channel_pgm_en2	memctrl16	Output
reject2	memctrl16	Input
seq_done2	memctrl16	Output
page_nxt_chn2	memctrl16	Output
buf_run2	memctrl16	Output
buf_wr_chn2	memctrl16	Output
buf_wpage_nxt_chn2	memctrl16	Output
buf_wdata_chn2	memctrl16	Output
buf_wrun2	memctrl16	Output
buf_rd_chn2	memctrl16	Output
buf_rpage_nxt_chn2	memctrl16	Output
buf_rdata_chn2	memctrl16	Input
want_rq3	memctrl16	Input
need_rq3	memctrl16	Input
channel_pgm_en3	memctrl16	Output
reject3	memctrl16	Input
seq_done3	memctrl16	Output
page_nxt_chn3	memctrl16	Output
buf_run3	memctrl16	Output
buf_wr_chn3	memctrl16	Output
buf_wpage_nxt_chn3	memctrl16	Output
buf_wdata_chn3	memctrl16	Output
buf_wrun3	memctrl16	Output
buf_rd_chn3	memctrl16	Output
buf_rpage_nxt_chn3	memctrl16	Output
buf_rdata_chn3	memctrl16	Input
want_rq4	memctrl16	Input
need_rq4	memctrl16	Input
channel_pgm_en4	memctrl16	Output
reject4	memctrl16	Input
seq_done4	memctrl16	Output
page_nxt_chn4	memctrl16	Output
buf_run4	memctrl16	Output
buf_wr_chn4	memctrl16	Output
buf_wpage_nxt_chn4	memctrl16	Output
buf_wdata_chn4	memctrl16	Output
buf_wrun4	memctrl16	Output
buf_rd_chn4	memctrl16	Output
buf_rpage_nxt_chn4	memctrl16	Output
buf_rdata_chn4	memctrl16	Input
want_rq8	memctrl16	Input
need_rq8	memctrl16	Input
channel_pgm_en8	memctrl16	Output
reject8	memctrl16	Input
seq_done8	memctrl16	Output
page_nxt_chn8	memctrl16	Output
buf_run8	memctrl16	Output
buf_rd_chn8	memctrl16	Output
buf_rpage_nxt_chn8	memctrl16	Output
buf_rdata_chn8	memctrl16	Input
want_rq9	memctrl16	Input
need_rq9	memctrl16	Input
channel_pgm_en9	memctrl16	Output
reject9	memctrl16	Input
seq_done9	memctrl16	Output
page_nxt_chn9	memctrl16	Output
buf_run9	memctrl16	Output
buf_rd_chn9	memctrl16	Output
buf_rpage_nxt_chn9	memctrl16	Output
buf_rdata_chn9	memctrl16	Input
want_rq10	memctrl16	Input
need_rq10	memctrl16	Input
channel_pgm_en10	memctrl16	Output
reject10	memctrl16	Input
seq_done10	memctrl16	Output
page_nxt_chn10	memctrl16	Output
buf_run10	memctrl16	Output
buf_rd_chn10	memctrl16	Output
buf_rpage_nxt_chn10	memctrl16	Output
buf_rdata_chn10	memctrl16	Input
want_rq11	memctrl16	Input
need_rq11	memctrl16	Input
channel_pgm_en11	memctrl16	Output
reject11	memctrl16	Input
seq_done11	memctrl16	Output
page_nxt_chn11	memctrl16	Output
buf_run11	memctrl16	Output
buf_rd_chn11	memctrl16	Output
buf_rpage_nxt_chn11	memctrl16	Output
buf_rdata_chn11	memctrl16	Input
want_rq12	memctrl16	Input
need_rq12	memctrl16	Input
channel_pgm_en12	memctrl16	Output
reject12	memctrl16	Input
seq_done12	memctrl16	Output
page_nxt_chn12	memctrl16	Output
buf_run12	memctrl16	Output
buf_wr_chn12	memctrl16	Output
buf_wpage_nxt_chn12	memctrl16	Output
buf_wdata_chn12	memctrl16	Output
buf_wrun12	memctrl16	Output
want_rq13	memctrl16	Input
need_rq13	memctrl16	Input
channel_pgm_en13	memctrl16	Output
reject13	memctrl16	Input
seq_done13	memctrl16	Output
page_nxt_chn13	memctrl16	Output
buf_run13	memctrl16	Output
buf_wr_chn13	memctrl16	Output
buf_wpage_nxt_chn13	memctrl16	Output
buf_wdata_chn13	memctrl16	Output
buf_wrun13	memctrl16	Output
want_rq14	memctrl16	Input
need_rq14	memctrl16	Input
channel_pgm_en14	memctrl16	Output
reject14	memctrl16	Input
seq_done14	memctrl16	Output
page_nxt_chn14	memctrl16	Output
buf_run14	memctrl16	Output
buf_wr_chn14	memctrl16	Output
buf_wpage_nxt_chn14	memctrl16	Output
buf_wdata_chn14	memctrl16	Output
buf_wrun14	memctrl16	Output
want_rq15	memctrl16	Input
need_rq15	memctrl16	Input
channel_pgm_en15	memctrl16	Output
reject15	memctrl16	Input
seq_done15	memctrl16	Output
page_nxt_chn15	memctrl16	Output
buf_run15	memctrl16	Output
buf_wr_chn15	memctrl16	Output
buf_wpage_nxt_chn15	memctrl16	Output
buf_wdata_chn15	memctrl16	Output
buf_wrun15	memctrl16	Output
SDRST	memctrl16	Output
SDCLK	memctrl16	Output
SDNCLK	memctrl16	Output
SDA	memctrl16	Output
SDBA	memctrl16	Output
SDWE	memctrl16	Output
SDRAS	memctrl16	Output
SDCAS	memctrl16	Output
SDCKE	memctrl16	Output
SDODT	memctrl16	Output
SDD	memctrl16	Inout
SDDML	memctrl16	Output
DQSL	memctrl16	Inout
NDQSL	memctrl16	Inout
SDDMU	memctrl16	Output
DQSU	memctrl16	Inout
NDQSU	memctrl16	Inout
tmp_debug	memctrl16	Output
reject	memctrl16	Signal
ext_buf_rd	memctrl16	Signal
ext_buf_rpage_nxt	memctrl16	Signal
ext_buf_page_nxt	memctrl16	Signal
ext_buf_rchn	memctrl16	Signal
ext_buf_rrefresh	memctrl16	Signal
ext_buf_rrun	memctrl16	Signal
ext_buf_rdata	memctrl16	Signal
ext_buf_wr	memctrl16	Signal
ext_buf_wpage_nxt	memctrl16	Signal
ext_buf_wchn	memctrl16	Signal
ext_buf_wrefresh	memctrl16	Signal
ext_buf_wrun	memctrl16	Signal
ext_buf_wdata	memctrl16	Signal
want_rq	memctrl16	Signal
need_rq	memctrl16	Signal
status_ad_phy	memctrl16	Signal
status_rq_phy	memctrl16	Signal
status_start_phy	memctrl16	Signal
status_ad_mcontr	memctrl16	Signal
status_rq_mcontr	memctrl16	Signal
status_start_mcontr	memctrl16	Signal
set_status_w	memctrl16	Signal
en_schedul	memctrl16	Signal
need	memctrl16	Signal
grant	memctrl16	Signal
grant_chn	memctrl16	Signal
priority_addr	memctrl16	Signal
priority_data	memctrl16	Signal
priority_en	memctrl16	Signal
cmd_wr_chn	memctrl16	Signal
cmd_addr_cur	memctrl16	Signal
cmd_addr_start	memctrl16	Signal
grant_r	memctrl16	Signal
cmd_seq_set	memctrl16	Signal
cmd_seq_fill	memctrl16	Signal
cmd_seq_full	memctrl16	Signal
cmd_seq_need	memctrl16	Signal
cmd_seq_run	memctrl16	Signal
cmd_seq_chn	memctrl16	Signal
cmd_seq_refresh	memctrl16	Signal
cmd_seq_addr	memctrl16	Signal
sel_refresh_w	memctrl16	Signal
pre_run_seq_w	memctrl16	Signal
pre_run_chn_w	memctrl16	Signal
mcontr_reset	memctrl16	Signal
mcontr_enabled	memctrl16	Signal
sequencer_run_busy	memctrl16	Signal
sequencer_run_done	memctrl16	Signal
refresh_want	memctrl16	Signal
refresh_need	memctrl16	Signal
refresh_grant	memctrl16	Signal
refresh_en	memctrl16	Signal
refresh_period	memctrl16	Signal
refresh_addr	memctrl16	Signal
mcontr_en	memctrl16	Signal
mcontr_chn_en	memctrl16	Signal
chn_want_some	memctrl16	Signal
chn_need_some	memctrl16	Signal
chn_want_r	memctrl16	Signal
status_data	memctrl16	Signal
mcontr_0bit_addr	memctrl16	Signal
mcontr_0bit_we	memctrl16	Signal
mcontr_16bit_addr	memctrl16	Signal
mcontr_16bit_data	memctrl16	Signal
mcontr_16bit_we	memctrl16	Signal
set_chn_en_w	memctrl16	Signal
set_refresh_period_w	memctrl16	Signal
set_refresh_address_w	memctrl16	Signal
set_refresh_period	memctrl16	Signal
reject_r	memctrl16	Signal
ext_buf_rdata0	memctrl16	Signal
ext_buf_rdata1	memctrl16	Signal
ext_buf_rdata2	memctrl16	Signal
ext_buf_rdata3	memctrl16	Signal
ext_buf_rdata4	memctrl16	Signal
ext_buf_rdata8	memctrl16	Signal
ext_buf_rdata9	memctrl16	Signal
ext_buf_rdata10	memctrl16	Signal
ext_buf_rdata11	memctrl16	Signal
ext_buf_rchn_late	memctrl16	Signal
ext_buf_rd_late	memctrl16	Signal
EXT_READ_LATENCY	memctrl16	Parameter
want_rq5	memctrl16	Signal
need_rq5	memctrl16	Signal
want_rq6	memctrl16	Signal
need_rq6	memctrl16	Signal
want_rq7	memctrl16	Signal
need_rq7	memctrl16	Signal
mcntrl_tiled_rw.ADDR	cmd_deser	Parameter
mcntrl_ps_pio.ADDR	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR_MASK	cmd_deser	Parameter
mcntrl_ps_pio.ADDR_MASK	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR_MASK	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR_MASK	cmd_deser	Parameter
mcntrl_tiled_rw.NUM_CYCLES	cmd_deser	Parameter
mcntrl_ps_pio.NUM_CYCLES	cmd_deser	Parameter
memctrl16.cmd_deser.NUM_CYCLES	cmd_deser	Parameter
memctrl16.mcontr_sequencer.NUM_CYCLES	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR_WIDTH	cmd_deser	Parameter
mcntrl_ps_pio.ADDR_WIDTH	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR_WIDTH	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR_WIDTH	cmd_deser	Parameter
mcntrl_tiled_rw.DATA_WIDTH	cmd_deser	Parameter
mcntrl_ps_pio.DATA_WIDTH	cmd_deser	Parameter
memctrl16.cmd_deser.DATA_WIDTH	cmd_deser	Parameter
memctrl16.mcontr_sequencer.DATA_WIDTH	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR1	cmd_deser	Parameter
mcntrl_ps_pio.ADDR1	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR1	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR1	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR_MASK1	cmd_deser	Parameter
mcntrl_ps_pio.ADDR_MASK1	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR_MASK1	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR_MASK1	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR2	cmd_deser	Parameter
mcntrl_ps_pio.ADDR2	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR2	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR2	cmd_deser	Parameter
mcntrl_tiled_rw.ADDR_MASK2	cmd_deser	Parameter
mcntrl_ps_pio.ADDR_MASK2	cmd_deser	Parameter
memctrl16.cmd_deser.ADDR_MASK2	cmd_deser	Parameter
memctrl16.mcontr_sequencer.ADDR_MASK2	cmd_deser	Parameter
mcntrl_tiled_rw.WE_EARLY	cmd_deser	Parameter
mcntrl_ps_pio.WE_EARLY	cmd_deser	Parameter
memctrl16.cmd_deser.WE_EARLY	cmd_deser	Parameter
memctrl16.mcontr_sequencer.WE_EARLY	cmd_deser	Parameter
mcntrl_tiled_rw.rst	cmd_deser	Input
mcntrl_ps_pio.rst	cmd_deser	Input
memctrl16.cmd_deser.rst	cmd_deser	Input
memctrl16.mcontr_sequencer.rst	cmd_deser	Input
mcntrl_tiled_rw.clk	cmd_deser	Input
mcntrl_ps_pio.clk	cmd_deser	Input
memctrl16.cmd_deser.clk	cmd_deser	Input
memctrl16.mcontr_sequencer.clk	cmd_deser	Input
mcntrl_tiled_rw.srst	cmd_deser	Input
mcntrl_ps_pio.srst	cmd_deser	Input
memctrl16.cmd_deser.srst	cmd_deser	Input
memctrl16.mcontr_sequencer.srst	cmd_deser	Input
mcntrl_tiled_rw.ad	cmd_deser	Input
mcntrl_ps_pio.ad	cmd_deser	Input
memctrl16.cmd_deser.ad	cmd_deser	Input
memctrl16.mcontr_sequencer.ad	cmd_deser	Input
mcntrl_tiled_rw.stb	cmd_deser	Input
mcntrl_ps_pio.stb	cmd_deser	Input
memctrl16.cmd_deser.stb	cmd_deser	Input
memctrl16.mcontr_sequencer.stb	cmd_deser	Input
mcntrl_tiled_rw.addr	cmd_deser	Output
mcntrl_ps_pio.addr	cmd_deser	Output
memctrl16.cmd_deser.addr	cmd_deser	Output
memctrl16.mcontr_sequencer.addr	cmd_deser	Output
mcntrl_tiled_rw.data	cmd_deser	Output
mcntrl_ps_pio.data	cmd_deser	Output
memctrl16.cmd_deser.data	cmd_deser	Output
memctrl16.mcontr_sequencer.data	cmd_deser	Output
mcntrl_tiled_rw.we	cmd_deser	Output
mcntrl_ps_pio.we	cmd_deser	Output
memctrl16.cmd_deser.we	cmd_deser	Output
memctrl16.mcontr_sequencer.we	cmd_deser	Output
mcntrl_tiled_rw.WE_WIDTH	cmd_deser	Parameter
mcntrl_ps_pio.WE_WIDTH	cmd_deser	Parameter
memctrl16.cmd_deser.WE_WIDTH	cmd_deser	Parameter
memctrl16.mcontr_sequencer.WE_WIDTH	cmd_deser	Parameter
ALWAYS_234 clk	cmd_encod_4mux	Always Construct
ALWAYS_235 clk	cmd_encod_4mux	Always Construct
ALWAYS_236 clk	cmd_encod_linear_mux	Always Construct
ALWAYS_242 clk	cmd_encod_linear_rw	Always Construct
ALWAYS_243 clk	cmd_encod_linear_rw	Always Construct
ALWAYS_254 clk	cmd_encod_tiled_32_rw	Always Construct
ALWAYS_255 clk	cmd_encod_tiled_32_rw	Always Construct
ALWAYS_260 clk	cmd_encod_tiled_mux	Always Construct
ALWAYS_265 clk	cmd_encod_tiled_rw	Always Construct
ALWAYS_266 clk	cmd_encod_tiled_rw	Always Construct
ALWAYS_272 mclk	mcntrl393	Always Construct
ALWAYS_273 axi_clk	mcntrl393	Always Construct
ALWAYS_274 axi_clk	mcntrl393	Always Construct
mcntrl_buf_rd.ALWAYS_280 wclk	mcntrl_buf_rd	Always Construct
mcntrl_ps_pio.ALWAYS_280 wclk	mcntrl_buf_rd	Always Construct
mcntrl_buf_wr.ALWAYS_281 rclk	mcntrl_buf_wr	Always Construct
mcntrl_ps_pio.ALWAYS_281 rclk	mcntrl_buf_wr	Always Construct
ALWAYS_282 mclk	mcntrl_linear_rw	Always Construct
ALWAYS_283 mclk	mcntrl_linear_rw	Always Construct
ALWAYS_284 mclk	mcntrl_linear_rw	Always Construct
ALWAYS_285 mclk	mcntrl_linear_rw	Always Construct
ALWAYS_286 mclk	mcntrl_linear_rw	Always Construct
ALWAYS_287 mclk	mcntrl_ps_pio	Always Construct
ALWAYS_288 mclk	mcntrl_ps_pio	Always Construct
ALWAYS_289 mclk	mcntrl_ps_pio	Always Construct
ALWAYS_290 mclk	mcntrl_ps_pio	Always Construct
ALWAYS_291 mclk	mcntrl_tiled_rw	Always Construct
ALWAYS_292 mclk	mcntrl_tiled_rw	Always Construct
ALWAYS_293 mclk	mcntrl_tiled_rw	Always Construct
ALWAYS_294 mclk	mcntrl_tiled_rw	Always Construct
ALWAYS_295 mclk	memctrl16	Always Construct
ALWAYS_296 mclk	memctrl16	Always Construct
ALWAYS_297 mclk	memctrl16	Always Construct
ALWAYS_298 mclk	memctrl16	Always Construct
ALWAYS_299 mclk	memctrl16	Always Construct
ALWAYS_300 mclk	memctrl16	Always Construct
ALWAYS_301 mclk	memctrl16	Always Construct
ALWAYS_302 mclk	memctrl16	Always Construct
ALWAYS_303 mclk	memctrl16	Always Construct
ALWAYS_304 mclk	memctrl16	Always Construct
ALWAYS_305 mclk	memctrl16	Always Construct
ALWAYS_306 mclk	memctrl16	Always Construct
ALWAYS_307 mclk	memctrl16	Always Construct
ALWAYS_308 mclk	memctrl16	Always Construct
ALWAYS_309 mclk	memctrl16	Always Construct
ALWAYS_310 mclk	memctrl16	Always Construct
ALWAYS_311 mclk	memctrl16	Always Construct
ALWAYS_312 mclk	memctrl16	Always Construct
ALWAYS_313 mclk	memctrl16	Always Construct
ALWAYS_502 clk	fifo_2regs	Always Construct
ALWAYS_503 clk	fifo_2regs	Always Construct
ALWAYS_508 clk or rst	fifo_same_clock	Always Construct
ALWAYS_509 clk	fifo_same_clock	Always Construct
ALWAYS_546 rst or clk	status_router2	Always Construct
mcntrl_linear_rw.cmd_deser	mcntrl_linear_rw	Module Instance
mcntrl_tiled_rw.cmd_deser	mcntrl_tiled_rw	Module Instance
mcntrl_ps_pio.cmd_deser	mcntrl_ps_pio	Module Instance
memctrl16.cmd_deser	memctrl16	Module Instance
mcntrl_tiled_rw.cmd_deser_dual	cmd_deser	Module Instance
mcntrl_ps_pio.cmd_deser_dual	cmd_deser	Module Instance
memctrl16.cmd_deser.cmd_deser_dual	cmd_deser	Module Instance
memctrl16.mcontr_sequencer.cmd_deser_dual	cmd_deser	Module Instance
mcntrl_tiled_rw.cmd_deser_multi	cmd_deser	Module Instance
mcntrl_ps_pio.cmd_deser_multi	cmd_deser	Module Instance
memctrl16.cmd_deser.cmd_deser_multi	cmd_deser	Module Instance
memctrl16.mcontr_sequencer.cmd_deser_multi	cmd_deser	Module Instance
mcntrl_tiled_rw.cmd_deser_single	cmd_deser	Module Instance
mcntrl_ps_pio.cmd_deser_single	cmd_deser	Module Instance
memctrl16.cmd_deser.cmd_deser_single	cmd_deser	Module Instance
memctrl16.mcontr_sequencer.cmd_deser_single	cmd_deser	Module Instance
cmd_encod_4mux	mcntrl393
cmd_encod_linear_mux	mcntrl393
cmd_encod_linear_rd	cmd_encod_linear_rw	Module Instance
cmd_encod_linear_rw	mcntrl393
cmd_encod_linear_wr	cmd_encod_linear_rw	Module Instance
cmd_encod_tiled_32_rd	cmd_encod_tiled_32_rw	Module Instance
cmd_encod_tiled_32_rw	mcntrl393
cmd_encod_tiled_32_wr	cmd_encod_tiled_32_rw	Module Instance
cmd_encod_tiled_mux	mcntrl393
cmd_encod_tiled_rd	cmd_encod_tiled_rw	Module Instance
cmd_encod_tiled_rw	mcntrl393
cmd_encod_tiled_wr	cmd_encod_tiled_rw	Module Instance
ddr_refresh	memctrl16	Module Instance
dly_16	memctrl16	Module Instance
fifo_1cycle	status_router2	Module Instance
cmd_encod_tiled_32_rw.fifo_2regs	cmd_encod_tiled_32_rd	Module Instance
cmd_encod_tiled_32_rw.cmd_encod_tiled_32_wr.fifo_2regs	cmd_encod_tiled_32_wr	Module Instance
mcntrl_ps_pio.fifo_same_clock	mcntrl_ps_pio	Module Instance
memctrl16.fifo_same_clock	status_router2	Module Instance
GENERATE [1067]	mcntrl393
mcntrl_buf_wr.GENERATE [107]	ram_var_w_var_r	GENERATE
mcntrl_ps_pio.GENERATE [107]	ram_var_w_var_r	GENERATE
memctrl16.GENERATE [122]	status_router2	GENERATE
memctrl16.scheduler16.GENERATE [122]	scheduler16	GENERATE
mcntrl_tiled_rw.GENERATE [63]	cmd_deser	GENERATE
mcntrl_ps_pio.GENERATE [63]	cmd_deser	GENERATE
memctrl16.cmd_deser.GENERATE [63]	cmd_deser	GENERATE
memctrl16.mcontr_sequencer.GENERATE [63]	cmd_deser	GENERATE
mcntrl_tiled_rw.GENERATE [68]	status_generate	GENERATE
mcntrl_ps_pio.GENERATE [68]	status_generate	GENERATE
memctrl16.status_generate.GENERATE [68]	status_generate	GENERATE
memctrl16.mcontr_sequencer.GENERATE [68]	status_generate	GENERATE
mcntrl_buf_rd	mcntrl393
mcntrl_buf_rd	mcntrl393
mcntrl_buf_rd	mcntrl393
mcntrl_buf_wr	mcntrl393
mcntrl_buf_wr	mcntrl393
mcntrl_buf_wr	mcntrl393
mcntrl_linear_rw	mcntrl393
mcntrl_linear_rw	mcntrl393
mcntrl_linear_rw	mcntrl393
mcntrl_ps_pio	mcntrl393
mcntrl_tiled_rw	mcntrl393
mcntrl_tiled_rw	mcntrl393
mcntrl_tiled_rw	mcntrl393
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_common_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_from_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcont_to_chnbuf_reg	memctrl16	Module Instance
mcontr_sequencer	memctrl16	Module Instance
memctrl16	mcntrl393
mcntrl_buf_wr.ram36_declare_init.vh	ram_var_w_var_r	Include
mcntrl_ps_pio.ram36_declare_init.vh	ram_var_w_var_r	Include
mcntrl_buf_wr.ram36_pass_init.vh	ram_var_w_var_r	Include
mcntrl_ps_pio.ram36_pass_init.vh	ram_var_w_var_r	Include
mcntrl_buf_wr.ram_64w_64r	ram_var_w_var_r	Module Instance
mcntrl_ps_pio.ram_64w_64r	ram_var_w_var_r	Module Instance
mcntrl_buf_wr.ram_64w_lt64r	ram_var_w_var_r	Module Instance
mcntrl_ps_pio.ram_64w_lt64r	ram_var_w_var_r	Module Instance
mcntrl_buf_wr.ram_dummy	ram_var_w_var_r	Module Instance
mcntrl_ps_pio.ram_dummy	ram_var_w_var_r	Module Instance
mcntrl_buf_wr.ram_lt64w_64r	ram_var_w_var_r	Module Instance
mcntrl_ps_pio.ram_lt64w_64r	ram_var_w_var_r	Module Instance
mcntrl_buf_wr.ram_lt64w_lt64r	ram_var_w_var_r	Module Instance
mcntrl_ps_pio.ram_lt64w_lt64r	ram_var_w_var_r	Module Instance
mcntrl_buf_rd.ram_var_w_var_r	mcntrl_buf_rd	Module Instance
mcntrl_buf_wr.ram_var_w_var_r	mcntrl_buf_wr	Module Instance
mcntrl_ps_pio.mcntrl_buf_rd.ram_var_w_var_r	mcntrl_buf_rd	Module Instance
mcntrl_ps_pio.mcntrl_buf_wr.ram_var_w_var_r	mcntrl_buf_wr	Module Instance
scheduler16	memctrl16	Module Instance
mcntrl_linear_rw.status_generate	mcntrl_linear_rw	Module Instance
mcntrl_tiled_rw.status_generate	mcntrl_tiled_rw	Module Instance
mcntrl_ps_pio.status_generate	mcntrl_ps_pio	Module Instance
memctrl16.status_generate	memctrl16	Module Instance
mcntrl_tiled_rw.status_generate_extra	status_generate	Module Instance
mcntrl_ps_pio.status_generate_extra	status_generate	Module Instance
memctrl16.status_generate.status_generate_extra	status_generate	Module Instance
memctrl16.mcontr_sequencer.status_generate_extra	status_generate	Module Instance
mcntrl_tiled_rw.status_generate_only	status_generate	Module Instance
mcntrl_ps_pio.status_generate_only	status_generate	Module Instance
memctrl16.status_generate.status_generate_only	status_generate	Module Instance
memctrl16.mcontr_sequencer.status_generate_only	status_generate	Module Instance
status_router16	mcntrl393
status_router16.status_router2	status_router16	Module Instance
memctrl16.status_router2	memctrl16	Module Instance
status_router8	status_router16	Module Instance
status_router8	status_router16	Module Instance
cmd_encod_tiled_rw.x393_mcontr_encode_cmd.vh	cmd_encod_tiled_rd	Include
cmd_encod_tiled_rw.cmd_encod_tiled_wr.x393_mcontr_encode_cmd.vh	cmd_encod_tiled_wr	Include
cmd_encod_tiled_32_rw.cmd_encod_tiled_32_rd.x393_mcontr_encode_cmd.vh	cmd_encod_tiled_32_rd	Include
cmd_encod_tiled_32_rw.cmd_encod_tiled_32_wr.x393_mcontr_encode_cmd.vh	cmd_encod_tiled_32_wr	Include