Static Public Member Functions

Always Constructs
ALWAYS_282	( mclk )
ALWAYS_283	( mclk )
ALWAYS_284	( mclk )
ALWAYS_285	( mclk )
ALWAYS_286	( mclk )

Public Attributes

Inputs
mrst
mclk
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start
frame_start
next_page
suspend
xfer_grant
xfer_done

Outputs
status_ad	[ 7 : 0 ]
status_rq
frame_run
frame_done
frame_finished
line_unfinished	[FRAME_HEIGHT_BITS - 1 : 0 ]
frame_number	[LAST_FRAME_BITS - 1 : 0 ]
xfer_want
xfer_need
xfer_reject
xfer_start_rd
xfer_start_wr
xfer_bank	[ 2 : 0 ]
xfer_row	[ADDRESS_NUMBER - 1 : 0 ]
xfer_col	[COLADDR_NUMBER - 4 : 0 ]
xfer_num128	[NUM_XFER_BITS - 1 : 0 ]
xfer_partial
xfer_page_rst_wr
xfer_page_rst_rd
xfer_skipped	reg
cmd_wrmem

Parameters
ADDRESS_NUMBER	15
COLADDR_NUMBER	10
NUM_XFER_BITS	6
FRAME_WIDTH_BITS	13
FRAME_HEIGHT_BITS	16
LAST_FRAME_BITS	16
MCNTRL_SCANLINE_ADDR	'h120
MCNTRL_SCANLINE_MASK	'h7f0
MCNTRL_SCANLINE_MODE	'h0
MCNTRL_SCANLINE_STATUS_CNTRL	'h1
MCNTRL_SCANLINE_STARTADDR	'h2
MCNTRL_SCANLINE_FRAME_SIZE	'h3
MCNTRL_SCANLINE_FRAME_LAST	'h4
MCNTRL_SCANLINE_FRAME_FULL_WIDTH	'h5
MCNTRL_SCANLINE_WINDOW_WH	'h6
MCNTRL_SCANLINE_WINDOW_X0Y0	'h7
MCNTRL_SCANLINE_WINDOW_STARTXY	'h8
MCNTRL_SCANLINE_STATUS_REG_ADDR	'h4
MCNTRL_SCANLINE_PENDING_CNTR_BITS	2
MCNTRL_SCANLINE_FRAME_PAGE_RESET	1 'b0
MCONTR_LINTILE_NRESET	0
MCONTR_LINTILE_EN	1
MCONTR_LINTILE_WRITE	2
MCONTR_LINTILE_EXTRAPG	3
MCONTR_LINTILE_EXTRAPG_BITS	2
MCONTR_LINTILE_RST_FRAME	8
MCONTR_LINTILE_SINGLE	9
MCONTR_LINTILE_REPEAT	10
MCONTR_LINTILE_DIS_NEED	11
MCONTR_LINTILE_SKIP_LATE	12
NUM_RC_BURST_BITS	ADDRESS_NUMBER +COLADDR_NUMBER - 3
MPY_WIDTH	NUM_RC_BURST_BITS
PAR_MOD_LATENCY	9
EXTRA_BITS	[COLADDR_NUMBER - 3 -NUM_XFER_BITS - 1 : 0 ] 0

Signals
reg[FRAME_WIDTH_BITS - 1 : 0 ]	curr_x
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	curr_y
reg[FRAME_HEIGHT_BITS : 0 ]	next_y
reg[NUM_RC_BURST_BITS - 1 : 0 ]	line_start_addr
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	frame_y
reg[FRAME_WIDTH_BITS - 1 : 0 ]	frame_x
reg[FRAME_HEIGHT_BITS - 4 : 0 ]	frame_y8_r
reg[FRAME_WIDTH_BITS : 0 ]	frame_full_width_r
reg[MPY_WIDTH - 1 : 0 ]	mul_rslt
reg[NUM_RC_BURST_BITS - 1 : 0 ]	start_addr_r
*reg[ 3 3 - 1 : 0 ]**	bank_reg
wire[FRAME_WIDTH_BITS +FRAME_HEIGHT_BITS - 3 : 0 ]	mul_rslt_w
reg[FRAME_WIDTH_BITS : 0 ]	row_left
reg	last_in_row
reg[COLADDR_NUMBER - 3 : 0 ]	mem_page_left
reg[COLADDR_NUMBER - 4 : 0 ]	line_start_page_left
reg[NUM_XFER_BITS : 0 ]	lim_by_xfer
wire[COLADDR_NUMBER - 3 : 0 ]	remainder_in_xfer
reg	continued_xfer
reg[NUM_XFER_BITS - 1 : 0 ]	leftover
reg[NUM_XFER_BITS : 0 ]	xfer_num128_r
wire	pgm_param_w
reg[ 2 : 0 ]	xfer_start_r
reg	xfer_start_rd_r
reg	xfer_start_wr_r
reg[PAR_MOD_LATENCY - 1 : 0 ]	par_mod_r
reg[PAR_MOD_LATENCY - 1 : 0 ]	recalc_r
wire	calc_valid
wire	chn_en
wire	chn_rst
reg	chn_rst_d
reg	xfer_page_rst_r
reg	xfer_page_rst_pos
reg	xfer_page_rst_neg
reg[ 2 : 0 ]	page_cntr
wire[ 1 : 0 ]	cmd_extra_pages
wire	skip_too_late
wire	disable_need
wire	repeat_frames
wire	single_frame_w
wire	rst_frame_num_w
reg	single_frame_r
reg[ 1 : 0 ]	rst_frame_num_r
reg	frame_en
reg	busy_r
reg	want_r
reg	need_r
reg	frame_done_r
reg	frame_finished_r
wire	last_in_row_w
wire	last_row_w
reg	last_block
reg[MCNTRL_SCANLINE_PENDING_CNTR_BITS - 1 : 0 ]	pending_xfers
reg[NUM_RC_BURST_BITS - 1 : 0 ]	row_col_r
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	line_unfinished_relw_r
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	line_unfinished_r
wire	pre_want
reg	pre_want_r1
wire[ 1 : 0 ]	status_data
wire[ 3 : 0 ]	cmd_a
wire[ 31 : 0 ]	cmd_data
wire	cmd_we
wire	set_mode_w
wire	set_status_w
wire	set_start_addr_w
wire	set_frame_size_w
wire	set_last_frame_w
wire	set_frame_width_w
wire	set_window_wh_w
wire	set_window_x0y0_w
wire	set_window_start_w
wire	lsw13_zero
wire	msw_zero
reg[ 12 : 0 ]	mode_reg
reg[NUM_RC_BURST_BITS - 1 : 0 ]	start_range_addr
reg[NUM_RC_BURST_BITS - 1 : 0 ]	frame_size
reg[LAST_FRAME_BITS - 1 : 0 ]	last_frame_number
reg[NUM_RC_BURST_BITS - 1 : 0 ]	start_addr
reg[NUM_RC_BURST_BITS - 1 : 0 ]	next_frame_start_addr
reg[LAST_FRAME_BITS - 1 : 0 ]	frame_number_cntr
reg[LAST_FRAME_BITS - 1 : 0 ]	frame_number_current
reg	is_last_frame
reg[ 4 : 0 ]	frame_start_r
reg[FRAME_WIDTH_BITS : 0 ]	frame_full_width
reg[FRAME_WIDTH_BITS : 0 ]	window_width
reg[FRAME_HEIGHT_BITS : 0 ]	window_height
reg[FRAME_WIDTH_BITS - 1 : 0 ]	window_x0
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	window_y0
reg[FRAME_WIDTH_BITS - 1 : 0 ]	start_x
reg[FRAME_HEIGHT_BITS - 1 : 0 ]	start_y
reg	xfer_done_d
integer	i
wire	xfer_limited_by_mem_page
reg	xfer_limited_by_mem_page_r
wire	start_skip_w
reg	start_skip_r
reg	skip_run
reg	xfer_reject_r
reg	frame_start_pending
reg[ 1 : 0 ]	frame_start_pending_long
wire	xfer_done_skipped
wire	frame_start_delayed
wire	frame_start_mod
wire	start_not_partial