idelay_fine_pipe Module Reference

Inheritance diagram for idelay_fine_pipe:

Collaboration diagram for idelay_fine_pipe:

Static Public Member Functions

Always Constructs
ALWAYS_551	( clk )

Public Attributes

Inputs
clk
rst
set
ld
delay	[ 7 : 0 ]
data_in

Outputs
data_out

Parameters
IODELAY_GRP	"IODELAY_MEMORY"
DELAY_VALUE	integer 0
REFCLK_FREQUENCY	real 200 . 0
HIGH_PERFORMANCE_MODE	"FALSE"

Signals
reg[ 2 : 0 ]	fdly_pre
reg[ 2 : 0 ]	fdly

Module Instances
IDELAYE2_FINEDELAY::idelay2_finedelay_i	Module IDELAYE2_FINEDELAY

Detailed Description

Definition at line 41 of file idelay_fine_pipe.v.

Member Function Documentation

ALWAYS_551 (   clk   )

Always Construct

Definition at line 58 of file idelay_fine_pipe.v.

Member Data Documentation

IODELAY_GRP "IODELAY_MEMORY"

Parameter

Definition at line 43 of file idelay_fine_pipe.v.

DELAY_VALUE 0

Parameter

Definition at line 44 of file idelay_fine_pipe.v.

REFCLK_FREQUENCY 200 . 0

Parameter

Definition at line 45 of file idelay_fine_pipe.v.

HIGH_PERFORMANCE_MODE "FALSE"

Parameter

Definition at line 46 of file idelay_fine_pipe.v.

clk

Input

Definition at line 48 of file idelay_fine_pipe.v.

rst

Input

Definition at line 49 of file idelay_fine_pipe.v.

set

Input

Definition at line 50 of file idelay_fine_pipe.v.

ld

Input

Definition at line 51 of file idelay_fine_pipe.v.

delay [ 7 : 0 ]

Input

Definition at line 52 of file idelay_fine_pipe.v.

data_in

Input

Definition at line 53 of file idelay_fine_pipe.v.

data_out

Output

Definition at line 54 of file idelay_fine_pipe.v.

fdly_pre

Signal

Definition at line 57 of file idelay_fine_pipe.v.

fdly

Signal

Definition at line 57 of file idelay_fine_pipe.v.

IDELAYE2_FINEDELAY idelay2_finedelay_i

Module Instance

Definition at line 70 of file idelay_fine_pipe.v.

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The documentation for this Module was generated from the following files:

• wrap/idelay_fine_pipe.v