x393
1.0
FPGAcodeforElphelNC393camera
idelay_fine_pipe.v
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1
39
`timescale 1ns/1ps
40
41
module
idelay_fine_pipe
42
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
43
# (
parameter
IODELAY_GRP
=
"IODELAY_MEMORY"
,
44
parameter
integer
DELAY_VALUE
=
0
,
45
parameter
real
REFCLK_FREQUENCY
=
200.0
,
46
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
47
) (
48
input
clk
,
49
input
rst
,
50
input
set
,
51
input
ld
,
52
input
[
7
:
0
]
delay
,
53
input
data_in
,
54
output
data_out
55
);
56
57
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
],
fdly
=
DELAY_VALUE
[
2
:
0
];
58
always
@ (
posedge
clk
)
begin
59
if
(
rst
)
fdly_pre
<=
DELAY_VALUE
[
2
:
0
];
60
else
if
(
ld
)
fdly_pre
<=
delay
[
2
:
0
];
61
62
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
];
63
else
if
(
set
)
fdly
<=
fdly_pre
;
64
end
65
`ifdef
SIMULATION
66
reg
[7:0]
delay_r;
67
always
@
(posedge
clk)
begin
68
if
(rst)
delay_r
<=
DELAY_VALUE;
69
else
if
(ld)
delay_r
<=
delay;
70
end
71
always
@
(fdly_pre)
begin
72
if
(fdly_pre
>
3'h4)
$display
("ERROR: fine idelay value should be <5, specified %d (0x%x) @ %t",
delay_r,
fdly_pre,$time);
73
end
74
`endif
// SIMULATION
75
`ifndef
IGNORE_ATTR
76
(*
IODELAY_GROUP
=
IODELAY_GRP
*)
77
`endif
78
IDELAYE2_FINEDELAY
79
#(
80
.
CINVCTRL_SEL
(
"FALSE"
),
81
.
DELAY_SRC
(
"IDATAIN"
),
82
.
FINEDELAY
(
"ADD_DLY"
),
83
.
HIGH_PERFORMANCE_MODE
(
HIGH_PERFORMANCE_MODE
),
84
.
IDELAY_TYPE
(
"VAR_LOAD_PIPE"
),
85
.
IDELAY_VALUE
(
DELAY_VALUE
>>
3
),
86
// .IS_C_INVERTED(1'b0), // ISE does not have this parameter
87
// .IS_DATAIN_INVERTED(1'b0), // ISE does not have this parameter
88
// .IS_IDATAIN_INVERTED(1'b0), // ISE does not have this parameter
89
.
PIPE_SEL
(
"TRUE"
),
90
.
REFCLK_FREQUENCY
(
REFCLK_FREQUENCY
),
91
.
SIGNAL_PATTERN
(
"DATA"
)
92
)
93
idelay2_finedelay_i
(
94
.
CNTVALUEOUT
(),
95
.
DATAOUT
(
data_out
),
96
.
C
(
clk
),
97
.
CE
(
1'b0
),
98
.
CINVCTRL
(
1'b0
),
99
.
CNTVALUEIN
(
delay
[
7
:
3
]),
100
.
DATAIN
(
1'b0
),
101
.
IDATAIN
(
data_in
),
102
.
IFDLY
(
fdly
),
103
.
INC
(
1'b0
),
104
.
LD
(
set
),
105
.
LDPIPEEN
(
ld
),
106
.
REGRST
(
rst
)
107
);
108
109
endmodule
110
111
idelay_fine_pipe.11263clk
11263clk
Definition:
idelay_fine_pipe.v:48
idelay_fine_pipe.11267delay
[7:0] 11267delay
Definition:
idelay_fine_pipe.v:52
idelay_fine_pipe.11269data_out
11269data_out
Definition:
idelay_fine_pipe.v:54
idelay_fine_pipe.11271fdly
11271fdlyreg[2:0]
Definition:
idelay_fine_pipe.v:57
idelay_fine_pipe.11270fdly_pre
11270fdly_prereg[2:0]
Definition:
idelay_fine_pipe.v:57
idelay_fine_pipe.11268data_in
11268data_in
Definition:
idelay_fine_pipe.v:53
idelay_fine_pipe.11264rst
11264rst
Definition:
idelay_fine_pipe.v:49
idelay_fine_pipe.IDELAYE2_FINEDELAY
idelay2_finedelay_i IDELAYE2_FINEDELAY
Definition:
idelay_fine_pipe.v:70
idelay_fine_pipe.11261REFCLK_FREQUENCY
real 11261REFCLK_FREQUENCY200.0
Definition:
idelay_fine_pipe.v:45
idelay_fine_pipe.11262HIGH_PERFORMANCE_MODE
11262HIGH_PERFORMANCE_MODE"FALSE"
Definition:
idelay_fine_pipe.v:46
idelay_fine_pipe.11265set
11265set
Definition:
idelay_fine_pipe.v:50
idelay_fine_pipe
Definition:
idelay_fine_pipe.v:41
idelay_fine_pipe.11259IODELAY_GRP
11259IODELAY_GRP"IODELAY_MEMORY"
Definition:
idelay_fine_pipe.v:43
idelay_fine_pipe.11266ld
11266ld
Definition:
idelay_fine_pipe.v:51
idelay_fine_pipe.11260DELAY_VALUE
integer 11260DELAY_VALUE0
Definition:
idelay_fine_pipe.v:44
wrap
idelay_fine_pipe.v
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