x393
1.0
FPGAcodeforElphelNC393camera
odelay_fine_pipe.v
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1
39
`timescale 1ns/1ps
40
41
module
odelay_fine_pipe
42
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
43
# (
parameter
IODELAY_GRP
=
"IODELAY_MEMORY"
,
44
parameter
[
7
:
0
]
DELAY_VALUE
=
0
,
45
parameter
real
REFCLK_FREQUENCY
=
200.0
,
46
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
47
) (
48
input
clk
,
49
input
rst
,
50
input
set
,
51
input
ld
,
52
input
[
7
:
0
]
delay
,
53
input
data_in
,
54
output
data_out
55
);
56
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
],
fdly
=
DELAY_VALUE
[
2
:
0
];
57
always
@ (
posedge
clk
)
begin
58
if
(
rst
)
fdly_pre
<=
DELAY_VALUE
[
2
:
0
];
59
else
if
(
ld
)
fdly_pre
<=
delay
[
2
:
0
];
60
61
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
];
62
else
if
(
set
)
fdly
<=
fdly_pre
;
63
end
64
`ifdef
SIMULATION
65
reg
[7:0]
delay_r;
66
always
@
(posedge
clk)
begin
67
if
(rst)
delay_r
<=
DELAY_VALUE;
68
else
if
(ld)
delay_r
<=
delay;
69
end
70
always
@
(fdly_pre)
begin
71
if
(fdly_pre
>
3'h4)
$display
("ERROR: fine odelay value should be <5, specified %d (0x%x) @ %t",
fdly_pre,
delay_r,$time);
72
end
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`endif
//SIMULATION
74
75
`ifndef
IGNORE_ATTR
76
(*
IODELAY_GROUP
=
IODELAY_GRP
*)
77
`endif
78
ODELAYE2_FINEDELAY
79
#(
80
.
CINVCTRL_SEL
(
"FALSE"
),
81
.
DELAY_SRC
(
"ODATAIN"
),
82
.
FINEDELAY
(
"ADD_DLY"
),
83
.
HIGH_PERFORMANCE_MODE
(
HIGH_PERFORMANCE_MODE
),
84
.
ODELAY_TYPE
(
"VAR_LOAD_PIPE"
),
85
.
ODELAY_VALUE
(
DELAY_VALUE
>>
3
),
86
// .IS_C_INVERTED(1'b0), // ISE does not have this parameter
87
// .IS_ODATAIN_INVERTED(1'b0), // ISE does not have this parameter
88
.
PIPE_SEL
(
"TRUE"
),
89
.
REFCLK_FREQUENCY
(
REFCLK_FREQUENCY
),
90
.
SIGNAL_PATTERN
(
"DATA"
)
91
)
92
odelay2_finedelay_i
(
93
.
CNTVALUEOUT
(),
94
.
DATAOUT
(
data_out
),
95
.
C
(
clk
),
96
.
CE
(
1'b0
),
97
.
CINVCTRL
(
1'b0
),
98
.
CNTVALUEIN
(
delay
[
7
:
3
]),
99
.
CLKIN
(
1'b0
),
100
.
ODATAIN
(
data_in
),
101
.
OFDLY
(
fdly
),
102
.
INC
(
1'b0
),
103
.
LD
(
set
),
104
.
LDPIPEEN
(
ld
),
105
.
REGRST
(
rst
)
106
);
107
108
endmodule
109
110
odelay_fine_pipe.11513HIGH_PERFORMANCE_MODE
11513HIGH_PERFORMANCE_MODE"FALSE"
Definition:
odelay_fine_pipe.v:46
odelay_fine_pipe.11516set
11516set
Definition:
odelay_fine_pipe.v:50
odelay_fine_pipe.11522fdly
11522fdlyreg[2:0]
Definition:
odelay_fine_pipe.v:56
odelay_fine_pipe.11518delay
[7:0] 11518delay
Definition:
odelay_fine_pipe.v:52
odelay_fine_pipe.11514clk
11514clk
Definition:
odelay_fine_pipe.v:48
odelay_fine_pipe.ODELAYE2_FINEDELAY
odelay2_finedelay_i ODELAYE2_FINEDELAY
Definition:
odelay_fine_pipe.v:70
odelay_fine_pipe.11515rst
11515rst
Definition:
odelay_fine_pipe.v:49
odelay_fine_pipe.11519data_in
11519data_in
Definition:
odelay_fine_pipe.v:53
odelay_fine_pipe.11520data_out
11520data_out
Definition:
odelay_fine_pipe.v:54
odelay_fine_pipe.11511DELAY_VALUE
[7:0] 11511DELAY_VALUE0
Definition:
odelay_fine_pipe.v:44
odelay_fine_pipe
Definition:
odelay_fine_pipe.v:41
odelay_fine_pipe.11521fdly_pre
11521fdly_prereg[2:0]
Definition:
odelay_fine_pipe.v:56
odelay_fine_pipe.11517ld
11517ld
Definition:
odelay_fine_pipe.v:51
odelay_fine_pipe.11510IODELAY_GRP
11510IODELAY_GRP"IODELAY_MEMORY"
Definition:
odelay_fine_pipe.v:43
odelay_fine_pipe.11512REFCLK_FREQUENCY
real 11512REFCLK_FREQUENCY200.0
Definition:
odelay_fine_pipe.v:45
wrap
odelay_fine_pipe.v
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