x393  1.0
FPGAcodeforElphelNC393camera
csconvert.v
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1 
39 `timescale 1ns/1ps
40 
41 module csconvert#(
42  parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
43  parameter CMPRS_COLOR20 = 1, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented)
44  parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
45  parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
46  parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
47  parameter CMPRS_MONO8 = 7 // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
48 )(
49  input xclk,
50  input frame_en,
51  input [ 2:0] converter_type,
52 
53  input ignore_color, //zero Cb/Cr components
54 // input four_blocks, // use only 4 blocks for the output, not 6
55 // input jp4_dc_improved, // in JP4 mode, compare DC coefficients to the same color ones
56  input scale_diff, // divide differences by 2 (to fit in 8-bit range)
57  input hdr, // second green absolute, not difference
58  input limit_diff, // 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream (==1)
59  input [ 9:0] m_cb, // [9:0] scale for CB - default 0.564 (10'h90)
60  input [ 9:0] m_cr, // [9:0] scale for CB - default 0.713 (10'hb6)
61  input [ 7:0] mb_din, // input bayer data in scanline sequence, GR/BG sequence
62  input [ 1:0] bayer_phase,
63  input pre2_first_in, // marks the first input pixel (2 cycles ahead)
64 
65  output reg [ 8:0] signed_y, // - now signed char, -128(black) to +127 (white)
66  output reg [ 8:0] signed_c, // new, q is just signed char
67  output reg [ 7:0] yaddrw, // address for the external buffer memory to write 16x16x8bit Y data
68  output reg ywe, // wrire enable of Y data
69  output reg [ 7:0] caddrw, // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
70  output reg cwe, // write enable for CbCr data
71  output reg pre_first_out,
72 
73 // output reg pre_color_enable,
74 // output reg ccv_out_start, //TODO: adjust to minimal latency?
75  output reg [ 7:0] n000, // not clear how they are used, make them just with latency1 from old
76  output reg [ 7:0] n255);
78  // outputs to be multiplexed:
85 
88 
89  reg [ 7:0] en_converters;
90  reg ignore_color_r; //zero Cb/Cr components
91  reg [2:0] converter_type_r;
92 // reg jp4_dc_improved_r;
93 // reg four_blocks_r;
95  reg hdr_r;
96 // reg [1:0] tile_margin_r;
97  reg [1:0] bayer_phase_r;
98 // reg [3:0] bayer_phase_onehot;
99 // wire limit_diff = 1'b1; // as in the prototype - just a constant 1
100 /*
101  reg [5:0] component_numsLS; // component_num [0]
102  reg [5:0] component_numsMS; // component_num [1]
103  reg [5:0] component_numsHS; // component_num [2]
104  reg [5:0] component_colorsS; // use color quantization table (YCbCR, jp4diff)
105  reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
106 */
107  always @ (posedge xclk) begin
109  if (pre2_first_in) begin
110  converter_type_r [2:0] <= converter_type[2:0];
112 // jp4_dc_improved_r <= jp4_dc_improved;
113 // four_blocks_r <= four_blocks;
115  hdr_r <= hdr;
116 // tile_margin_r[1:0] <= tile_margin[1:0];
117  bayer_phase_r[1:0] <= bayer_phase[1:0];
118 // bayer_phase_onehot[3:0]<={(bayer_phase[1:0]==2'h3)?1'b1:1'b0,
119 // (bayer_phase[1:0]==2'h2)?1'b1:1'b0,
120 // (bayer_phase[1:0]==2'h1)?1'b1:1'b0,
121 // (bayer_phase[1:0]==2'h0)?1'b1:1'b0};
122  end
123 
124  // generate one-hot converter enable
127 
130 
131  if (!frame_en) en_converters[CMPRS_MONO16] <= 0;
133 
134  if (!frame_en) en_converters[CMPRS_JP4] <= 0;
136 
139 
140  if (!frame_en) en_converters[CMPRS_MONO8] <= 0;
142  end
143 
144 
145  csconvert18a i_csconvert18 (
146  .RST (!en_converters[CMPRS_COLOR18]), // input
147  .CLK (xclk), // input
148  .mono (ignore_color_r), // input
149  .limit_diff (limit_diff), // input 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream
150  .m_cb (m_cb[9:0]), // input[9:0] scale for CB - default 0.564 (10'h90)
151  .m_cr (m_cr[9:0]), // input[9:0] scale for CB - default 0.713 (10'hb6)
152  .din (mb_din[7:0]), // input[7:0]
153  .pre_first_in (pre_first_in), // input
154  .signed_y (conv18_signed_y[7:0]),// output[7:0]
155  .q (conv18_signed_c[8:0]),// output[8:0]
156  .yaddr (conv18_yaddrw[7:0]), // output[7:0]
157  .ywe (conv18_ywe), // output
158  .caddr (conv18_caddrw[6:0]), // output[6:0]
159  .cwe (conv18_cwe), // output
161  .bayer_phase (bayer_phase_r[1:0]), // input[1:0]
162  .n000 (conv18_n000[7:0]), // output[7:0]
163  .n255 (conv18_n255[7:0])); // output[7:0]
164 
165  csconvert_mono i_csconvert_mono (
167  .clk (xclk),
168  .din (mb_din[7:0]),
170  .y_out (mono16_signed_y[7:0]),
171  .yaddr (mono16_yaddrw[7:0]),
172  .ywe (mono16_ywe),
174  csconvert_jp4 i_csconvert_jp4 (
176  .clk (xclk),
177  .din (mb_din[7:0]),
179  .y_out (jp4_signed_y[7:0]),
180  .yaddr (jp4_yaddrw[7:0]),
181  .ywe (jp4_ywe),
183 
184  csconvert_jp4diff i_csconvert_jp4diff (
186  .clk (xclk),
188  .hdr (hdr_r),
189  .din (mb_din[7:0]),
191  .y_out (jp4diff_signed_y[8:0]),
192  .yaddr (jp4diff_yaddrw[7:0]),
193  .ywe (jp4diff_ywe),
195  .bayer_phase (bayer_phase_r[1:0]));
196 
197 
198  //TODO: temporary plugs, until module for 20x20 is created
199  // will be wrong, of course
200  assign conv20_signed_y[7:0]= conv18_signed_y[7:0];
201  assign conv20_yaddrw[7:0]= conv18_yaddrw[7:0];
202  assign conv20_ywe= conv18_ywe;
203  assign conv20_signed_c[8:0]= conv18_signed_c[8:0];
204  assign conv20_caddrw[6:0]= conv18_caddrw[6:0];
205  assign conv20_cwe= conv18_cwe;
207  // TODO: temporary assign N000 and N255 for other (not csconvert18) modes until they are implemented in those modules
208 
209  assign conv20_n000= conv18_n000;
210  assign mono16_n000= conv18_n000;
211  assign jp4_n000= conv18_n000;
212  assign jp4diff_n000= conv18_n000;
213  assign conv20_n255= conv18_n255;
214  assign mono16_n255= conv18_n255;
215  assign jp4_n255= conv18_n255;
216  assign jp4diff_n255= conv18_n255;
217 
218 // multiplex outputs
219  // average for each block should be calculated before the data goes to output output
220  always @ (posedge xclk) case (converter_type_r[2:0])
221  CMPRS_COLOR18:begin //color 18
223  signed_y[8:0] <= {conv18_signed_y[7],conv18_signed_y[7:0]};
224  ywe <= conv18_ywe;
226  signed_c[8:0] <= {conv18_signed_c[8:0]};
227  cwe <= conv18_cwe;
228  caddrw[7:0] <= {1'b0,conv18_caddrw[6:0]};
229  n000 <= conv18_n000;
230  n255 <= conv18_n255;
231 // pre_color_enable <= 1'b1;
232 // ccv_out_start <= (conv18_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency?
233  end
234  CMPRS_COLOR20:begin //color 20
236  signed_y[8:0] <= {conv20_signed_y[7],conv20_signed_y[7:0]};
237  ywe <= conv20_ywe;
239  signed_c[8:0] <= {conv20_signed_c[8:0]};
240  cwe <= conv20_cwe;
241  caddrw[7:0] <= {1'b0,conv20_caddrw[6:0]};
242  n000 <= conv20_n000;
243  n255 <= conv20_n255;
244 
245  // pre_color_enable <= 1'b1;
246  // ccv_out_start <= (conv20_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency?
247  end
248  CMPRS_MONO16:begin //mono
250  signed_y[8:0] <= {mono16_signed_y[7],mono16_signed_y[7:0]};
251  ywe <= mono16_ywe;
253  signed_c[8:0] <= 9'h0;
254  cwe <= 1'b0;
255  caddrw[7:0] <= 8'h0;
256  n000 <= mono16_n000;
257  n255 <= mono16_n255;
258 
259 // pre_color_enable <= 1'b0;
260 // ccv_out_start <= accYdone[0];
261  end
262  CMPRS_JP4:begin // jp4
264  signed_y[8:0] <= {jp4_signed_y[7],jp4_signed_y[7:0]};
265  ywe <= jp4_ywe;
266  yaddrw[7:0] <= {jp4_yaddrw[7],jp4_yaddrw[3],jp4_yaddrw[6:4],jp4_yaddrw[2:0]};
267  signed_c[8:0] <= 9'h0;
268  cwe <= 1'b0;
269  caddrw[7:0] <= 8'h0;
270  n000 <= jp4_n000;
271  n255 <= jp4_n255;
272 
273 // pre_color_enable <= 1'b0;
274 // ccv_out_start <= accYdone[0];
275  end
276  CMPRS_JP4DIFF:begin //jp4diff
278  signed_y[8:0] <= {jp4diff_signed_y[8:0]};
279  ywe <= jp4diff_ywe;
281  signed_c[8:0] <= 9'h0;
282  cwe <= 1'b0;
283  caddrw[7:0] <= 8'h0;
284  n000 <= jp4diff_n000;
285  n255 <= jp4diff_n255;
286 
287 // pre_color_enable <= 1'b0;
288 // ccv_out_start <= accYdone[0];
289  end
290  default:begin //color 18 (or try 'X'
291  pre_first_out <= 'bx; // conv18_pre_first_out;
292  signed_y[8:0] <= 'bx; // {conv18_signed_y[7],conv18_signed_y[7:0]};
293  ywe <= 'bx; //conv18_ywe;
294  yaddrw[7:0] <= 'bx; //{conv18_yaddrw[7],conv18_yaddrw[3],conv18_yaddrw[6:4],conv18_yaddrw[2:0]};
295  signed_c[8:0] <= 'bx; //{conv18_signed_c[8:0]};
296  cwe <= 'bx; //conv18_cwe;
297  caddrw[7:0] <= 'bx; //{1'b0,conv18_caddrw[6:0]};
298  n000 <= 'bx; //conv18_n000;
299  n255 <= 'bx; //conv18_n255;
300  end
301 
302  endcase
303 
304 
305 
306 
307 
308 endmodule
309 
2071conv18_caddrwwire[6:0]
Definition: csconvert.v:82
[ 7:0] 2111yaddr
Definition: csconvert18a.v:250
2095en_convertersreg[7:0]
Definition: csconvert.v:89
2062jp4_signed_ywire[7:0]
Definition: csconvert.v:79
2087mono16_n000wire[7:0]
Definition: csconvert.v:86
2036CMPRS_MONO87
Definition: csconvert.v:47
[ 2:0] 2039converter_type
Definition: csconvert.v:51
2093jp4_n255wire[7:0]
Definition: csconvert.v:87
reg [ 7:0] 2056n000
Definition: csconvert.v:75
2073conv18_ywewire
Definition: csconvert.v:83
2090conv18_n255wire[7:0]
Definition: csconvert.v:87
2031CMPRS_COLOR180
Definition: csconvert.v:42
i_csconvert18 csconvert18a
Definition: csconvert.v:145
2066conv18_yaddrwwire[7:0]
Definition: csconvert.v:81
2226y_outwire[7:0]
Definition: csconvert_jp4.v:60
2032CMPRS_COLOR201
Definition: csconvert.v:43
2082mono16_pre_first_outwire
Definition: csconvert.v:84
2084jp4diff_pre_first_outwire
Definition: csconvert.v:84
2089jp4diff_n000wire[7:0]
Definition: csconvert.v:86
2097converter_type_rreg[2:0]
Definition: csconvert.v:91
2100bayer_phase_rreg[1:0]
Definition: csconvert.v:97
2063jp4diff_signed_ywire[8:0]
Definition: csconvert.v:80
2075conv20_ywewire
Definition: csconvert.v:83
2081conv20_pre_first_outwire
Definition: csconvert.v:84
reg 2055pre_first_out
Definition: csconvert.v:71
2099hdr_rreg
Definition: csconvert.v:95
[ 6:0] 2113caddr
Definition: csconvert18a.v:252
i_csconvert_jp4diff csconvert_jp4diff
Definition: csconvert.v:184
[ 7:0] 2107din
Definition: csconvert18a.v:246
2033CMPRS_MONO162
Definition: csconvert.v:44
[ 9:0] 2045m_cr
Definition: csconvert.v:60
2229yaddrwire[7:0]
Definition: csconvert_jp4.v:63
2083jp4_pre_first_outwire
Definition: csconvert.v:84
[ 7:0] 2118n255
Definition: csconvert18a.v:257
[ 8:0] 2110q
Definition: csconvert18a.v:249
[ 1:0] 2047bayer_phase
Definition: csconvert.v:62
2078jp4_ywewire
Definition: csconvert.v:83
2076conv20_cwewire
Definition: csconvert.v:83
reg 2054cwe
Definition: csconvert.v:70
2059conv18_signed_ywire[7:0]
Definition: csconvert.v:79
2286y_outwire[7:0]
reg 2052ywe
Definition: csconvert.v:68
2065conv20_signed_cwire[8:0]
Definition: csconvert.v:80
2079jp4diff_ywewire
Definition: csconvert.v:83
2072conv20_caddrwwire[6:0]
Definition: csconvert.v:82
2092mono16_n255wire[7:0]
Definition: csconvert.v:87
2038frame_en
Definition: csconvert.v:50
2070jp4diff_yaddrwwire[7:0]
Definition: csconvert.v:81
2068mono16_yaddrwwire[7:0]
Definition: csconvert.v:81
2225pre_first_outwire
Definition: csconvert_jp4.v:59
[ 9:0] 2044m_cb
Definition: csconvert.v:59
2034CMPRS_JP43
Definition: csconvert.v:45
2098scale_diff_rreg
Definition: csconvert.v:94
2074conv18_cwewire
Definition: csconvert.v:83
2048pre2_first_in
Definition: csconvert.v:63
2069jp4_yaddrwwire[7:0]
Definition: csconvert.v:81
2067conv20_yaddrwwire[7:0]
Definition: csconvert.v:81
2086conv20_n000wire[7:0]
Definition: csconvert.v:86
2077mono16_ywewire
Definition: csconvert.v:83
2085conv18_n000wire[7:0]
Definition: csconvert.v:86
2040ignore_color
Definition: csconvert.v:53
reg [ 7:0] 2053caddrw
Definition: csconvert.v:69
i_csconvert_jp4 csconvert_jp4
Definition: csconvert.v:174
reg [ 7:0] 2051yaddrw
Definition: csconvert.v:67
reg [ 8:0] 2049signed_y
Definition: csconvert.v:65
i_csconvert_mono csconvert_mono
Definition: csconvert.v:165
[ 7:0] 2109signed_y
Definition: csconvert18a.v:248
2080conv18_pre_first_outwire
Definition: csconvert.v:84
2061mono16_signed_ywire[7:0]
Definition: csconvert.v:79
2060conv20_signed_ywire[7:0]
Definition: csconvert.v:79
2064conv18_signed_cwire[8:0]
Definition: csconvert.v:80
2091conv20_n255wire[7:0]
Definition: csconvert.v:87
[ 7:0] 2117n000
Definition: csconvert18a.v:256
[ 1:0] 2116bayer_phase
Definition: csconvert18a.v:255
2287yaddrreg[7:0]
[ 9:0] 2106m_cr
Definition: csconvert18a.v:245
2094jp4diff_n255wire[7:0]
Definition: csconvert.v:87
2035CMPRS_JP4DIFF4
Definition: csconvert.v:46
2088jp4_n000wire[7:0]
Definition: csconvert.v:86
reg [ 8:0] 2050signed_c
Definition: csconvert.v:66
[ 7:0] 2046mb_din
Definition: csconvert.v:61
reg [ 7:0] 2057n255
Definition: csconvert.v:76
2058pre_first_inreg
Definition: csconvert.v:77
2096ignore_color_rreg
Definition: csconvert.v:90
2043limit_diff
Definition: csconvert.v:58
[7:0] 2219din
Definition: csconvert_jp4.v:52
[ 9:0] 2105m_cb
Definition: csconvert18a.v:244
2041scale_diff
Definition: csconvert.v:56