42 parameter CMPRS_COLOR18 =
0,
// JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer 43 parameter CMPRS_COLOR20 =
1,
// JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer (not implemented) 44 parameter CMPRS_MONO16 =
2,
// JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed 45 parameter CMPRS_JP4 =
3,
// JP4 mode with 16x16 macroblocks 47 parameter CMPRS_MONO8 =
7 // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented) 54 // input four_blocks, // use only 4 blocks for the output, not 6 55 // input jp4_dc_improved, // in JP4 mode, compare DC coefficients to the same color ones 56 input scale_diff,
// divide differences by 2 (to fit in 8-bit range) 57 input hdr,
// second green absolute, not difference 58 input limit_diff,
// 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream (==1) 59 input [
9:
0]
m_cb,
// [9:0] scale for CB - default 0.564 (10'h90) 60 input [
9:
0]
m_cr,
// [9:0] scale for CB - default 0.713 (10'hb6) 61 input [
7:
0]
mb_din,
// input bayer data in scanline sequence, GR/BG sequence 65 output reg [
8:
0]
signed_y,
// - now signed char, -128(black) to +127 (white) 66 output reg [
8:
0]
signed_c,
// new, q is just signed char 67 output reg [
7:
0]
yaddrw,
// address for the external buffer memory to write 16x16x8bit Y data 68 output reg ywe,
// wrire enable of Y data 69 output reg [
7:
0]
caddrw,
// address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr) 70 output reg cwe,
// write enable for CbCr data 73 // output reg pre_color_enable, 74 // output reg ccv_out_start, //TODO: adjust to minimal latency? 75 output reg [
7:
0]
n000,
// not clear how they are used, make them just with latency1 from old 78 // outputs to be multiplexed: 92 // reg jp4_dc_improved_r; 96 // reg [1:0] tile_margin_r; 98 // reg [3:0] bayer_phase_onehot; 99 // wire limit_diff = 1'b1; // as in the prototype - just a constant 1 101 reg [5:0] component_numsLS; // component_num [0] 102 reg [5:0] component_numsMS; // component_num [1] 103 reg [5:0] component_numsHS; // component_num [2] 104 reg [5:0] component_colorsS; // use color quantization table (YCbCR, jp4diff) 105 reg [5:0] component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous) 112 // jp4_dc_improved_r <= jp4_dc_improved; 113 // four_blocks_r <= four_blocks; 116 // tile_margin_r[1:0] <= tile_margin[1:0]; 118 // bayer_phase_onehot[3:0]<={(bayer_phase[1:0]==2'h3)?1'b1:1'b0, 119 // (bayer_phase[1:0]==2'h2)?1'b1:1'b0, 120 // (bayer_phase[1:0]==2'h1)?1'b1:1'b0, 121 // (bayer_phase[1:0]==2'h0)?1'b1:1'b0}; 124 // generate one-hot converter enable 149 .
limit_diff (
limit_diff),
// input 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream 150 .
m_cb (
m_cb[
9:
0]),
// input[9:0] scale for CB - default 0.564 (10'h90) 151 .
m_cr (
m_cr[
9:
0]),
// input[9:0] scale for CB - default 0.713 (10'hb6) 198 //TODO: temporary plugs, until module for 20x20 is created 199 // will be wrong, of course 207 // TODO: temporary assign N000 and N255 for other (not csconvert18) modes until they are implemented in those modules 219 // average for each block should be calculated before the data goes to output output 231 // pre_color_enable <= 1'b1; 232 // ccv_out_start <= (conv18_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency? 245 // pre_color_enable <= 1'b1; 246 // ccv_out_start <= (conv20_yaddrw[7:0]==8'hc5); //TODO: adjust to minimal latency? 259 // pre_color_enable <= 1'b0; 260 // ccv_out_start <= accYdone[0]; 273 // pre_color_enable <= 1'b0; 274 // ccv_out_start <= accYdone[0]; 287 // pre_color_enable <= 1'b0; 288 // ccv_out_start <= accYdone[0]; 290 default:
begin //color 18 (or try 'X' 292 signed_y[
8:
0] <=
'bx;
// {conv18_signed_y[7],conv18_signed_y[7:0]}; 293 ywe <=
'bx;
//conv18_ywe; 294 yaddrw[
7:
0] <=
'bx;
//{conv18_yaddrw[7],conv18_yaddrw[3],conv18_yaddrw[6:4],conv18_yaddrw[2:0]}; 295 signed_c[
8:
0] <=
'bx;
//{conv18_signed_c[8:0]}; 296 cwe <=
'bx;
//conv18_cwe; 297 caddrw[
7:
0] <=
'bx;
//{1'b0,conv18_caddrw[6:0]}; 298 n000 <=
'bx;
//conv18_n000; 299 n255 <=
'bx;
//conv18_n255;
2071conv18_caddrwwire[6:0]
2095en_convertersreg[7:0]
2062jp4_signed_ywire[7:0]
[ 2:0] 2039converter_type
i_csconvert18 csconvert18a
2066conv18_yaddrwwire[7:0]
2082mono16_pre_first_outwire
2084jp4diff_pre_first_outwire
2089jp4diff_n000wire[7:0]
2097converter_type_rreg[2:0]
2100bayer_phase_rreg[1:0]
2063jp4diff_signed_ywire[8:0]
2081conv20_pre_first_outwire
i_csconvert_jp4diff csconvert_jp4diff
2083jp4_pre_first_outwire
2059conv18_signed_ywire[7:0]
2065conv20_signed_cwire[8:0]
2072conv20_caddrwwire[6:0]
2070jp4diff_yaddrwwire[7:0]
2068mono16_yaddrwwire[7:0]
2067conv20_yaddrwwire[7:0]
i_csconvert_jp4 csconvert_jp4
i_csconvert_mono csconvert_mono
2080conv18_pre_first_outwire
2061mono16_signed_ywire[7:0]
2060conv20_signed_ywire[7:0]
2064conv18_signed_cwire[8:0]
2094jp4diff_n255wire[7:0]