x393
1.0
FPGAcodeforElphelNC393camera
csconvert18a.v
Go to the documentation of this file.
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// 2015: Updating for 393, removing old SRL16 primitives
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/*
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09/07/2002 Andrey Filippov
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Compared to spreadsheet simulation. Y - matches, CbCr in ~25% give result one less than spreadsheet simulation.
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It is always odd and s.s. gives next even
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TODO: optimize sequencing counters and possibly add some extra bits - as to calculate int((a+b+c+d)/4)
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instead of int((int((a+b)/2)+int((c+d)/2))/2)
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Color space converter processes one MCU at a time. It receives 18x18 8-bit bayer pixels (now it is always in (GR/BG)
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sequence). With some latency it will produce 16x16x8 bit Y data (could be some artifacts on the borders) in scan-line
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sequence and clock rate and Cb and Cr at the same time at half rate, so 4:2:0 will be generated at the same
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time.
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update: now it processes overlapping tiles (18x18) to avoid problems on the MCU boarders
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Y= 0.299*R+0.587*G+0.114*B
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Cb=-0.168*R-0.3313*G+0.5*B = 0.564*(B-Y)+128
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Cr=0.5*R-0.4187*G-0.0813*B = 0.713*(R-Y)+128
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For Bayer array (GR/BG)(bayer_phase[1:0]==0), and pixels P[Y,X]:
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R[0,0]=0.5* (P[0,-1]+P[0,1])
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R[0,1]= P[0,1]
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R[1,0]=0.25*(P[0,-1]+P[0,1]+P[2,-1]+P[2,1])
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R[1,1]=0.5 *(P[0,1] +P[2,1])
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G[0,0]= P[0,0]
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G[0,1]=0.25*(P[-1,1]+P[0,0]+P[0,2]+P[1,1])
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G[1,0]=0.25*(P[0,0]+P[1,-1]+P[1,1]+P[2,0])
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G[1,1]= P[1,1]
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B[0,0]=0.5* (P[-1,0]+P[1,0])
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B[0,1]=0.25*(P[-1,0]+P[-1,2]+P[1,0]+P[1,2])
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B[1,0]= P[1,0]
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B[1,1]=0.5* (P[1,0]+P[1,2])
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Y[0,0]=0.299*0.5*(P[0,-1]+P[0,1]) + 0.587*P[0,0] + 0.114*0.5* (P[-1,0]+P[1,0])
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Y[0,1]=0.299*P[0,1]+0.587*0.25*(P[-1,1]+P[0,0]+P[0,2]+P[1,1])+0.114*0.25*(P[-1,0]+P[-1,2]+P[1,0]+P[1,2])
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Y[1,0]=0.299*0.25*(P[0,-1]+P[0,1]+P[2,-1]+P[2,1])+0.587*0.25*(P[0,0]+P[1,-1]+P[1,1]+P[2,0])+0.114*P[1,0]
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Y[1,1]=0.299*0.5 *(P[0,1] +P[2,1])+0.587*P[1,1]+0.114*0.5* (P[1,0]+P[1,2])
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Y[0,0]=(0x96*P[0,0]+ 0x4d*((P[0,-1]+P[0,1])/2) + 0x1d*((P[-1,0]+P[1,0])/2))>>8
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Y[0,1]=(0x4d*P[0,1]+ 0x96*((P[-1,1]+P[0,0]+P[0,2]+P[1,1])/4)+ 0x1d*((P[-1,0]+P[-1,2]+P[1,0]+P[1,2])/4))>>8
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Y[1,0]=(0x1d*P[1,0]+ 0x96*((P[0,0]+P[1,-1]+P[1,1]+P[2,0])/4)+ 0x4d*((P[0,-1]+P[0,1]+P[2,-1]+P[2,1])/4))>>8
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Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2) + 0x4d*((P[0,1] +P[2,1])/2)))>>8
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Cb and Cy are needed 1 for each 4 pixels (4:2:0)
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(YC= 0.299*P[0,1]+0.587*(0.5*P[0,0]+P[1,1])+0.114*P[1,0] )
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Cb=0.564*(P[1,0]-(0.299*P[0,1]+0.587*0.5*(P[0,0]+P[1,1])+0.114*P[1,0]))+128
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Cr=0.713*(P[0,1]-(0.299*P[0,1]+0.587*0.5*(P[0,0]+P[1,1])+0.114*P[1,0]))+128
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Cb=0.564*(P[1,0]-(0.299*P[0,1]+0.587*0.5*(P[0,0]+P[1,1])+0.114*P[1,0]))+128=
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0.564*P[1,0]-0.299*0.564*P[0,1]-0.587*0.564*0.5*(P[0,0]+P[1,1])-0.114*0.564*P[1,0]))+128=
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0.564*P[1,0]-0.168636*P[0,1]-0.165534*P[0,0]-0.165534*P[1,1]-0.064638*P[1,0]+128=
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0.499362*P[1,0]-0.168636*P[0,1]-0.165534*P[0,0]-0.165534*P[1,1]+128=
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-0.165534*P[0,0] -0.168636*P[0,1] +0.499362*P[1,0] -0.165534*P[1,1]+ 128=
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(-256*0.165534*P[0,0] -256*0.168636*P[0,1] +256*0.499362*P[1,0] -256*0.165534*P[1,1])>>8+ 128=
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(-42.5*P[0,0] -43*P[0,1] +128*P[1,0] -42.5*P[1,1])>>8+ 128=
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(-85*((P[0,0]+P[1,1])/2) -43*P[0,1] +128*P[1,0])>>8+ 128=
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(-0x55*((P[0,0]+P[1,1])/2) -2b*P[0,1] +P[1,0]<<7)>>8+ 0x80=
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(-0x55*((P[0,0]+P[1,1])/2) -2b*P[0,1])>>8 +P[1,0]>>1 +0x80=
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Cr=0.713*(P[0,1]-(0.299*P[0,1]+0.587*0.5*(P[0,0]+P[1,1])+0.114*P[1,0]))+128=
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0.713* P[0,1]- 0.713*0.299*P[0,1] - 0.713*0.587*0.5*P[0,0]- 0.713*0.587*0.5*P[1,1] -0.713*0.114*P[1,0]+128=
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0.713* P[0,1]- 0.213187*P[0,1] - 0.2092655*P[0,0]- 0.2092655*P[1,1] -0.081282*P[1,0]+128=
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0.499813* P[0,1] -0.2092655*P[0,0] -0.2092655*P[1,1] -0.081282*P[1,0]+128=
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-0.2092655*P[0,0] +0.499813* P[0,1] -0.081282*P[1,0] -0.2092655*P[1,1] +128=
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(-256*0.2092655*P[0,0] +256*0.499813* P[0,1] -256*0.081282*P[1,0] -256*0.2092655*P[1,1])>>8 +128=
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(-54*P[0,0] +128* P[0,1] -21*P[1,0] -54*P[1,1])>>8 +128= // rounded up, sum=129 -> decreasing
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(-53.5*P[0,0] +128* P[0,1] -21*P[1,0] -53.5*P[1,1])>>8 +128=
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(-107*((P[0,0]+P[1,1])/2) +P[0,1]<<7 -21*P[1,0])>>8 +128=
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(-0x6b*((P[0,0]+P[1,1])/2) +P[0,1]<<7 -0x15*P[1,0])>>8 +0x80=
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(-0x6b*((P[0,0]+P[1,1])/2) -0x15*P[1,0])>>8 +P[0,1]>>1 +0x80=
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*/
/*
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For Bayer array (RG/GB)(bayer_phase[1:0]==1), and pixels P[Y,X]:
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R[0,0]= P[0,0]
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R[0,1]=0.5 *(P[0,0]+P[0,2])
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R[1,0]=0.5 *(P[0,0]+P[2,0])
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R[1,1]=0.25*(P[0,0]+P[0,2]+P[2,0]+P[2,2])
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G[0,0]=0.25*(P[-1,0]+P[0,-1]+P[0,1]+P[1,0])
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G[0,1]= P[0,1]
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G[1,0]= P[1,0]
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G[1,1]=0.25*(P[0,1]+P[1,0]+P[1,2]+P[2,1])
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B[0,0]=0.25*(P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1])
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B[0,1]=0.5* (P[-1,1]+P[1,1])
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B[1,0]=0.5* (P[1,-1]+P[1,1])
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B[1,1]= P[1,1]
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Y[0,0]=0.299*P[0,0] + 0.587*0.25*(P[-1,0]+P[0,-1]+P[0,1]+P[1,0]) + 0.114*0.25*(P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1])
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Y[0,1]=0.299*0.5 *(P[0,0]+P[0,2])+0.587*P[0,1]+0.114*0.5* (P[-1,1]+P[1,1])
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Y[1,0]=0.299*0.5 *(P[0,0]+P[2,0])+0.587*P[1,0]+0.114*0.5* (P[1,-1]+P[1,1])
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Y[1,1]=0.299*0.25*(P[0,0]+P[0,2]+P[2,0]+P[2,2])+0.587*0.25*(P[0,1]+P[1,0]+P[1,2]+P[2,1])+0.114*P[1,1]
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Y[0,0]=(0x4d*P[0,0]+ 0x96*((P[-1,0]+P[0,-1]+P[0,1]+P[1,0])/4) + 0x1d*((P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1])/4))>>8
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Y[0,1]=(0x96*P[0,1]+ 0x4d*((P[0,0]+P[0,2])/2)+ 0x1d*((P[-1,1]+P[1,1])/2))>>8
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Y[1,0]=(0x96*P[1,0]+ 0x4d*((P[0,0]+P[2,0])/2)+ 0x1d*((P[1,-1]+P[1,1])/2))>>8
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Y[1,1]=(0x1d*P[1,1]+ 0x96*((P[0,1]+P[1,0]+P[1,2]+P[2,1])/4) + 0x4d*((P[0,0]+P[0,2]+P[2,0]+P[2,2])/4)))>>8
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Cb and Cy are needed 1 for each 4 pixels (4:2:0)
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(YC= 0.299*P[0,0]+0.587*(0.5*P[0,1]+P[1,0])+0.114*P[1,1] )
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Cb=0.564*(P[1,1]-(0.299*P[0,0]+0.587*0.5*(P[0,1]+P[1,0])+0.114*P[1,1]))+128
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Cr=0.713*(P[0,0]-(0.299*P[0,0]+0.587*0.5*(P[0,1]+P[1,0])+0.114*P[1,1]))+128
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Cb=0.564*(P[1,1]-(0.299*P[0,0]+0.587*0.5*(P[0,1]+P[1,0])+0.114*P[1,1]))+128=
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(-0x55*((P[0,1]+P[1,0])/2) -2b*P[0,0] +P[1,1]<<7)>>8+ 0x80=
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(-0x55*((P[0,1]+P[1,0])/2) -2b*P[0,0])>>8 +P[1,1]>>1 +0x80=
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Cr=0.713*(P[0,0]-(0.299*P[0,0]+0.587*0.5*(P[0,1]+P[1,0])+0.114*P[1,1]))+128=
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(-0x6b*((P[0,1]+P[1,0])/2) +P[0,0]<<7 -0x15*P[1,1])>>8 +0x80=
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(-0x6b*((P[0,1]+P[1,0])/2) -0x15*P[1,1])>>8 +P[0,0]>>1 +0x80=
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----
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*/
/*
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For Bayer array (BG/GR)(bayer_phase[1:0]==2), and pixels P[Y,X]:
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R[0,0]=0.25*(P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1])
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R[0,1]=0.5 *(P[-1,1] +P[1,1])
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R[1,0]=0.5* (P[1,-1]+P[1,1])
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R[1,1]= P[1,1]
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G[0,0]=0.25*(P[-1,0]+P[0,-1]+P[0,1]+P[1,0])
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G[0,1]= P[0,1]
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G[1,0]= P[1,0]
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G[1,1]=0.25*(P[0,1]+P[1,0]+P[1,2]+P[2,1])
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B[0,0]= P[0,0]
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B[0,1]=0.5* (P[0,0]+P[0,2])
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B[1,0]=0.5* (P[0,0]+P[2,0])
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B[1,1]=0.25*(P[0,0]+P[0,2]+P[2,0]+P[2,2])
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Y[0,0]=0.299*0.25*(P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1]) + 0.587*0.25*(P[-1,0]+P[0,-1]+P[0,1]+P[1,0]) + 0.114* P[0,0]
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Y[0,1]=0.299*0.5 *(P[-1,1] +P[1,1])+0.587*P[0,1]+0.114*0.5* (P[0,0]+P[0,2])
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Y[1,0]=0.299*0.5* (P[1,-1]+P[1,1])+0.587*P[1,0]+0.114*0.5* (P[0,0]+P[2,0])
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Y[1,1]=0.299*P[1,1]+0.587*0.25*(P[0,1]+P[1,0]+P[1,2]+P[2,1])+0.114*0.25*(P[0,0]+P[0,2]+P[2,0]+P[2,2])
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Y[0,0]=(0x1d*P[0,0]+ 0x96*((P[-1,0]+P[0,-1]+P[0,1]+P[1,0])/4)+ 0x4d*((P[-1,-1]+P[-1,1]+P[1,-1]+P[1,1])/4))>>8
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Y[0,1]=(0x96*P[0,1]+ 0x4d*((P[-1,1] +P[1,1])/2)+ 0x1d*((P[0,0]+P[0,2])/2))>>8
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Y[1,0]=(0x96*P[1,0]+ 0x4d*((P[1,-1]+P[1,1])/2)+ 0x1d*((P[0,0]+P[2,0])/2))>>8
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Y[1,1]=(0x4d*P[1,1]+ 0x96*((P[0,1]+P[1,0]+P[1,2]+P[2,1])/4) + 0x1d*((P[0,0]+P[0,2]+P[2,0]+P[2,2])/4)))>>8
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Cb and Cy are needed 1 for each 4 pixels (4:2:0)
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(YC= 0.299*P[1,1]+0.587*(0.5*P[1,0]+P[0,1])+0.114*P[0,0] )
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Cb=0.564*(P[0,0]-(0.299*P[1,1]+0.587*0.5*(P[1,0]+P[0,1])+0.114*P[0,0]))+128
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Cr=0.713*(P[1,1]-(0.299*P[1,1]+0.587*0.5*(P[1,0]+P[0,1])+0.114*P[0,0]))+128
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Cb=0.564*(P[0,0]-(0.299*P[1,1]+0.587*0.5*(P[1,0]+P[0,1])+0.114*P[0,0]))+128=
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(-0x55*((P[1,0]+P[0,1])/2) -2b*P[1,1] +P[0,0]<<7)>>8+ 0x80=
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(-0x55*((P[1,0]+P[0,1])/2) -2b*P[1,1])>>8 +P[0,0]>>1 +0x80=
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Cr=0.713*(P[1,1]-(0.299*P[1,1]+0.587*0.5*(P[1,0]+P[0,1])+0.114*P[0,0]))+128=
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(-0x6b*((P[1,0]+P[0,1])/2) +P[1,1]<<7 -0x15*P[0,0])>>8 +0x80=
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(-0x6b*((P[1,0]+P[0,1])/2) -0x15*P[0,0])>>8 +P[1,1]>>1 +0x80=
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----
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*/
/*
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For Bayer array (GB/RG)(bayer_phase[1:0]==3), and pixels P[Y,X]:
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R[0,0]=0.5 *(P[-1,0]+P[1,0])
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R[0,1]=0.25*(P[-1,0]+P[-1,2]+P[1,0]+P[1,2])
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R[1,0]= P[1,0]
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R[1,1]=0.5 *(P[1,0]+P[1,2])
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G[0,0]= P[0,0]
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G[0,1]=0.25*(P[-1,1]+P[0,0]+P[0,2]+P[1,1])
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G[1,0]=0.25*(P[0,0]+P[1,-1]+P[1,1]+P[2,0])
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G[1,1]= P[1,1]
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B[0,0]=0.5* (P[0,-1]+P[0,1])
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B[0,1]= P[0,1]
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B[1,0]=0.25*(P[0,-1]+P[0,1]+P[2,-1]+P[2,1])
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B[1,1]=0.5* (P[0,1]+P[2,1])
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Y[0,0]=0.299*0.5 *(P[-1,0]+P[1,0]) + 0.587*P[0,0] + 0.114*0.5* (P[0,-1]+P[0,1])
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Y[0,1]=0.299*0.25*(P[-1,0]+P[-1,2]+P[1,0]+P[1,2])+0.587*0.25*(P[-1,1]+P[0,0]+P[0,2]+P[1,1])+0.114*P[0,1]
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Y[1,0]=0.299*P[1,0]+0.587*0.25*(P[0,-1]+P[0,1]+P[2,-1]+P[2,1])+0.114*0.25*(P[0,-1]+P[0,1]+P[2,-1]+P[2,1])
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Y[1,1]=0.299*0.5 *(P[1,0]+P[1,2])+0.587*P[1,1]+0.114*0.5* (P[0,1]+P[2,1])
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Y[0,0]=(0x96*P[0,0]+ 0x4d*((P[-1,0]+P[1,0])/2) + 0x1d*((P[0,-1]+P[0,1])/2))>>8
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Y[0,1]=(0x1d*P[0,1]+ 0x96*((P[-1,1]+P[0,0]+P[0,2]+P[1,1])/4)+ 0x4d*((P[-1,0]+P[-1,2]+P[1,0]+P[1,2])/4))>>8
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Y[1,0]=(0x4d*P[1,0]+ 0x96*((P[0,0]+P[1,-1]+P[1,1]+P[2,0])/4)+ 0x1d*((P[0,-1]+P[0,1]+P[2,-1]+P[2,1])/4))>>8
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Y[1,1]=(0x96*P[1,1]+ 0x4d*((P[1,0]+P[1,2])/2 + 0x1d*((P[0,1] +P[2,1])/2)))>>8
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Cb and Cy are needed 1 for each 4 pixels (4:2:0)
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(YC= 0.299*P[1,0]+0.587*(0.5*P[1,1]+P[0,0])+0.114*P[0,1] )
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Cb=0.564*(P[0,1]-(0.299*P[1,0]+0.587*0.5*(P[1,1]+P[0,0])+0.114*P[0,1]))+128
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Cr=0.713*(P[1,0]-(0.299*P[1,0]+0.587*0.5*(P[1,1]+P[0,0])+0.114*P[0,1]))+128
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Cb=0.564*(P[0,1]-(0.299*P[1,0]+0.587*0.5*(P[1,1]+P[0,0])+0.114*P[0,1]))+128=
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(-0x55*((P[1,1]+P[0,0])/2) -2b*P[1,0] +P[0,1]<<7)>>8+ 0x80=
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(-0x55*((P[1,1]+P[0,0])/2) -2b*P[1,0])>>8 +P[0,1]>>1 +0x80=
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Cr=0.713*(P[1,0]-(0.299*P[1,0]+0.587*0.5*(P[1,1]+P[0,0])+0.114*P[0,1]))+128=
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(-0x6b*((P[1,1]+P[0,0])/2) +P[1,0]<<7 -0x15*P[0,1])>>8 +0x80=
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(-0x6b*((P[1,1]+P[0,0])/2) -0x15*P[0,1])>>8 +P[1,0]>>1 +0x80=
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----
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*/
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/* 02/24/2003 - modified to include bypass for monochrome mode**/
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/* 06/29/2004 - added counting of pixels with value of 0 and 255 (limited to 255 to use just 8 bits) **/
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//05.07.2008 - latency included here
239
module
csconvert18a
(
240
input
RST
,
241
input
CLK
,
242
input
mono
,
243
input
limit_diff
,
// 1 - limit color outputs to -128/+127 range, 0 - let them be limited downstream
244
input
[
9
:
0
]
m_cb
,
// [9:0] scale for CB - default 0.564 (10'h90)
245
input
[
9
:
0
]
m_cr
,
// [9:0] scale for CB - default 0.713 (10'hb6)
246
input
[
7
:
0
]
din
,
// input bayer data in scanline sequence, GR/BG sequence
247
input
pre_first_in
,
// marks the first input pixel
248
output
[
7
:
0
]
signed_y
,
// - now signed char, -128(black) to +127 (white)
249
output
[
8
:
0
]
q
,
// new, q is just signed char
250
output
[
7
:
0
]
yaddr
,
// address for the external buffer memory to write 16x16x8bit Y data
251
output
ywe
,
// wrire enable of Y data
252
output
[
6
:
0
]
caddr
,
// address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
253
output
cwe
,
// write enable for CbCr data
254
output
pre_first_out
,
255
input
[
1
:
0
]
bayer_phase
,
256
output
[
7
:
0
]
n000
,
257
output
[
7
:
0
]
n255
);
258
259
// Was: s ynthesis attribute shreg_extract of csconvert18a is yes;"
260
261
wire
ystrt
,
nxtline
;
262
reg
[
7
:
0
]
yaddr_r
;
// address for the external buffer memory to write 16x16x8bit Y data
263
reg
ywe_r
;
// write enable of Y data
264
reg
[
6
:
0
]
caddr_r
;
// address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
265
reg
cwe_r
;
// write enable for CbCr data
266
reg
odd_pix
;
// odd pixel (assumes even number of pixels in a line
267
reg
odd_line
;
// odd line
268
reg
pix_green
;
// (was "odd_pix==odd_line", now modified with bayer_phase[1:0]: bayer_phase[1]^bayer_phase[0]^(odd_pix==odd_line)
269
reg
y_eq_0
,
y_eq_255
;
270
reg
[
7
:
0
]
n000_r
;
271
reg
[
7
:
0
]
n255_r
;
272
wire
[
1
:
0
]
strt_dly
;
273
wire
strt
;
274
reg
[
7
:
0
]
signed_y_r
;
275
276
assign
pre_first_out
=
ystrt
;
277
278
assign
n000
=
n000_r
;
279
assign
n255
=
n255_r
;
280
assign
signed_y
=
signed_y_r
;
// - now signed char, -128(black) to +127 (white)
281
assign
yaddr
=
yaddr_r2
;
282
assign
ywe
=
ywe_r2
;
283
assign
caddr
=
caddr_r2
;
284
assign
cwe
=
cwe_r2
;
285
286
dly_16
#(.
WIDTH
(
1
))
i_strt_dly0
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd15
), .
din
(
pre_first_in
), .
dout
(
strt_dly
[
0
]));
287
dly_16
#(.
WIDTH
(
1
))
i_strt_dly1
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd15
), .
din
(
strt_dly
[
0
]), .
dout
(
strt_dly
[
1
]));
288
dly_16
#(.
WIDTH
(
1
))
i_strt
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd4
), .
din
(
strt_dly
[
1
]), .
dout
(
strt
));
289
290
// SRL16 i_strt_dly0 (.Q(strt_dly[0]), .D(pre_first_in), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
291
// SRL16 i_strt_dly1 (.Q(strt_dly[1]), .D(strt_dly[0]), .CLK(CLK), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); // dly=15+1
292
// SRL16 i_strt (.Q(strt), .D(strt_dly[1]), .CLK(CLK), .A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=4+1
293
dly_16
#(.
WIDTH
(
1
))
i_ystrt
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd5
), .
din
(
strt
), .
dout
(
ystrt
));
294
dly_16
#(.
WIDTH
(
1
))
i_nxtline
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd1
), .
din
(!
RST
&&
ywe_r
&& (
yaddr_r
[
3
:
0
]==
4'hf
) && (
yaddr_r
[
7
:
4
]!=
4'hf
)), .
dout
(
nxtline
));
295
296
// SRL16 i_ystrt (.Q(ystrt), .D(strt), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b1), .A3(1'b0)); // dly=5+1
297
// SRL16 i_nxtline(.Q(nxtline),.D(!RST && ywe_r && (yaddr_r[3:0]==4'hf) && (yaddr_r[7:4]!=4'hf)), .CLK(CLK), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0)); // dly=1+1
298
299
always
@ (
posedge
CLK
)
begin
300
ywe_r
<= !
RST
&& (
ystrt
||
nxtline
|| (
ywe_r
&& (
yaddr_r
[
3
:
0
]!=
4'hf
)));
301
yaddr_r
[
7
:
4
] <= (
RST
||
strt
)?
4'h0
: (
nxtline
?(
yaddr_r
[
7
:
4
]+
1
):
yaddr_r
[
7
:
4
]);
302
yaddr_r
[
3
:
0
] <=
ywe_r
? (
yaddr_r
[
3
:
0
]+
1
):
4'h0
;
303
odd_pix
<=
RST
||
strt
|| ~
odd_pix
;
304
if
(
RST
||
strt
)
odd_line
<=
1'b0
;
305
else
if
(
yaddr_r
[
3
:
0
]==
4'hd
)
odd_line
<= ~
odd_line
;
306
if
(
RST
||
strt
)
pix_green
<=
bayer_phase
[
1
]^
bayer_phase
[
0
];
307
else
pix_green
<=~(
yaddr_r
[
3
:
0
]==
4'hd
)^
pix_green
;
308
end
309
310
// First block generates 2 8-bit values (latency=3)- pixel (p2) and average value of previous and next pixel in the same
311
// row (pa). For the first pixel that "average" equals to next pixel, for the last - previous
312
reg
[
7
:
0
]
p0
;
313
reg
[
7
:
0
]
p1
;
314
reg
[
7
:
0
]
pd0
;
315
reg
[
7
:
0
]
pa0
;
316
wire
[
8
:
0
]
ppa
;
317
always
@ (
posedge
CLK
)
p0
<=
din
[
7
:
0
];
318
always
@ (
posedge
CLK
)
p1
<=
p0
[
7
:
0
];
319
// always @ (posedge CLK) pd0 <= p1[7:0];
320
always
@ (
posedge
RST
or
posedge
CLK
)
if
(
RST
)
pd0
<=
8'b0
;
else
pd0
<=
p1
[
7
:
0
];
// generates more effective than with 2-bit SRs (line above)
321
assign
ppa
[
8
:
0
]={
1'b0
,
pd0
}+{
1'b0
,
p0
};
322
always
@ (
posedge
CLK
)
pa0
<=
ppa
[
8
:
1
];
//loosing 1 bit here!
323
// next - 2 pairs of 8 bit wide 16-bit long serial-in, serial out shift registers. Verify implementation - Should use 32 LUTs
324
// update 06/10/2004 - make an output pd_c[7:0] 2 cycles after pd_1[7:0] for color processing without additional resources
325
reg
[
17
:
0
]
pd_10
,
pd_11
,
pd_12
,
pd_13
,
pd_14
,
pd_15
,
pd_16
,
pd_17
;
326
// reg [17:0] pd_20,pd_21,pd_22,pd_23,pd_24,pd_25,pd_26,pd_27;
327
reg
[
7
:
0
]
pd1_dly
;
328
reg
[
7
:
0
]
pdc
;
329
reg
[
15
:
0
]
pd_20
,
pd_21
,
pd_22
,
pd_23
,
pd_24
,
pd_25
,
pd_26
,
pd_27
;
330
reg
[
17
:
0
]
pa_10
,
pa_11
,
pa_12
,
pa_13
,
pa_14
,
pa_15
,
pa_16
,
pa_17
;
331
reg
[
17
:
0
]
pa_20
,
pa_21
,
pa_22
,
pa_23
,
pa_24
,
pa_25
,
pa_26
,
pa_27
;
332
333
wire
[
7
:
0
]
pd1
;
334
wire
[
7
:
0
]
pd2
;
335
wire
[
7
:
0
]
pa1
;
336
wire
[
7
:
0
]
pa2
;
337
338
assign
pd1
={
pd_17
[
17
],
pd_16
[
17
],
pd_15
[
17
],
pd_14
[
17
],
pd_13
[
17
],
pd_12
[
17
],
pd_11
[
17
],
pd_10
[
17
]};
339
assign
pd2
={
pd_27
[
15
],
pd_26
[
15
],
pd_25
[
15
],
pd_24
[
15
],
pd_23
[
15
],
pd_22
[
15
],
pd_21
[
15
],
pd_20
[
15
]};
340
assign
pa1
={
pa_17
[
17
],
pa_16
[
17
],
pa_15
[
17
],
pa_14
[
17
],
pa_13
[
17
],
pa_12
[
17
],
pa_11
[
17
],
pa_10
[
17
]};
341
assign
pa2
={
pa_27
[
17
],
pa_26
[
17
],
pa_25
[
17
],
pa_24
[
17
],
pa_23
[
17
],
pa_22
[
17
],
pa_21
[
17
],
pa_20
[
17
]};
342
343
344
always
@ (
posedge
CLK
)
pd_10
<= {
pd_10
[
16
:
0
],
pd0
[
0
]};
345
always
@ (
posedge
CLK
)
pd_11
<= {
pd_11
[
16
:
0
],
pd0
[
1
]};
346
always
@ (
posedge
CLK
)
pd_12
<= {
pd_12
[
16
:
0
],
pd0
[
2
]};
347
always
@ (
posedge
CLK
)
pd_13
<= {
pd_13
[
16
:
0
],
pd0
[
3
]};
348
always
@ (
posedge
CLK
)
pd_14
<= {
pd_14
[
16
:
0
],
pd0
[
4
]};
349
always
@ (
posedge
CLK
)
pd_15
<= {
pd_15
[
16
:
0
],
pd0
[
5
]};
350
always
@ (
posedge
CLK
)
pd_16
<= {
pd_16
[
16
:
0
],
pd0
[
6
]};
351
always
@ (
posedge
CLK
)
pd_17
<= {
pd_17
[
16
:
0
],
pd0
[
7
]};
352
353
always
@ (
posedge
CLK
)
pd1_dly
[
7
:
0
] <=
pd1
[
7
:
0
];
354
always
@ (
posedge
CLK
)
pdc
[
7
:
0
] <=
pd1_dly
[
7
:
0
];
355
always
@ (
posedge
CLK
)
pd_20
<= {
pd_20
[
14
:
0
],
pdc
[
0
]};
356
always
@ (
posedge
CLK
)
pd_21
<= {
pd_21
[
14
:
0
],
pdc
[
1
]};
357
always
@ (
posedge
CLK
)
pd_22
<= {
pd_22
[
14
:
0
],
pdc
[
2
]};
358
always
@ (
posedge
CLK
)
pd_23
<= {
pd_23
[
14
:
0
],
pdc
[
3
]};
359
always
@ (
posedge
CLK
)
pd_24
<= {
pd_24
[
14
:
0
],
pdc
[
4
]};
360
always
@ (
posedge
CLK
)
pd_25
<= {
pd_25
[
14
:
0
],
pdc
[
5
]};
361
always
@ (
posedge
CLK
)
pd_26
<= {
pd_26
[
14
:
0
],
pdc
[
6
]};
362
always
@ (
posedge
CLK
)
pd_27
<= {
pd_27
[
14
:
0
],
pdc
[
7
]};
363
364
always
@ (
posedge
CLK
)
pa_10
<= {
pa_10
[
16
:
0
],
pa0
[
0
]};
365
always
@ (
posedge
CLK
)
pa_11
<= {
pa_11
[
16
:
0
],
pa0
[
1
]};
366
always
@ (
posedge
CLK
)
pa_12
<= {
pa_12
[
16
:
0
],
pa0
[
2
]};
367
always
@ (
posedge
CLK
)
pa_13
<= {
pa_13
[
16
:
0
],
pa0
[
3
]};
368
always
@ (
posedge
CLK
)
pa_14
<= {
pa_14
[
16
:
0
],
pa0
[
4
]};
369
always
@ (
posedge
CLK
)
pa_15
<= {
pa_15
[
16
:
0
],
pa0
[
5
]};
370
always
@ (
posedge
CLK
)
pa_16
<= {
pa_16
[
16
:
0
],
pa0
[
6
]};
371
always
@ (
posedge
CLK
)
pa_17
<= {
pa_17
[
16
:
0
],
pa0
[
7
]};
372
373
always
@ (
posedge
CLK
)
pa_20
<= {
pa_20
[
16
:
0
],
pa_10
[
17
]};
374
always
@ (
posedge
CLK
)
pa_21
<= {
pa_21
[
16
:
0
],
pa_11
[
17
]};
375
always
@ (
posedge
CLK
)
pa_22
<= {
pa_22
[
16
:
0
],
pa_12
[
17
]};
376
always
@ (
posedge
CLK
)
pa_23
<= {
pa_23
[
16
:
0
],
pa_13
[
17
]};
377
always
@ (
posedge
CLK
)
pa_24
<= {
pa_24
[
16
:
0
],
pa_14
[
17
]};
378
always
@ (
posedge
CLK
)
pa_25
<= {
pa_25
[
16
:
0
],
pa_15
[
17
]};
379
always
@ (
posedge
CLK
)
pa_26
<= {
pa_26
[
16
:
0
],
pa_16
[
17
]};
380
always
@ (
posedge
CLK
)
pa_27
<= {
pa_27
[
16
:
0
],
pa_17
[
17
]};
381
382
383
wire
[
7
:
0
]
pd_prev
=
pd2
[
7
:
0
];
384
wire
[
7
:
0
]
pd_next
=
pd0
[
7
:
0
];
385
wire
[
7
:
0
]
pa_prev
=
pa2
[
7
:
0
];
386
wire
[
7
:
0
]
pa_next
=
pa0
[
7
:
0
];
387
388
// now the result Y calculation depends on the pixel position (bx,by). It consists of 3 terms, each with different coefficient.
389
// first term always includes pd1[7:0]
390
// if (bx[1]==by[1]) // 00 or 11
391
// second term is pa1, third - (pd0+pd2)/2
392
// else
393
// second term is (pa1 + (pd0+pd2)/2)/2, third - (pa0+pa2)/2
394
// reg [7:0] m1; same as pd1_dly
395
reg
[
7
:
0
]
m2
;
396
reg
[
7
:
0
]
m3
;
397
wire
[
8
:
0
]
pd02s
= {
1'b0
,
pd_prev
[
7
:
0
]}+{
1'b0
,
pd_next
[
7
:
0
]};
// will use pd02s[8:1]
398
wire
[
8
:
0
]
pa1pd02s
={
1'b0
,
pa1
[
7
:
0
]}+{
1'b0
,
pd02s
[
8
:
1
]};
// will use pa1pd02s[8:1]
399
wire
[
8
:
0
]
pa02s
= {
1'b0
,
pa_prev
[
7
:
0
]}+{
1'b0
,
pa_next
[
7
:
0
]};
// will use pa02s[8:1]
400
// always @ (posedge CLK) m1 <= pd1[7:0]; // same as pd1_dly
401
// always @ (posedge CLK) m2 <= (odd_pix==odd_line)? pa1[7:0] : pa1pd02s[8:1];
402
// always @ (posedge CLK) m3 <= (odd_pix==odd_line)? pd02s[8:1] : pa02s[8:1];
403
always
@ (
posedge
CLK
)
m2
<=
pix_green
?
pa1
[
7
:
0
] :
pa1pd02s
[
8
:
1
];
404
always
@ (
posedge
CLK
)
m3
<=
pix_green
?
pd02s
[
8
:
1
] :
pa02s
[
8
:
1
];
405
/*
406
Y[0,0]=(0x96*P[0,0]+ 0x4d*((P[0,-1]+P[0,1])/2) + 0x1d*((P[-1,0]+P[1,0])/2))>>8
407
Y[0,1]=(0x4d*P[0,1]+ 0x96*((P[-1,1]+P[0,0]+P[0,2]+P[1,1])/4)+ 0x1d*((P[-1,0]+P[-1,2]+P[1,0]+P[1,2])/4))>>8
408
Y[1,0]=(0x1d*P[1,0]+ 0x96*((P[0,0]+P[1,-1]+P[1,1]+P[2,0])/4)+ 0x4d*((P[0,-1]+P[0,1]+P[2,-1]+P[2,1])/4))>>8
409
Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2 + 0x4d*((P[0,1] +P[2,1])/2)))>>8
410
+-----+--------+-------+-------+-------+-------+-------+
411
| | (0) | | | * | * | * * |
412
| | G R | * | * + * | + | * + * | + |
413
| | B G | | | * | * | * * |
414
+-----+--------+-------+-------+-------+-------+-------+
415
| 0 | P[0,0] | 0x96 | 0x4d | 0x1d | | |
416
| +--------+-------+-------+-------+-------+-------+
417
| G R | P[0,1] | 0x4d | | | 0x96 | 0x1d |
418
| +--------+-------+-------+-------+-------+-------+
419
| B G | P[1,0] | 0x1d | | | 0x96 | 0x4d |
420
| +--------+-------+-------+-------+-------+-------+
421
| | P[1,1] | 0x96 | 0x1d | 0x4d | | |
422
+-----+--------+-------+-------+-------+-------+-------+
423
| 1 | P[0,0] | 0x4d | | | 0x96 | 0x1d |
424
| +--------+-------+-------+-------+-------+-------+
425
| R G | P[0,1] | 0x96 | 0x4d | 0x1d | | |
426
| +--------+-------+-------+-------+-------+-------+
427
| G B | P[1,0] | 0x96 | 0x1d | 0x4d | | |
428
| +--------+-------+-------+-------+-------+-------+
429
| | P[1,1] | 0x1d | | | 0x96 | 0x4d |
430
+-----+--------+-------+-------+-------+-------+-------+
431
| 2 | P[0,0] | 0x1d | | | 0x96 | 0x4d |
432
| +--------+-------+-------+-------+-------+-------+
433
| B G | P[0,1] | 0x96 | 0x1d | 0x4d | | |
434
| +--------+-------+-------+-------+-------+-------+
435
| G R | P[1,0] | 0x96 | 0x4d | 0x1d | | |
436
| +--------+-------+-------+-------+-------+-------+
437
| | P[1,1] | 0x4d | | | 0x96 | 0x1d |
438
+-----+--------+-------+-------+-------+-------+-------+
439
| 3 | P[0,0] | 0x96 | 0x1d | 0x4d | | |
440
| +--------+-------+-------+-------+-------+-------+
441
| G B | P[0,1] | 0x1d | | | 0x96 | 0x4d |
442
| +--------+-------+-------+-------+-------+-------+
443
| R G | P[1,0] | 0x4d | | | 0x96 | 0x1d |
444
| +--------+-------+-------+-------+-------+-------+
445
| | P[1,1] | 0x96 | 0x4d | 0x1d | | |
446
+-----+--------+-------+-------+-------+-------+-------+
447
448
449
*/
450
reg
[
7
:
0
]
k1
;
451
reg
[
7
:
0
]
k2
;
452
reg
[
7
:
0
]
k3
;
453
always
@ (
posedge
CLK
)
case
({
bayer_phase
[
1
:
0
],
odd_line
,
odd_pix
})
454
// 0 - GR/BG
455
4'b0000
:
begin
456
k1
<=
8'h96
;
457
k2
<=
8'h4d
;
458
k3
<=
8'h1d
;
459
end
460
4'b0001
:
begin
461
k1
<=
8'h4d
;
462
k2
<=
8'h96
;
463
k3
<=
8'h1d
;
464
end
465
4'b0010
:
begin
466
k1
<=
8'h1d
;
467
k2
<=
8'h96
;
468
k3
<=
8'h4d
;
469
end
470
4'b0011
:
begin
471
k1
<=
8'h96
;
472
k2
<=
8'h1d
;
473
k3
<=
8'h4d
;
474
end
475
// 1 - RG/GB
476
4'b0100
:
begin
477
k1
<=
8'h4d
;
478
k2
<=
8'h96
;
479
k3
<=
8'h1d
;
480
end
481
4'b0101
:
begin
482
k1
<=
8'h96
;
483
k2
<=
8'h4d
;
484
k3
<=
8'h1d
;
485
end
486
4'b0110
:
begin
487
k1
<=
8'h96
;
488
k2
<=
8'h1d
;
489
k3
<=
8'h4d
;
490
end
491
4'b0111
:
begin
492
k1
<=
8'h1d
;
493
k2
<=
8'h96
;
494
k3
<=
8'h4d
;
495
end
496
// 2 - BG/GR
497
4'b1000
:
begin
498
k1
<=
8'h1d
;
499
k2
<=
8'h96
;
500
k3
<=
8'h4d
;
501
end
502
4'b1001
:
begin
503
k1
<=
8'h96
;
504
k2
<=
8'h1d
;
505
k3
<=
8'h4d
;
506
end
507
4'b1010
:
begin
508
k1
<=
8'h96
;
509
k2
<=
8'h4d
;
510
k3
<=
8'h1d
;
511
end
512
4'b1011
:
begin
513
k1
<=
8'h4d
;
514
k2
<=
8'h96
;
515
k3
<=
8'h1d
;
516
end
517
// 3 - GB/RG
518
4'b1100
:
begin
519
k1
<=
8'h96
;
520
k2
<=
8'h1d
;
521
k3
<=
8'h4d
;
522
end
523
4'b1101
:
begin
524
k1
<=
8'h1d
;
525
k2
<=
8'h96
;
526
k3
<=
8'h4d
;
527
end
528
4'b1110
:
begin
529
k1
<=
8'h4d
;
530
k2
<=
8'h96
;
531
k3
<=
8'h1d
;
532
end
533
4'b1111
:
begin
534
k1
<=
8'h96
;
535
k2
<=
8'h4d
;
536
k3
<=
8'h1d
;
537
end
538
endcase
539
540
wire
[
15
:
0
]
mm1
=
pd1_dly
[
7
:
0
] *
k1
[
7
:
0
];
//m1[7:0]*k1[7:0];
541
wire
[
15
:
0
]
mm2
=
m2
[
7
:
0
]*
k2
[
7
:
0
];
542
wire
[
15
:
0
]
mm3
=
m3
[
7
:
0
]*
k3
[
7
:
0
];
543
544
reg
[
7
:
0
]
y
;
545
// reg [7:0] y0; // bypass in monochrome mode
546
// wire [7:0] y0 = pdc;
547
reg
[
7
:
0
]
y0_r
;
548
// wire [7:0] y0; // bypass in monochrome mode
549
reg
[
15
:
0
]
y1
,
y2
,
y3
;
550
551
// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs).
552
// TODO: reduce width of y1,y2,y3 and correctly round
553
// wire [15:0] y_sum =y1+y2+y3;
554
reg
[
15
:
0
]
y_sum_r
;
555
// always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
556
// wire [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
557
wire
[
7
:
0
]
pre_y
=
mono
?
y0_r
: (
y_sum_r
[
15
:
8
]+
y_sum_r
[
7
]);
558
// making y output signed -128..+127
559
560
always
@ (
posedge
CLK
)
begin
561
y1
<=
mm1
;
562
y2
<=
mm2
;
563
y3
<=
mm3
;
564
y0_r
<=
pdc
;
565
y_sum_r
<=
y1
+
y2
+
y3
;
566
y
[
7
:
0
] <=
pre_y
[
7
:
0
];
567
signed_y_r
[
7
:
0
] <= {~
pre_y
[
7
],
pre_y
[
6
:
0
]};
568
end
569
570
571
// Try easier and hope better algorithm of color extractions that should perform better on gradients.
572
// It will rely on the fact that Y is already calculated, so instead of processing 4 pixels it will
573
// calculate Cb for "B" pixel, and Cr - for "R", subtracting calculated "Y" for that pixel.
574
//Cb = 0.564*(B-Y)+128
575
//Cr = 0.713*(R-Y)+128
576
// First - delay pd1[7:0] by 2 clock periods - to match "Y" output (one ahead, actually)
577
// It is better to implement it earlier - while calculating pd2 - anyway it had to be delayed by 18 (16+2) form pd1 - make it in 2 stages 2 +16
578
// pdc[7:0] - one cycle ahead of the "Y" for each pixel
579
// Try multiplication by constant without the register for that constant, just 2:1 mux. Still use aregister for the other operand (is it needed?)
580
reg
[
7
:
0
]
cbcrmult1
;
581
//wire [7:0] cbcrmult2; // 1 of 2 constants - should be valid during ywe_r and 1 more cycle ("use_cr"
582
wire
[
9
:
0
]
cbcrmult2
;
// 1 of 2 constants - should be valid during ywe_r and 1 more cycle ("use_cr"
583
//wire [15:0] cbcrmulto; // output of 8x8 multiplier
584
wire
[
17
:
0
]
cbcrmulto
;
// output of 8x8 multiplier
585
586
// ignoring overflow we do not need extra bits
587
// high saturation can cause overflow, but we have very limited resources in model 313 to port back to
588
//reg [8:0] cbcrmultr; // 1 extra bit for precision (before subtraction)
589
reg
[
10
:
0
]
cbcrmultr
;
// 1 extra bit for precision (before subtraction)
590
//reg [8:0] cbcr; // after subraction (with extra bit preserved)
591
reg
[
10
:
0
]
cbcr
;
// after subraction (with extra bit preserved)
592
reg
sel_cbcrmult1
;
// 0 - use pdc[7:0], 1 - use y[7:0]. Should be valid 1 cycle ahead of ywe_r!
593
reg
use_cr
;
// in this line cr is calculated. Valid during ywe_r and 1 cycle after
594
reg
sub_y
;
// output accumulator/subtractor. 0 - load new data, 1 - subtract. Walid 2 cycles after ywe_r
595
wire
cwe0
;
// preliminary cwe_r (to be modulated by odd/even pixels)
596
reg
cstrt
;
//ystrt dealyed by 1
597
reg
cnxt
;
// nxtline delayed by 1
598
reg
pre_sel_cbcrmult1
;
599
// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output
600
601
always
@ (
posedge
CLK
)
begin
602
// if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
603
// else sel_cbcrmult1 <= ~sel_cbcrmult1;
604
if
(~(
ywe_r
||
ystrt
||
nxtline
))
pre_sel_cbcrmult1
<= ~(
bayer_phase
[
1
] ^
bayer_phase
[
0
] ^
odd_line
);
605
else
pre_sel_cbcrmult1
<= ~
pre_sel_cbcrmult1
;
606
607
sel_cbcrmult1
<=
pre_sel_cbcrmult1
;
608
609
sub_y
<= ~
sel_cbcrmult1
;
610
// cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
611
cbcrmult1
<=
sel_cbcrmult1
?
y
[
7
:
0
]:
y0_r
[
7
:
0
];
// delayed by 1 clock
612
613
if
(~
ywe_r
)
use_cr
<= ~(
bayer_phase
[
1
] ^
odd_line
);
614
end
615
assign
cbcrmult2
=
use_cr
?
m_cr
:
m_cb
;
// maybe will need a register? (use_cr will still be good as it is valid early)
616
//assign cbcrmulto = cbcrmult1*cbcrmult2;
617
assign
cbcrmulto
=
cbcrmult1
*
cbcrmult2_r
;
618
reg
[
9
:
0
]
cbcrmult2_r
;
// will be one cycle later than cbcrmult2, but is still OK. Will be absorbed into the DSP block
619
// will preserve extra bit, but do not need to add half of the truncated MSB - on average there will be no shift after subtraction
620
always
@ (
posedge
CLK
)
begin
621
cbcrmult2_r
<=
cbcrmult2
;
622
cbcrmultr
[
10
:
0
] <=
cbcrmulto
[
17
:
7
];
623
cbcr
[
10
:
0
] <=
sub_y
? (
cbcr
[
10
:
0
]-
cbcrmultr
[
10
:
0
]+
1'b1
):
cbcrmultr
[
10
:
0
];
624
end
625
//limit_diff
626
// Here 0 is shifted to 0x80
627
// new, q is signed char
628
assign
q
[
8
:
0
]= ((
cbcr
[
10
]==
cbcr
[
9
]) && (!
limit_diff
|| (
cbcr
[
10
]==
cbcr
[
8
])))?
cbcr
[
9
:
1
]: {
cbcr
[
10
],
limit_diff
?
cbcr
[
10
]:(~
cbcr
[
10
]),{
7
{~
cbcr
[
10
]}}};
629
630
dly_16
#(.
WIDTH
(
1
))
i_cwe0
(.
clk
(
CLK
),.
rst
(
1'b0
), .
dly
(
4'd1
), .
din
(
ywe_r
), .
dout
(
cwe0
));
631
//SRL16 i_cwe0 (.D(ywe_r ), .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
632
633
634
635
always
@ (
posedge
CLK
)
begin
636
cstrt
<=
ystrt
;
637
cnxt
<=
nxtline
;
638
// cwe_r <= cwe0 && sub_y;
639
cwe_r
<=
cwe0
&& !
sel_cbcrmult1
;
640
caddr_r
[
2
:
0
]<=
cwe0
?(
caddr_r
[
2
:
0
]+
cwe_r
):
3'b0
;
641
if
(
cstrt
)
caddr_r
[
6
] <= ~
bayer_phase
[
1
];
642
else
if
(
cnxt
)
caddr_r
[
6
] <= ~
caddr_r
[
6
];
643
if
(
cstrt
)
caddr_r
[
5
:
3
] <=
3'b0
;
644
else
if
(
cnxt
)
caddr_r
[
5
:
3
] <=(
bayer_phase
[
1
]^
caddr_r
[
6
])?
caddr_r
[
5
:
3
]:(
caddr_r
[
5
:
3
]+
1
);
645
end
646
// extra signals delayed by 1 clock
647
reg
ywe_r2
,
cwe_r2
;
648
reg
[
6
:
0
]
caddr_r2
;
649
reg
[
7
:
0
]
yaddr_r2
;
650
always
@ (
posedge
CLK
)
begin
651
ywe_r2
<=
ywe_r
;
652
cwe_r2
<=
cwe_r
;
653
yaddr_r2
<=
yaddr_r
;
654
caddr_r2
<=
caddr_r
;
655
end
656
657
658
always
@ (
posedge
CLK
)
begin
659
y_eq_0
<= (
y0_r
[
7
:
0
] ==
8'h0
);
660
y_eq_255
<= (
y0_r
[
7
:
0
] ==
8'hff
);
661
if
(
strt
)
n000_r
[
7
:
0
] <=
8'h0
;
662
else
if
((
n000_r
[
7
:
0
]!=
8'hff
) &&
y_eq_0
&&
ywe_r2
)
n000_r
[
7
:
0
] <=
n000_r
[
7
:
0
]+
1
;
663
if
(
strt
)
n255_r
[
7
:
0
] <=
8'h0
;
664
else
if
((
n255_r
[
7
:
0
]!=
8'hff
) &&
y_eq_255
&&
ywe_r2
)
n255_r
[
7
:
0
] <=
n255_r
[
7
:
0
]+
1
;
665
end
666
667
668
endmodule
669
csconvert18a.2120nxtline
2120nxtlinewire
Definition:
csconvert18a.v:261
csconvert18a.dly_16
i_cwe0 dly_16
Definition:
csconvert18a.v:630
csconvert18a.2111yaddr
[ 7:0] 2111yaddr
Definition:
csconvert18a.v:250
csconvert18a.2207sub_y
2207sub_yreg
Definition:
csconvert18a.v:594
csconvert18a.2143pd_13
2143pd_13reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2144pd_14
2144pd_14reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2133strt
2133strtwire
Definition:
csconvert18a.v:273
dly_16.10332clk
10332clk
Definition:
dly_16.v:44
csconvert18a.2122ywe_r
2122ywe_rreg
Definition:
csconvert18a.v:263
csconvert18a.2170pa_24
2170pa_24reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2152pd_22
2152pd_22reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2159pa_11
2159pa_11reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2167pa_21
2167pa_21reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2186pa02s
2186pa02swire[8:0]
Definition:
csconvert18a.v:399
csconvert18a.2214cwe_r2
2214cwe_r2reg
Definition:
csconvert18a.v:647
csconvert18a.2172pa_26
2172pa_26reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2181pa_next
2181pa_nextwire[7:0]
Definition:
csconvert18a.v:386
csconvert18a.2142pd_12
2142pd_12reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2160pa_12
2160pa_12reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2185pa1pd02s
2185pa1pd02swire[8:0]
Definition:
csconvert18a.v:398
csconvert18a.2125odd_pix
2125odd_pixreg
Definition:
csconvert18a.v:266
csconvert18a.2200cbcrmult1
2200cbcrmult1reg[7:0]
Definition:
csconvert18a.v:580
csconvert18a.2131n255_r
2131n255_rreg[7:0]
Definition:
csconvert18a.v:271
csconvert18a.2203cbcrmultr
2203cbcrmultrreg[10:0]
Definition:
csconvert18a.v:589
csconvert18a.2150pd_20
2150pd_20reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2208cwe0
2208cwe0wire
Definition:
csconvert18a.v:595
csconvert18a.2157pd_27
2157pd_27reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2188k2
2188k2reg[7:0]
Definition:
csconvert18a.v:451
csconvert18a.2147pd_17
2147pd_17reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2161pa_13
2161pa_13reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2176pa1
2176pa1wire[7:0]
Definition:
csconvert18a.v:335
csconvert18a.2177pa2
2177pa2wire[7:0]
Definition:
csconvert18a.v:336
csconvert18a.2168pa_22
2168pa_22reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2132strt_dly
2132strt_dlywire[1:0]
Definition:
csconvert18a.v:272
csconvert18a.2189k3
2189k3reg[7:0]
Definition:
csconvert18a.v:452
csconvert18a.2191mm2
2191mm2wire[15:0]
Definition:
csconvert18a.v:541
csconvert18a.2190mm1
2190mm1wire[15:0]
Definition:
csconvert18a.v:540
csconvert18a.2113caddr
[ 6:0] 2113caddr
Definition:
csconvert18a.v:252
csconvert18a.2166pa_20
2166pa_20reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2108pre_first_in
2108pre_first_in
Definition:
csconvert18a.v:247
csconvert18a.2107din
[ 7:0] 2107din
Definition:
csconvert18a.v:246
csconvert18a
Definition:
csconvert18a.v:239
csconvert18a.2210cnxt
2210cnxtreg
Definition:
csconvert18a.v:597
csconvert18a.2179pd_next
2179pd_nextwire[7:0]
Definition:
csconvert18a.v:384
csconvert18a.2209cstrt
2209cstrtreg
Definition:
csconvert18a.v:596
csconvert18a.2118n255
[ 7:0] 2118n255
Definition:
csconvert18a.v:257
csconvert18a.2110q
[ 8:0] 2110q
Definition:
csconvert18a.v:249
csconvert18a.2204cbcr
2204cbcrreg[10:0]
Definition:
csconvert18a.v:591
dly_16.10336dout
[WIDTH-1:0] 10336dout
Definition:
dly_16.v:48
csconvert18a.2135p0
2135p0reg[7:0]
Definition:
csconvert18a.v:312
csconvert18a.2146pd_16
2146pd_16reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2187k1
2187k1reg[7:0]
Definition:
csconvert18a.v:450
csconvert18a.2162pa_14
2162pa_14reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2202cbcrmulto
2202cbcrmultowire[17:0]
Definition:
csconvert18a.v:584
csconvert18a.2139ppa
2139ppawire[8:0]
Definition:
csconvert18a.v:316
csconvert18a.2148pd1_dly
2148pd1_dlyreg[7:0]
Definition:
csconvert18a.v:327
csconvert18a.2141pd_11
2141pd_11reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2194y0_r
2194y0_rreg[7:0]
Definition:
csconvert18a.v:547
csconvert18a.2126odd_line
2126odd_linereg
Definition:
csconvert18a.v:267
csconvert18a.2128y_eq_0
2128y_eq_0reg
Definition:
csconvert18a.v:269
csconvert18a.2136p1
2136p1reg[7:0]
Definition:
csconvert18a.v:313
csconvert18a.2196y2
2196y2reg[15:0]
Definition:
csconvert18a.v:549
csconvert18a.2140pd_10
2140pd_10reg[17:0]
Definition:
csconvert18a.v:325
csconvert18a.2197y3
2197y3reg[15:0]
Definition:
csconvert18a.v:549
csconvert18a.2115pre_first_out
2115pre_first_out
Definition:
csconvert18a.v:254
dly_16.10335din
[WIDTH-1:0] 10335din
Definition:
dly_16.v:47
csconvert18a.2174pd1
2174pd1wire[7:0]
Definition:
csconvert18a.v:333
csconvert18a.2169pa_23
2169pa_23reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2138pa0
2138pa0reg[7:0]
Definition:
csconvert18a.v:315
csconvert18a.2127pix_green
2127pix_greenreg
Definition:
csconvert18a.v:268
csconvert18a.2206use_cr
2206use_crreg
Definition:
csconvert18a.v:593
csconvert18a.2130n000_r
2130n000_rreg[7:0]
Definition:
csconvert18a.v:270
csconvert18a.2165pa_17
2165pa_17reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2201cbcrmult2
2201cbcrmult2wire[9:0]
Definition:
csconvert18a.v:582
csconvert18a.2163pa_15
2163pa_15reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2178pd_prev
2178pd_prevwire[7:0]
Definition:
csconvert18a.v:383
csconvert18a.2104limit_diff
2104limit_diff
Definition:
csconvert18a.v:243
csconvert18a.2183m3
2183m3reg[7:0]
Definition:
csconvert18a.v:396
csconvert18a.2155pd_25
2155pd_25reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2123caddr_r
2123caddr_rreg[6:0]
Definition:
csconvert18a.v:264
csconvert18a.2134signed_y_r
2134signed_y_rreg[7:0]
Definition:
csconvert18a.v:274
csconvert18a.2102CLK
2102CLK
Definition:
csconvert18a.v:241
csconvert18a.2192mm3
2192mm3wire[15:0]
Definition:
csconvert18a.v:542
csconvert18a.2154pd_24
2154pd_24reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2198y_sum_r
2198y_sum_rreg[15:0]
Definition:
csconvert18a.v:554
csconvert18a.2151pd_21
2151pd_21reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2156pd_26
2156pd_26reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2109signed_y
[ 7:0] 2109signed_y
Definition:
csconvert18a.v:248
csconvert18a.2119ystrt
2119ystrtwire
Definition:
csconvert18a.v:261
csconvert18a.2103mono
2103mono
Definition:
csconvert18a.v:242
csconvert18a.2213ywe_r2
2213ywe_r2reg
Definition:
csconvert18a.v:647
csconvert18a.2212cbcrmult2_r
2212cbcrmult2_rreg[9:0]
Definition:
csconvert18a.v:618
csconvert18a.2211pre_sel_cbcrmult1
2211pre_sel_cbcrmult1reg
Definition:
csconvert18a.v:598
csconvert18a.2117n000
[ 7:0] 2117n000
Definition:
csconvert18a.v:256
csconvert18a.2116bayer_phase
[ 1:0] 2116bayer_phase
Definition:
csconvert18a.v:255
csconvert18a.2101RST
2101RST
Definition:
csconvert18a.v:240
csconvert18a.2106m_cr
[ 9:0] 2106m_cr
Definition:
csconvert18a.v:245
csconvert18a.2137pd0
2137pd0reg[7:0]
Definition:
csconvert18a.v:314
csconvert18a.2175pd2
2175pd2wire[7:0]
Definition:
csconvert18a.v:334
csconvert18a.2182m2
2182m2reg[7:0]
Definition:
csconvert18a.v:395
csconvert18a.2171pa_25
2171pa_25reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2216yaddr_r2
2216yaddr_r2reg[7:0]
Definition:
csconvert18a.v:649
csconvert18a.2180pa_prev
2180pa_prevwire[7:0]
Definition:
csconvert18a.v:385
csconvert18a.2149pdc
2149pdcreg[7:0]
Definition:
csconvert18a.v:328
csconvert18a.2158pa_10
2158pa_10reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2153pd_23
2153pd_23reg[15:0]
Definition:
csconvert18a.v:329
csconvert18a.2129y_eq_255
2129y_eq_255reg
Definition:
csconvert18a.v:269
csconvert18a.2164pa_16
2164pa_16reg[17:0]
Definition:
csconvert18a.v:330
csconvert18a.2199pre_y
2199pre_ywire[7:0]
Definition:
csconvert18a.v:557
csconvert18a.2114cwe
2114cwe
Definition:
csconvert18a.v:253
csconvert18a.2195y1
2195y1reg[15:0]
Definition:
csconvert18a.v:549
csconvert18a.2124cwe_r
2124cwe_rreg
Definition:
csconvert18a.v:265
csconvert18a.2173pa_27
2173pa_27reg[17:0]
Definition:
csconvert18a.v:331
csconvert18a.2215caddr_r2
2215caddr_r2reg[6:0]
Definition:
csconvert18a.v:648
csconvert18a.2145pd_15
2145pd_15reg[17:0]
Definition:
csconvert18a.v:325
dly_16.10333rst
10333rst
Definition:
dly_16.v:45
csconvert18a.2193y
2193yreg[7:0]
Definition:
csconvert18a.v:544
csconvert18a.2105m_cb
[ 9:0] 2105m_cb
Definition:
csconvert18a.v:244
csconvert18a.2205sel_cbcrmult1
2205sel_cbcrmult1reg
Definition:
csconvert18a.v:592
csconvert18a.2121yaddr_r
2121yaddr_rreg[7:0]
Definition:
csconvert18a.v:262
csconvert18a.2112ywe
2112ywe
Definition:
csconvert18a.v:251
csconvert18a.2184pd02s
2184pd02swire[8:0]
Definition:
csconvert18a.v:397
dly_16.10334dly
[3:0] 10334dly
Definition:
dly_16.v:46
compressor_jp
csconvert18a.v
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