841
701afi_safe_rd_pendingreg
cmd_deser_32bit_i cmd_deser
693safe_some_left_rd_wwire
[WRITE_WIDTH - 1 : 0] 10318wr_data
chn1rd_buf_i mcntrl_buf_rd
682afi_wa_safe_not_fullreg
reset_page_rd_i pulse_cross_clock
703write_pages_readyreg[2:0]
650advance_rel_addr_rdwire
675axi_rd_receivedreg[7:0]
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
669axi_arw_requestedreg[7:0]
618rdwr_reset_addr_mclkreg
624last_in_line64reg[FRAME_WIDTH_BITS:0]
debug_slave_i debug_slave
[READ_WIDTH - 1 : 0] 10317rd_data
649advance_rel_addr_wrwire
674axi_rd_pendingwire[7:0]
686bufwr_wereg[BUFWR_WE_WIDTH-1:0]
700afi_ra_safe_not_fullreg
[DATA_WIDTH-1:0] 9934data
680read_pages_readyreg[2:0]
616width64_minus1_mclkreg[FRAME_WIDTH_BITS:0]
709dbg_write_counterreg[15:0]
513MEMBRIDGE_STATUS_CNTRL'h1
[FRAME_HEIGHT_BITS-1:0] 538line_unfinished_chn1
660buf_in_line64reg[FRAME_WIDTH_BITS:0]
615width64_mclkreg[FRAME_WIDTH_BITS:0]
514MEMBRIDGE_LO_ADDR64'h2
[ADDR_WIDTH-1:0] 9933addr
670axi_bursts_requestedreg[7:0]
706dbg_read_counterreg[30:0]
699afi_rd_safe_not_emptyreg
[1 << LOG2WIDTH_WR-1:0] 5202ext_data_in
[1 << LOG2WIDTH_RD-1:0] 5188ext_data_out
elastic_cross_clock_i elastic_cross_clock
648advance_rel_addr_wwire
705buf_in_line64_rreg[6:0]
520MEMBRIDGE_STATUS_REG'h3b
chn1wr_buf_i mcntrl_buf_wr
672axi_wr_pendingwire[7:0]
status_generate_i status_generate
681afi_wd_safe_not_fullreg
[ALL_BITS-1:0] 10777status
652advance_rel_addr_dreg[DELAY_ADVANCE_ADDR-1:0]
[14-LOG2WIDTH_RD:0] 5185ext_raddr
[14-LOG2WIDTH_WR:0] 5200ext_waddr
611lo_addr64_mclkreg[28:0]