51 // input emul64, // emulate 64 pixel wide reads with actual 32-wide columns 52 // in the future - use rd64/wr64 for JP4 mode 53 input wclk,
// !mclk (inverted) 54 input [
1:
0]
wpage_in,
// will register to wclk, input OK with mclk 55 input wpage_set,
// set internal write page to wpage_in 56 input page_next,
// advance to next page (and reset lower bits to 0) 57 output [
1:
0]
page,
// current inernal page 58 input we,
// write port enable (also increment write buffer address) 64 // wire [4:0] next62_norm = waddr[6:2] + 1; 65 // wire [4:0] next62_rot = {waddr[2],waddr[6:3]} + 1; 66 // wire [4:0] next62_emul64 = {next62_rot[3:0],next62_rot[4]}; 67 always @ (
posedge wclk)
begin 75 // if (page_next || wpage_set) waddr[1:0] <= 0; 76 // else if (we) waddr[1:0] <= waddr[1:0] + 1; 78 // if (page_next || wpage_set) waddr[6:2] <= 0; 79 // else if (we && (&waddr[1:0])) waddr[6:2] <= emul64 ? next62_emul64 : next62_norm; 82 // ram_512x64w_1kx32r #( 87 )
ram_512x64w_1kx32r_i (
93 .
wclk (
wclk),
// input - OK, negedge mclk 95 .
we (
we),
// input @negedge mclk 96 .
web (
8'hff),
// input[7:0] [1 << LOG2WIDTH_WR-1:0] 11872data_in
[14-LOG2WIDTH_WR:0] 11869waddr
[1 << LOG2WIDTH_RD-1:0] 11867data_out
[14-LOG2WIDTH_RD:0] 11864raddr
[1 << LOG2WIDTH_RD-1:0] 5188ext_data_out
integer 5183LOG2WIDTH_RD5
[14-LOG2WIDTH_RD:0] 5185ext_raddr
ram_512x64w_1kx32r_i ram_var_w_var_r