phy_top Member List

This is the complete list of members for phy_top, including all inherited members.

reset	dci_reset	Input
ready	dci_reset	Output
IODELAY_GRP	idelay_ctrl	Parameter
refclk	idelay_ctrl	Input
rst	idelay_ctrl	Input
rdy	idelay_ctrl	Output
PHASE_WIDTH	mmcm_phase_cntr	Parameter
CLKIN_PERIOD	mmcm_phase_cntr	Parameter
BANDWIDTH	mmcm_phase_cntr	Parameter
CLKFBOUT_MULT_F	mmcm_phase_cntr	Parameter
CLKFBOUT_PHASE	mmcm_phase_cntr	Parameter
CLKOUT0_PHASE	mmcm_phase_cntr	Parameter
CLKOUT1_PHASE	mmcm_phase_cntr	Parameter
CLKOUT2_PHASE	mmcm_phase_cntr	Parameter
CLKOUT3_PHASE	mmcm_phase_cntr	Parameter
CLKOUT4_PHASE	mmcm_phase_cntr	Parameter
CLKOUT5_PHASE	mmcm_phase_cntr	Parameter
CLKOUT6_PHASE	mmcm_phase_cntr	Parameter
CLKOUT0_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT1_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT2_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT3_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT4_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT5_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT6_DUTY_CYCLE	mmcm_phase_cntr	Parameter
CLKOUT4_CASCADE	mmcm_phase_cntr	Parameter
CLKFBOUT_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT0_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT1_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT2_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT3_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT4_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT5_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT6_USE_FINE_PS	mmcm_phase_cntr	Parameter
CLKOUT0_DIVIDE_F	mmcm_phase_cntr	Parameter
CLKOUT1_DIVIDE	mmcm_phase_cntr	Parameter
CLKOUT2_DIVIDE	mmcm_phase_cntr	Parameter
CLKOUT3_DIVIDE	mmcm_phase_cntr	Parameter
CLKOUT4_DIVIDE	mmcm_phase_cntr	Parameter
CLKOUT5_DIVIDE	mmcm_phase_cntr	Parameter
CLKOUT6_DIVIDE	mmcm_phase_cntr	Parameter
COMPENSATION	mmcm_phase_cntr	Parameter
DIVCLK_DIVIDE	mmcm_phase_cntr	Parameter
REF_JITTER1	mmcm_phase_cntr	Parameter
REF_JITTER2	mmcm_phase_cntr	Parameter
SS_EN	mmcm_phase_cntr	Parameter
SS_MODE	mmcm_phase_cntr	Parameter
SS_MOD_PERIOD	mmcm_phase_cntr	Parameter
STARTUP_WAIT	mmcm_phase_cntr	Parameter
clkin1	mmcm_phase_cntr	Input
clkin2	mmcm_phase_cntr	Input
sel_clk2	mmcm_phase_cntr	Input
clkfbin	mmcm_phase_cntr	Input
rst	mmcm_phase_cntr	Input
pwrdwn	mmcm_phase_cntr	Input
psclk	mmcm_phase_cntr	Input
ps_we	mmcm_phase_cntr	Input
ps_din	mmcm_phase_cntr	Input
ps_ready	mmcm_phase_cntr	Output
ps_dout	mmcm_phase_cntr	Output
clkout0	mmcm_phase_cntr	Output
clkout1	mmcm_phase_cntr	Output
clkout2	mmcm_phase_cntr	Output
clkout3	mmcm_phase_cntr	Output
clkout4	mmcm_phase_cntr	Output
clkout5	mmcm_phase_cntr	Output
clkout6	mmcm_phase_cntr	Output
clkout0b	mmcm_phase_cntr	Output
clkout1b	mmcm_phase_cntr	Output
clkout2b	mmcm_phase_cntr	Output
clkout3b	mmcm_phase_cntr	Output
clkfbout	mmcm_phase_cntr	Output
clkfboutb	mmcm_phase_cntr	Output
locked	mmcm_phase_cntr	Output
clkin_stopped	mmcm_phase_cntr	Output
clkfb_stopped	mmcm_phase_cntr	Output
ps_dout_r	mmcm_phase_cntr	Signal
psen	mmcm_phase_cntr	Signal
psincdec	mmcm_phase_cntr	Signal
psdone	mmcm_phase_cntr	Signal
ps_target	mmcm_phase_cntr	Signal
ps_busy	mmcm_phase_cntr	Signal
ps_start0	mmcm_phase_cntr	Signal
ps_start	mmcm_phase_cntr	Signal
diff	mmcm_phase_cntr	Signal
reset_extended	mmcm_phase_cntr	Signal
CAPACITANCE	obuf	Parameter
DRIVE	obuf	Parameter
IOSTANDARD	obuf	Parameter
SLEW	obuf	Parameter
O	obuf	Output
I	obuf	Input
CAPACITANCE	oddr_ds	Parameter
IOSTANDARD	oddr_ds	Parameter
SLEW	oddr_ds	Parameter
DDR_CLK_EDGE	oddr_ds	Parameter
INIT	oddr_ds	Parameter
SRTYPE	oddr_ds	Parameter
clk	oddr_ds	Input
ce	oddr_ds	Input
rst	oddr_ds	Input
set	oddr_ds	Input
din	oddr_ds	Input
tin	oddr_ds	Input
dq	oddr_ds	Output
ndq	oddr_ds	Output
idq	oddr_ds	Signal
byte_lane.IODELAY_GRP	odelay_fine_pipe	Parameter
byte_lane.dqs_single.IODELAY_GRP	odelay_fine_pipe	Parameter
byte_lane.DELAY_VALUE	odelay_fine_pipe	Parameter
byte_lane.dqs_single.DELAY_VALUE	odelay_fine_pipe	Parameter
byte_lane.REFCLK_FREQUENCY	odelay_fine_pipe	Parameter
byte_lane.dqs_single.REFCLK_FREQUENCY	odelay_fine_pipe	Parameter
byte_lane.HIGH_PERFORMANCE_MODE	odelay_fine_pipe	Parameter
byte_lane.dqs_single.HIGH_PERFORMANCE_MODE	odelay_fine_pipe	Parameter
byte_lane.clk	odelay_fine_pipe	Input
byte_lane.dqs_single.clk	odelay_fine_pipe	Input
byte_lane.rst	odelay_fine_pipe	Input
byte_lane.dqs_single.rst	odelay_fine_pipe	Input
byte_lane.set	odelay_fine_pipe	Input
byte_lane.dqs_single.set	odelay_fine_pipe	Input
byte_lane.ld	odelay_fine_pipe	Input
byte_lane.dqs_single.ld	odelay_fine_pipe	Input
byte_lane.delay	odelay_fine_pipe	Input
byte_lane.dqs_single.delay	odelay_fine_pipe	Input
byte_lane.data_in	odelay_fine_pipe	Input
byte_lane.dqs_single.data_in	odelay_fine_pipe	Input
byte_lane.data_out	odelay_fine_pipe	Output
byte_lane.dqs_single.data_out	odelay_fine_pipe	Output
byte_lane.fdly_pre	odelay_fine_pipe	Signal
byte_lane.dqs_single.fdly_pre	odelay_fine_pipe	Signal
byte_lane.fdly	odelay_fine_pipe	Signal
byte_lane.dqs_single.fdly	odelay_fine_pipe	Signal
byte_lane.MODE_DDR	oserdes_mem	Parameter
byte_lane.dqs_single.MODE_DDR	oserdes_mem	Parameter
byte_lane.clk	oserdes_mem	Input
byte_lane.dqs_single.clk	oserdes_mem	Input
byte_lane.clk_div	oserdes_mem	Input
byte_lane.dqs_single.clk_div	oserdes_mem	Input
byte_lane.rst	oserdes_mem	Input
byte_lane.dqs_single.rst	oserdes_mem	Input
byte_lane.din	oserdes_mem	Input
byte_lane.dqs_single.din	oserdes_mem	Input
byte_lane.tin	oserdes_mem	Input
byte_lane.dqs_single.tin	oserdes_mem	Input
byte_lane.dout_dly	oserdes_mem	Output
byte_lane.dqs_single.dout_dly	oserdes_mem	Output
byte_lane.dout_iob	oserdes_mem	Output
byte_lane.dqs_single.dout_iob	oserdes_mem	Output
byte_lane.tout_dly	oserdes_mem	Output
byte_lane.dqs_single.tout_dly	oserdes_mem	Output
byte_lane.tout_iob	oserdes_mem	Output
byte_lane.dqs_single.tout_iob	oserdes_mem	Output
byte_lane.DATA_RATE	oserdes_mem	Parameter
byte_lane.dqs_single.DATA_RATE	oserdes_mem	Parameter
byte_lane.DATA_WIDTH	oserdes_mem	Parameter
byte_lane.dqs_single.DATA_WIDTH	oserdes_mem	Parameter
byte_lane.DATA_WIDTH_TRI	oserdes_mem	Parameter
byte_lane.dqs_single.DATA_WIDTH_TRI	oserdes_mem	Parameter
IODELAY_GRP	byte_lane	Parameter
IBUF_LOW_PWR	byte_lane	Parameter
IOSTANDARD_DQ	byte_lane	Parameter
IOSTANDARD_DM	byte_lane	Parameter
IOSTANDARD_DQS	byte_lane	Parameter
SLEW_DQ	byte_lane	Parameter
SLEW_DQS	byte_lane	Parameter
REFCLK_FREQUENCY	byte_lane	Parameter
HIGH_PERFORMANCE_MODE	byte_lane	Parameter
dq	byte_lane	Inout
dm	byte_lane	Output
dqs	byte_lane	Inout
ndqs	byte_lane	Inout
clk	byte_lane	Input
clk_div	byte_lane	Input
inv_clk_div	byte_lane	Input
rst	byte_lane	Input
dci_disable_dqs	byte_lane	Input
dci_disable_dq	byte_lane	Input
din	byte_lane	Input
din_dm	byte_lane	Input
tin_dq	byte_lane	Input
din_dqs	byte_lane	Input
tin_dqs	byte_lane	Input
dout	byte_lane	Output
dly_data	byte_lane	Input
dly_addr	byte_lane	Input
ld_delay	byte_lane	Input
set	byte_lane	Input
dqs_read	byte_lane	Signal
iclk	byte_lane	Signal
din_r	byte_lane	Signal
din_dm_r	byte_lane	Signal
din_dqs_r	byte_lane	Signal
tin_dq_r	byte_lane	Signal
tin_dqs_r	byte_lane	Signal
dly_data_r	byte_lane	Signal
set_r	byte_lane	Signal
dci_disable_dqs_r	byte_lane	Signal
dci_disable_dq_r	byte_lane	Signal
ld_odly	byte_lane	Signal
ld_idly	byte_lane	Signal
ld_odly_dqs	byte_lane	Signal
ld_idly_dqs	byte_lane	Signal
ld_odly_dm	byte_lane	Signal
decode_sel	byte_lane	Signal
IODELAY_GRP	cmd_addr	Parameter
IOSTANDARD	cmd_addr	Parameter
SLEW	cmd_addr	Parameter
REFCLK_FREQUENCY	cmd_addr	Parameter
HIGH_PERFORMANCE_MODE	cmd_addr	Parameter
ADDRESS_NUMBER	cmd_addr	Parameter
ddr3_a	cmd_addr	Output
ddr3_ba	cmd_addr	Output
ddr3_we	cmd_addr	Output
ddr3_ras	cmd_addr	Output
ddr3_cas	cmd_addr	Output
ddr3_cke	cmd_addr	Output
ddr3_odt	cmd_addr	Output
clk	cmd_addr	Input
clk_div	cmd_addr	Input
rst	cmd_addr	Input
in_a	cmd_addr	Input
in_ba	cmd_addr	Input
in_we	cmd_addr	Input
in_ras	cmd_addr	Input
in_cas	cmd_addr	Input
in_cke	cmd_addr	Input
in_odt	cmd_addr	Input
in_tri	cmd_addr	Input
dly_data	cmd_addr	Input
dly_addr	cmd_addr	Input
ld_delay	cmd_addr	Input
set	cmd_addr	Input
in_a_r	cmd_addr	Signal
in_ba_r	cmd_addr	Signal
in_we_r	cmd_addr	Signal
in_ras_r	cmd_addr	Signal
in_cas_r	cmd_addr	Signal
in_cke_r	cmd_addr	Signal
in_odt_r	cmd_addr	Signal
in_tri_r	cmd_addr	Signal
dly_data_r	cmd_addr	Signal
set_r	cmd_addr	Signal
ld_dly_cmd	cmd_addr	Signal
ld_dly_addr	cmd_addr	Signal
decode_addr24	cmd_addr	Signal
decode_sel	cmd_addr	Signal
IOSTANDARD_DQ	phy_top
IOSTANDARD_DM	phy_top
IOSTANDARD_DQS	phy_top
IOSTANDARD_CMDA	phy_top
IOSTANDARD_CLK	phy_top
SLEW_DQ	phy_top
SLEW_DQS	phy_top
SLEW_CMDA	phy_top
SLEW_CLK	phy_top
IBUF_LOW_PWR	phy_top
IODELAY_GRP	phy_top
REFCLK_FREQUENCY	phy_top
HIGH_PERFORMANCE_MODE	phy_top
ADDRESS_NUMBER	phy_top
PHASE_WIDTH	phy_top
BANDWIDTH	phy_top
CLKIN_PERIOD	phy_top
CLKFBOUT_MULT	phy_top
DIVCLK_DIVIDE	phy_top
CLKFBOUT_USE_FINE_PS	phy_top
CLKFBOUT_PHASE	phy_top
SDCLK_PHASE	phy_top
CLK_PHASE	phy_top
CLK_DIV_PHASE	phy_top
MCLK_PHASE	phy_top
REF_JITTER1	phy_top
SS_EN	phy_top
SS_MODE	phy_top
SS_MOD_PERIOD	phy_top
ddr3_nrst	phy_top
ddr3_clk	phy_top
ddr3_nclk	phy_top
ddr3_a	phy_top
ddr3_ba	phy_top
ddr3_we	phy_top
ddr3_ras	phy_top
ddr3_cas	phy_top
ddr3_cke	phy_top
ddr3_odt	phy_top
dq	phy_top
dml	phy_top
dqsl	phy_top
ndqsl	phy_top
dmu	phy_top
dqsu	phy_top
ndqsu	phy_top
clk_in	phy_top
clk	phy_top
clk_div	phy_top
mclk	phy_top
mrst	phy_top
ref_clk	phy_top
idelay_ctrl_reset	phy_top
rst_in	phy_top
ddr_rst	phy_top
dci_rst	phy_top
dly_rst	phy_top
in_a	phy_top
in_ba	phy_top
in_we	phy_top
in_ras	phy_top
in_cas	phy_top
in_cke	phy_top
in_odt	phy_top
in_tri	phy_top
din	phy_top
din_dm	phy_top
tin_dq	phy_top
din_dqs	phy_top
tin_dqs	phy_top
dout	phy_top
inv_clk_div	phy_top
dci_disable_dqs	phy_top
dci_disable_dq	phy_top
dly_data	phy_top
dly_addr	phy_top
ld_delay	phy_top
set	phy_top
locked_mmcm	phy_top
locked_pll	phy_top
dly_ready	phy_top
dci_ready	phy_top
tmp_debug	phy_top
ps_rdy	phy_top
ps_out	phy_top
rst	phy_top
ld_data_l	phy_top
ld_data_h	phy_top
ld_cmda	phy_top
ld_mmcm	phy_top
clkin_stopped_mmcm	phy_top
clkfb_stopped_mmcm	phy_top
dbg1	phy_top
dbg2	phy_top
sdclk	phy_top
clk_pre	phy_top
clk_div_pre	phy_top
sdclk_pre	phy_top
mclk_pre	phy_top
clk_fb	phy_top
ALWAYS_314 clk_div	byte_lane	Always Construct
ALWAYS_315 clk_div	cmd_addr	Always Construct
ALWAYS_328 clk_div	phy_top	Always Construct
ALWAYS_329 mclk	phy_top	Always Construct
ALWAYS_330 clk_div	phy_top	Always Construct
ALWAYS_552 psclk	mmcm_phase_cntr	Always Construct
ALWAYS_553 psclk	mmcm_phase_cntr	Always Construct
byte_lane.ALWAYS_554 clk	odelay_fine_pipe	Always Construct
byte_lane.dqs_single.ALWAYS_554 clk	odelay_fine_pipe	Always Construct
BUFG	phy_top
BUFIO	phy_top
BUFR	phy_top
BUFR	phy_top
byte_lane	phy_top
byte_lane	phy_top
cmd_addr	phy_top
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
cmda_single	cmd_addr	Module Instance
dci_reset	phy_top
DCIRESET	dci_reset	Module Instance
dm_single	byte_lane	Module Instance
dq_single	byte_lane	Module Instance
dqs_single	byte_lane	Module Instance
GENERATE [129]	cmd_addr	GENERATE
GENERATE [148]	byte_lane	GENERATE
idelay_ctrl	phy_top
IDELAYCTRL	idelay_ctrl	Module Instance
mmcm_phase_cntr	phy_top
MMCME2_ADV	mmcm_phase_cntr	Module Instance
obuf	phy_top
OBUF	obuf	Module Instance
OBUFTDS	oddr_ds	Module Instance
ODDR	oddr_ds	Module Instance
oddr_ds	phy_top
byte_lane.odelay_fine_pipe	dq_single	Module Instance
byte_lane.dm_single.odelay_fine_pipe	dm_single	Module Instance
byte_lane.dqs_single.odelay_fine_pipe	dqs_single	Module Instance
byte_lane.ODELAYE2_FINEDELAY	odelay_fine_pipe	Module Instance
byte_lane.dqs_single.ODELAYE2_FINEDELAY	odelay_fine_pipe	Module Instance
byte_lane.oserdes_mem	dq_single	Module Instance
byte_lane.dm_single.oserdes_mem	dm_single	Module Instance
byte_lane.dqs_single.oserdes_mem	dqs_single	Module Instance
byte_lane.OSERDESE2	oserdes_mem	Module Instance
byte_lane.dqs_single.OSERDESE2	oserdes_mem	Module Instance