dq_single Module Reference

Inheritance diagram for dq_single:

Collaboration diagram for dq_single:

Public Attributes

Inputs
iclk
clk
clk_div
inv_clk_div
rst
dci_disable
dly_data	[ 7 : 0 ]
din	[ 3 : 0 ]
tin	[ 3 : 0 ]
set_odelay
ld_odelay
set_idelay
ld_idelay

Inouts
dq

Outputs
dout	[ 3 : 0 ]

Parameters
IODELAY_GRP	"IODELAY_MEMORY"
IDELAY_VALUE	integer 0
ODELAY_VALUE	integer 0
IBUF_LOW_PWR	"TRUE"
IOSTANDARD	"SSTL15_T_DCI"
SLEW	"SLOW"
REFCLK_FREQUENCY	real 300 . 0
HIGH_PERFORMANCE_MODE	"FALSE"

Signals
wire	d_ser
wire	dq_tri
wire	dq_data_dly
wire	dq_dly
wire	dq_di

Module Instances
oserdes_mem::oserdes_i	Module oserdes_mem
odelay_fine_pipe::dq_out_dly_i	Module odelay_fine_pipe
IOBUF_DCIEN::iobufs_dq_i	Module IOBUF_DCIEN
idelay_fine_pipe::dq_in_dly_i	Module idelay_fine_pipe
iserdes_mem::iserdes_mem_i	Module iserdes_mem

Detailed Description

Definition at line 41 of file dq_single.v.

Member Data Documentation

IODELAY_GRP "IODELAY_MEMORY"

Parameter

Definition at line 42 of file dq_single.v.

IDELAY_VALUE 0

Parameter

Definition at line 43 of file dq_single.v.

ODELAY_VALUE 0

Parameter

Definition at line 44 of file dq_single.v.

IBUF_LOW_PWR "TRUE"

Parameter

Definition at line 45 of file dq_single.v.

IOSTANDARD "SSTL15_T_DCI"

Parameter

Definition at line 46 of file dq_single.v.

SLEW "SLOW"

Parameter

Definition at line 47 of file dq_single.v.

REFCLK_FREQUENCY 300 . 0

Parameter

Definition at line 48 of file dq_single.v.

HIGH_PERFORMANCE_MODE "FALSE"

Parameter

Definition at line 49 of file dq_single.v.

dq

Inout

Definition at line 51 of file dq_single.v.

iclk

Input

Definition at line 52 of file dq_single.v.

clk

Input

Definition at line 53 of file dq_single.v.

clk_div

Input

Definition at line 54 of file dq_single.v.

inv_clk_div

Input

Definition at line 55 of file dq_single.v.

rst

Input

Definition at line 56 of file dq_single.v.

dci_disable

Input

Definition at line 57 of file dq_single.v.

dly_data [ 7 : 0 ]

Input

Definition at line 58 of file dq_single.v.

din [ 3 : 0 ]

Input

Definition at line 59 of file dq_single.v.

tin [ 3 : 0 ]

Input

Definition at line 60 of file dq_single.v.

dout [ 3 : 0 ]

Output

Definition at line 61 of file dq_single.v.

set_odelay

Input

Definition at line 62 of file dq_single.v.

ld_odelay

Input

Definition at line 63 of file dq_single.v.

set_idelay

Input

Definition at line 64 of file dq_single.v.

ld_idelay

Input

Definition at line 65 of file dq_single.v.

d_ser

Signal

Definition at line 67 of file dq_single.v.

dq_tri

Signal

Definition at line 68 of file dq_single.v.

dq_data_dly

Signal

Definition at line 69 of file dq_single.v.

dq_dly

Signal

Definition at line 70 of file dq_single.v.

dq_di

Signal

Definition at line 72 of file dq_single.v.

idelay_fine_pipe dq_in_dly_i

Module Instance

Definition at line 116 of file dq_single.v.

IOBUF_DCIEN iobufs_dq_i

Module Instance

Definition at line 103 of file dq_single.v.

iserdes_mem iserdes_mem_i

Module Instance

Definition at line 131 of file dq_single.v.

odelay_fine_pipe dq_out_dly_i

Module Instance

Definition at line 88 of file dq_single.v.

oserdes_mem oserdes_i

Module Instance

Definition at line 75 of file dq_single.v.

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The documentation for this Module was generated from the following files:

• memctrl/phy/dq_single.v