255
3302transpose_dinwire[TRANSPOSE_WIDTH-1:0]
[2*WIDTH -1:0] 3227dout_10_32_76_54
3311stage2_pre2_en_outwire
3301stage1_pre2_start_outwire
3299dct1in_pad_lwire[DSP_WIDTH-1:0]
3308dct2in_pad_lwire[DSP_WIDTH-1:0]
[2*WIDTH -1:0] 3318dout_10_32_76_54
[2 * WIDTH -1:0] 3138d10_32_76_54
signed [OUTPUT_WIDTH-1:0] 3283d_out
3303transpose_douthwire[TRANSPOSE_WIDTH-1:0]
[OUT_WIDTH -1:0] 3140dout
3304transpose_doutlwire[TRANSPOSE_WIDTH-1:0]
3305transpose_start_outwire
3310stage2_pre2_start_outwire
dct_chen_transpose_i dct_chen_transpose
3295dct1in_lwire[INPUT_WIDTH-1:0]
3288ROUND_STAGE1DSP_WIDTH - TRANSPOSE_WIDTH - TRIM_STAGE_1
3312dbg_stage1_pre2_en_outwire
signed [INPUT_WIDTH-1:0] 3279xin
3294dct1in_hwire[INPUT_WIDTH-1:0]
dct1d_chen_stage2_i dct1d_chen
3290xin_rreg[INPUT_WIDTH-1:0]
3309dct2_outwire[OUTPUT_WIDTH-1:0]
3289ROUND_STAGE2DSP_WIDTH - OUTPUT_WIDTH - TRIM_STAGE_2
3307dct2in_pad_hwire[DSP_WIDTH-1:0]
3284REPLICATE_IN_STAGE1STAGE1_SAFE_BITS
3285PAD_IN_STAGE1DSP_WIDTH - INPUT_WIDTH - STAGE1_SAFE_BITS
dct1d_chen_reorder_out_i dct1d_chen_reorder_out
dct1d_chen_reorder_in_i dct1d_chen_reorder_in
3286REPLICATE_IN_STAGE2STAGE2_SAFE_BITS
3300dct1_outwire[TRANSPOSE_WIDTH-1:0]
3287PAD_IN_STAGE2DSP_WIDTH - TRANSPOSE_WIDTH - STAGE2_SAFE_BITS
3298dct1in_pad_hwire[DSP_WIDTH-1:0]