46 input [
WIDTH -
1:
0]
din,
// pre2_start-X-F4-X-F2-X-F6-F5-F0-F3-X-F1-X-F7 47 input pre2_start,
// Two cycles ahead of F4. Next one should start either at exactly 64 cycles, or >=68 cycles from the previous one 48 output [
2*
WIDTH -
1:
0]
dout_10_32_76_54,
// Concatenated/reordered output data {x[1],x[0]}/{x[3],x[2]}/ {x[7],x[6]}/{x[5],x[4]} 50 output reg en_out // to be sampled when start_out is expected 52 reg [
6:
0]
wcntr;
// write counter, used to calculate write address (2 pages of 64 words), that will be valid next cycle 57 reg wcol13;
// columns 1 and 3 (special) 58 wire [
3:
0]
wrow_mod;
// effective row, including modifier for wpage 65 reg [
5:
0]
rcntr =
6'h3f;
// read counter 66 reg [
5:
0]
raddr;
// read counter, addresses dual words 78 // TODO: prevent writing to previous page after pause! 79 always @(
posedge clk)
begin 94 else if (
pre_we_r)
wcntr <=
wcntr +
1;
// including page, should be before 'if (pre2_start)' 95 else if (
pre2_start)
wcntr <= {
wcntr[
6],
6'b0};
// if happens during pre_we_r - will be ignored, otherwise (after pause) will zero in-page adderss 132 .
dly (
4'h3),
// input[3:0] 139 min latency == 60, // adding 1 for read after write in RAM 140 max latency = 83 (when using a 2-page buffer) 141 wseq=(0x08, 0x62, 0x04, 0x6e, 0x0c, 0x0a, 0x00, 0x06, 142 0x09, 0x02, 0x05, 0x0e, 0x0d, 0x0b, 0x01, 0x07, 143 0x18, 0x03, 0x14, 0x0f, 0x1c, 0x1a, 0x10, 0x16, 144 0x19, 0x12, 0x15, 0x1e, 0x1d, 0x1b, 0x11, 0x17, 145 0x39, 0x13, 0x35, 0x1f, 0x3d, 0x3b, 0x31, 0x37, 146 0x38, 0x33, 0x34, 0x3f, 0x3c, 0x3a, 0x30, 0x36, 147 0x29, 0x32, 0x25, 0x3e, 0x2d, 0x2b, 0x21, 0x27, 148 0x28, 0x23, 0x24, 0x2f, 0x2c, 0x2a, 0x20, 0x26) 149 rseq = (0x00,0x10,0x20,0x30,-1,-1,-1,-1, 150 0x02,0x12,0x22,0x32,-1,-1,-1,-1, 151 0x04,0x14,0x24,0x34,-1,-1,-1,-1, 152 0x06,0x16,0x26,0x36,-1,-1,-1,-1, 153 0x08,0x18,0x28,0x38,-1,-1,-1,-1, 154 0x0a,0x1a,0x2a,0x3a,-1,-1,-1,-1, 155 0x0c,0x1c,0x2c,0x3c,-1,-1,-1,-1, 156 0x0e,0x1e,0x2e,0x3e,-1,-1,-1,-1)
[2*WIDTH -1:0] 3318dout_10_32_76_54
3337ram_regreg[2*WIDTH-1:0]
3338ram_reg2reg[2*WIDTH-1:0]
[0:127] 3330transpose_ramreg[WIDTH-1:0]