x393  1.0
FPGAcodeforElphelNC393camera
ahci_top.v
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1 
26 `timescale 1ns/1ps
27 
28 module ahci_top#(
29  parameter PREFETCH_ALWAYS = 0,
30  parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
31 // parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
32  parameter READ_CT_LATENCY = 2, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
33  parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
34  parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
35  parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
36  parameter FREQ_METER_WIDTH = 12
37 
38 )(
39  input aclk, // clock - should be buffered
40  input arst, // @aclk sync reset, active high
41  input mclk, // SATA system clock (current 75MHz for SATA2)
42  input mrst, // reset in mclk clock domain (after SATA PLL is on)
43  // async reset for SATA (mrst will be response to it)
44  output hba_arst, // hba async reset (currently does ~ the same as port reset)
45  output port_arst, // port0 async set by software (does not include arst)
46  output port_arst_any, // port0 async set by software and by arst
47  input hclk, // AXI HP interface clock for 64-bit DMA (current - 150MHz
48  input hrst, // reset in hclk clock domain
49 // MAXIGP1
50 // AXI Write Address
51  input [31:0] awaddr, // AWADDR[31:0], input
52  input awvalid, // AWVALID, input
53  output awready, // AWREADY, output
54  input [11:0] awid, // AWID[11:0], input
55  input [ 3:0] awlen, // AWLEN[3:0], input
56  input [ 1:0] awsize, // AWSIZE[1:0], input
57  input [ 1:0] awburst, // AWBURST[1:0], input
58 // AXI PS Master GP0: Write Data
59  input [31:0] wdata, // WDATA[31:0], input
60  input wvalid, // WVALID, input
61  output wready, // WREADY, output
62  input [11:0] wid, // WID[11:0], input
63  input wlast, // WLAST, input
64  input [ 3:0] wstb, // WSTRB[3:0], input
65 // AXI PS Master GP0: Write response
66  output bvalid, // BVALID, output
67  input bready, // BREADY, input
68  output [11:0] bid, // BID[11:0], output
69  output [ 1:0] bresp, // BRESP[1:0], output
70 // AXI Read Address
71  input [31:0] araddr, // ARADDR[31:0], input
72  input arvalid, // ARVALID, input
73  output arready, // ARREADY, output
74  input [11:0] arid, // ARID[11:0], input
75  input [ 3:0] arlen, // ARLEN[3:0], input
76  input [ 1:0] arsize, // ARSIZE[1:0], input
77  input [ 1:0] arburst, // ARBURST[1:0], input
78 // AXI Read Data
79  output [31:0] rdata, // RDATA[31:0], output
80  output rvalid, // RVALID, output
81  input rready, // RREADY, input
82  output [11:0] rid, // RID[11:0], output
83  output rlast, // RLAST, output
84  output [ 1:0] rresp, // RRESP
85 // SAXIHP3
86  // axi_hp signals write channel
87  // write address
88  output [31:0] afi_awaddr,
89  output afi_awvalid,
90  input afi_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
91  output [ 5:0] afi_awid,
92  output [ 1:0] afi_awlock,
93  output [ 3:0] afi_awcache,
94  output [ 2:0] afi_awprot,
95  output [ 3:0] afi_awlen,
96  output [ 1:0] afi_awsize,
97  output [ 1:0] afi_awburst,
98  output [ 3:0] afi_awqos,
99  // write data
100  output [63:0] afi_wdata,
101  output afi_wvalid,
102  input afi_wready, // @ SuppressThisWarning VEditor unused - used FIF0 level
103  output [ 5:0] afi_wid,
104  output afi_wlast,
105  output [ 7:0] afi_wstrb,
106  // write response
107  input afi_bvalid, // @SuppressThisWarning VEditor unused
108  output afi_bready,
109  input [ 5:0] afi_bid, // @SuppressThisWarning VEditor unused
110  input [ 1:0] afi_bresp, // @SuppressThisWarning VEditor unused
111  // PL extra (non-AXI) signals
112  input [ 7:0] afi_wcount,
113  input [ 5:0] afi_wacount,
114  output afi_wrissuecap1en,
115  // AXI_HP signals - read channel
116  // read address
117  output [31:0] afi_araddr,
118  output afi_arvalid,
119  input afi_arready, // @SuppressThisWarning VEditor unused - used FIF0 level
120  output [ 5:0] afi_arid,
121  output [ 1:0] afi_arlock,
122  output [ 3:0] afi_arcache,
123  output [ 2:0] afi_arprot,
124  output [ 3:0] afi_arlen,
125  output [ 1:0] afi_arsize,
126  output [ 1:0] afi_arburst,
127  output [ 3:0] afi_arqos,
128  // read data
129  input [63:0] afi_rdata,
130  input afi_rvalid,
131  output afi_rready,
132  input [ 5:0] afi_rid, // @SuppressThisWarning VEditor unused
133  input afi_rlast, // @SuppressThisWarning VEditor unused
134  input [ 1:0] afi_rresp, // @SuppressThisWarning VEditor unused
135  // PL extra (non-AXI) signals
136  input [ 7:0] afi_rcount,
137  input [ 2:0] afi_racount,
138  output afi_rdissuecap1en,
139 // Data/type FIFO, host -> device
140  // Data System memory or FIS -> device
141  output [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
142  output [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
143  output h2d_valid, // output register full
144  input h2d_ready, // send FIFO has room for data (>= 8? dwords)
145 
146 // Data/type FIFO, device -> host
147  input [31:0] d2h_data, // FIFO output data
148  input [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
149  input d2h_valid, // Data available from the transport layer in FIFO
150  input d2h_many, // Multiple DWORDs available from the transport layer in FIFO
151  output d2h_ready, // This module or DMA consumes DWORD
152 
153  // communication with transport/link/phys layers
154 // input phy_rst, // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
155  input [ 1:0] phy_ready, // 0 - not ready, 1..3 - negotiated speed
156  input xmit_ok, // FIS transmission acknowledged OK
157  input xmit_err, // Error during sending of a FIS
158  input syncesc_recv, // These two inputs interrupt transmit
159  output pcmd_st_cleared, // bit was cleared by software
160  output syncesc_send, // Send sync escape
161  input syncesc_send_done, // "SYNC escape until the interface is quiescent..."
162  output comreset_send, // Not possible yet?
163  input cominit_got,
164  output set_offline, // electrically idle
165  input x_rdy_collision, // X_RDY/X_RDY collision on interface
166 
167  output send_R_OK, // Should it be originated in this layer SM?
168  output send_R_ERR,
169 
170  // additional errors from SATA layers (single-clock pulses):
171  input serr_DT, // RWC: Transport state transition error
172  input serr_DS, // RWC: Link sequence error
173  input serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
174  input serr_DC, // RWC: CRC error in Link layer
175  input serr_DB, // RWC: 10B to 8B decode error
176  input serr_DW, // RWC: COMMWAKE signal was detected
177  input serr_DI, // RWC: PHY Internal Error
178  // sirq_PRC,
179  // sirq_IF || // sirq_INF
180  input serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
181  input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
182  input serr_EC, // RWC: Persistent Communication or Data Integrity Error
183  input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
184  input serr_EM, // RWC: Communication between the device and host was lost but re-established
185  input serr_EI, // RWC: Recovered Data integrity Error
186  // additional control signals for SATA layers
187  output [3:0] sctl_ipm, // Interface power management transitions allowed
188  output [3:0] sctl_spd, // Interface maximal speed
189 
190 
191 
192  output irq, // CPU interrupt request
193 
194 `ifdef USE_DATASCOPE
195 // Datascope interface (write to memory that can be software-read)
196  input datascope1_clk,
197  input [ADDRESS_BITS-1:0] datascope1_waddr,
198  input datascope1_we,
199  input [31:0] datascope1_di,
200 `endif
201 
202 
203 `ifdef USE_DRP
204  output drp_en, // @aclk strobes drp_ad
205  output drp_we,
206  output [14:0] drp_addr,
207  output [15:0] drp_di,
208  input drp_rdy,
209  input [15:0] drp_do,
210 `endif
211  input [FREQ_METER_WIDTH - 1:0] xclk_period, // relative (to 2*clk) xclk period
212  input [31:0] debug_in_phy,
213  input [31:0] debug_in_link
214 
215 
216 );
217 `ifdef USE_DATASCOPE
218 // Datascope interface (write to memory that can be software-read)
219  wire datascope_clk;
220  wire [ADDRESS_BITS-1:0] datascope_waddr;
221  wire datascope_we;
222  wire [31:0] datascope_di;
223 `endif
224 
225 // axi_ahci_regs signals:
226 // 1. Notification of data written @ hba_clk
227  wire [ADDRESS_BITS-1:0] soft_write_addr; // register address written by software
228  wire [31:0] soft_write_data; // register data written (after applying wstb and type (RO, RW, RWC, RW1)
229  wire soft_write_en; // write enable for data write
230 // wire hba_arst; // hba async reset (currently does ~ the same as port reset)
231 // wire port_arst; // port0 async reset by software
232 // 2. HBA R/W registers, use hba clock
233 // wire hba_rst;
234  wire regs_we_acs;
235 // wire [1:0] regs_re_fsm;
236  wire [31:0] regs_din_from_acs; // from fsm
237  wire regs_we_freceive;
238  wire [1:0] regs_re_ftransmit; // [0] - re, [1] - regen
239  wire [ADDRESS_BITS-1:0] regs_saddr; // read/write adderss from ahci_fsm
240  wire [ADDRESS_BITS-1:0] regs_waddr;
241  wire [ADDRESS_BITS-1:0] regs_raddr;
242  wire [31:0] regs_din_from_freceive;
243  wire [31:0] regs_dout;
244 
245  reg en_port;
246  wire [1:0] regs_re = en_port ? regs_re_ftransmit : 2'b0; // [0] - re, [1] - regen
247  wire regs_we = en_port ? ( regs_we_freceive | regs_we_acs) : 1'b0;
248 
249 
250  wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) |
251  ({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) |
252  ({ADDRESS_BITS{regs_we_acs}} & regs_saddr);
253 
254 
255 /*
256  wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{en_port & regs_we_freceive}} & regs_waddr) |
257  ({ADDRESS_BITS{en_port & regs_re_ftransmit[0]}} & regs_raddr) |
258  ({ADDRESS_BITS{en_port & regs_we_acs}} & regs_saddr);
259 */
260  wire [31:0] regs_din = ({32{regs_we_freceive}} & regs_din_from_freceive) |
261  ({32{regs_we_acs}} & regs_din_from_acs);
262 // wire [1:0] regs_re = regs_re_ftransmit | regs_re_fsm; // [0] - re, [1] - regen
263 
264 
265 //---------------------
266 
267 // wire [31:7] ctba; // input[31:7]
268  wire ctba_ld; // input
269  wire [15:0] prdtl; // input[15:0]
270 
271  wire dev_wr; // input
272  wire dma_cmd_start; // input
273  wire dma_prd_start; // input
274  wire dma_cmd_abort_xmit; // input
275  wire dma_cmd_abort_fsm; // abort from FSM (also from ahci_fis_transmit)
276 
277 // Use some of the custom registers in the address space?
278  wire [17:0] fsm_pgm_ad; // @aclk, address/data to program the AHCI FSM
279  wire fsm_pgm_wa; // @aclk, address strobe to program the AHCI FSM
280  wire fsm_pgm_wd; // @aclk, data strobe to program the AHCI FSM
281 
282 
283  wire [ 3:0] axi_wr_cache_mode; // input[3:0]
284  wire [ 3:0] axi_rd_cache_mode; // input[3:0]
285  wire set_axi_cache_mode; // input (both axi_wr_cache_mode and axi_rd_cache_mode)
286  wire dma_ct_busy; // output reg
287  wire [ 4:0] dma_ct_addr; // input[4:0]
288  wire [ 1:0] dma_ct_re; // input
289  wire [31:0] dma_ct_data; // output[31:0] reg
290 /// wire dma_prd_done; // output (finished next prd)
291  wire dma_prd_irq_clear; // reset pending prd_irq
292  wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
293  wire dma_cmd_busy; // output reg (DMA engine is processing PRDs)
294  wire dma_cmd_done; // output (last PRD is over)
295 
296  wire dma_abort_busy;
297  wire dma_abort_done;
298  wire axi_mismatch;
299 
300  wire [31:0] dma_dout; // output[31:0]
301  wire dma_dav; // output
302  wire dma_re; // input
303  wire last_h2d_data;// when active and no new data for 2 clocks - that was the last one
304 
305  wire dma_in_ready; // output
306  wire dma_we; // input
307  wire dma_extra_din; // all DRDs are transferred to memory, but FIFO has some data. Valid when transfer is stopped
308 
309 
310 // ---------------------------------------
311  // fsm <-> ahc_fis_receive
312  // fsm ->
313  wire frcv_first_vld;
314  // To debug/recover -
315  wire frcv_first_invalid; // Some data available from FIFO, but not FIS head
316  wire frcv_first_flush; // Skip FIFO data until empty or FIS head
317 
318  wire frcv_get_dsfis;
319  wire frcv_get_psfis;
320  wire frcv_get_rfis;
321  wire frcv_get_sdbfis;
322  wire frcv_get_ufis;
323  wire frcv_get_data_fis;
324  wire frcv_get_ignore; // ignore whatever FIS (use for DMA activate too?)
325  // short commands:
326  // next commands use register address/data/we for 1 clock cycle - after next to command (commnd - t0, we - t2)
327  wire frcv_update_err_sts;// update PxTFD.STS and PxTFD.ERR from the last received regs d2h
328  wire frcv_update_pio; // update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)
329 
330  wire frcv_update_prdbc; // update PRDBC in registers
331  wire frcv_clear_bsy_drq; // clear PxTFD.STS.BSY and PxTFD.STS.DRQ, update
332  wire frcv_clear_bsy_set_drq; // clear PxTFD.STS.BSY and sets PxTFD.STS.DRQ, update
333 
334  wire frcv_set_bsy; // set PxTFD.STS.BSY, update
335  wire frcv_set_sts_7f; // set PxTFD.STS = 0x7f, update
336  wire frcv_set_sts_80; // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update
337  wire frcv_decr_dwcr; // decrement DMA Xfer counter after read // need pulse to 'update_prdbc' to write to registers
338  wire frcv_decr_dwcw; // decrement DMA Xfer counter after write // need pulse to 'update_prdbc' to write to registers
339  wire frcv_clear_xfer_cntr; // Clear pXferCntr to 0
340 
341  // fsm <-
342  wire frcv_busy; // busy processing FIS
343  wire frcv_done; // done processing FIS (see fis_ok, fis_err, fis_ferr)
344  wire frcv_ok; // FIS done, checksum OK reset by starting a new get FIS
345  wire frcv_err; // FIS done, checksum ERROR reset by starting a new get FIS
346  wire frcv_ferr; // FIS done, fatal error - FIS too long
347  wire frcv_extra; // DMA all transferred, but some data is still in left. . Does not deny frcv_ok
348 
349  wire frcv_set_update_sig; // when set, enables get_sig (and resets itself)
350 /// wire frcv_pUpdateSig; // state variable
351 /// wire frcv_sig_available; // signature data available
352  wire frcv_update_sig; // update signature
353 
354 
355  // fsm <- state variables that are maintained inside 'ahc_fis_receive'
356  wire [7:0] tfd_sts; // Current PxTFD status field (updated after regFIS and SDB - certain fields)
357  // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
358 // wire [7:0] tfd_err; // Current PxTFD error field (updated after regFIS and SDB)
359  wire fis_i; // value of "I" field in received regsD2H or SDB FIS
360 /// wire sdb_n; // value of "N" field in received SDB FIS
361  wire dma_a; // value of "A" field in received DMA Setup FIS
362 /// wire dma_d; // value of "D" field in received DMA Setup FIS
363  wire pio_i; // value of "I" field in received PIO Setup FIS
364  wire pio_d; // value of "D" field in received PIO Setup FIS
365 /// wire [7:0] pio_es; // value of PIO E_Status
366  wire pPioXfer;
367 /// wire sactive0; // bit 0 of sActive DWORD received in SDB FIS
368  // Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
369 
370  wire [31:2] xfer_cntr;
371  wire xfer_cntr_zero;
372 
373 /// wire [11:0] data_in_dwords; // number of DWORDs received in data FIS (can be updated internally). Is it needed?
374 
375  // fsm <-> ahc_fis_transmit
376  // Command pulses to execute states fsm -> ahc_fis_transmit
377  wire fsnd_fetch_cmd; // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
378  // wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
379  wire fsnd_cfis_xmit; // transmit command (wait for dma_ct_busy == 0)
380  wire fsnd_dx_xmit; // send FIS header DWORD, (just 0x46), then forward DMA data
381  // transmit until error, 2048DWords or pDmaXferCnt
382  wire fsnd_atapi_xmit; // tarsmit ATAPI command FIS
383  // responses fsm <- ahc_fis_transmit
384  wire fsnd_done;
385 /// wire fsnd_busy;
386  // Short action pulses fsm -> ahc_fis_transmit
387  wire fsnd_clearCmdToIssue; // From CFIS:SUCCESS
388  // State variables fsm <- ahc_fis_transmit
389  wire fsnd_pCmdToIssue; // AHCI port variable
390  wire [ 2:0] fsnd_dx_err; // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err) 2 - X-RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
391  wire fsnd_ch_c; // Clear busy upon R_OK for this FIS
392  wire fsnd_ch_b; // Built-in self test command
393  wire fsnd_ch_r; // reset - may need to send SYNC escape before this command
394  wire fsnd_ch_p; // prefetchable - only used with non-zero PRDTL or ATAPI bit set
395  wire fsnd_ch_w; // Write: system memory -> device
396  wire fsnd_ch_a; // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
397 /// wire [4:0] fsnd_ch_cfl; // length of the command FIS in DW, 0 means none. 0 and 1 - illegal, ... Maybe not needed outside ahc_fis_transmit
398 
399  wire [11:0] data_out_dwords; // number of DWORDs sent in data FIS
400 
401  wire was_hba_rst;
402  wire was_port_rst;
403 
404  // signals between ahci_fsm and ahci_ctrl_stat
405 /// wire update_regs_pending;
406  wire update_all_regs;
407  wire update_regs_busy; // valid same cycle as update_all_regs
408 
409 /// wire st01_pending; // software turned PxCMD.ST from 0 to 1
410 /// wire st10_pending; // software turned PxCMD.ST from 1 to 0
411 /// wire st_pending_reset;// reset both st01_pending and st10_pending
412 
413 
414  // these following individual signals may be unneded - use update_all_regs -> update_regs_busy
415 // wire update_GHC__IS;
416 // wire update_HBA_PORT__PxIS;
417 // wire update_HBA_PORT__PxSSTS;
418 // wire update_HBA_PORT__PxSERR;
419 // wire update_HBA_PORT__PxCMD;
420 // wire update_HBA_PORT__PxCI;
421 
422 // PxCMD
423 // wire pcmd_clear_icc; // clear PxCMD.ICC field
424  wire pcmd_esp = 1'b0; // external SATA port (just forward value)
425 /// wire pcmd_cr; // command list run - current - read only by software (set by HBA)
426  wire pcmd_cr_set; // command list run set
427  wire pcmd_cr_reset; // command list run reset
428 // wire pcmd_fr; // ahci_fis_receive:get_fis_busy - use frcv_busy
429 
430  wire pcmd_fre0; // FIS enable copy to memory
431  wire pcmd_fre = pcmd_fre0 || 1; // FIS enable copy to memory
432 // wire pcmd_clear_bsy_drq; // == ahci_fis_receive:clear_bsy_drq
433  wire pcmd_clo; // RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
434 // wire pcmd_clear_st; // RW clear ST (start) bit
435  wire pcmd_st; // current value
436  wire pfsm_started; // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
437 //clear_bsy_drq
438 // Interrupt inputs
439  wire sirq_TFE; // RWC: Task File Error Status
440  wire sirq_IF; // RWC: Interface Fatal Error Status (sect. 6.1.2)
441  wire sirq_INF; // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
442  wire sirq_OF; // RWC: Overflow Status
443  wire sirq_PRC; // RO: PhyRdy changed Status
444  wire sirq_PC; // RO: Port Connect Change Status
445  wire sirq_DP; // RWC: Descriptor Processed with "I" bit on
446  wire sirq_UF; // RO: Unknown FIS
447  wire sirq_SDB; // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
448  wire sirq_DS; // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
449  wire sirq_PS; // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
450  wire sirq_DHR; // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
451 // SCR1:SError (only inputs that are not available in sirq_* ones
452  //sirq_PC;
453  //sirq_UF
454  wire serr_diag_X; // value of PxSERR.DIAG.X
455 
456 
457 
458 // SCR0: SStatus
459  wire ssts_ipm_dnp; // device not present or communication not established
460  wire ssts_ipm_active; // device in active state
461  wire ssts_ipm_part; // device in partial state
462  wire ssts_ipm_slumb; // device in slumber state
463  wire ssts_ipm_devsleep; // device in DevSleep state
464 
465  wire ssts_spd_dnp; // device not present or communication not established
466  wire ssts_spd_gen1; // Gen 1 rate negotiated
467  wire ssts_spd_gen2; // Gen 2 rate negotiated
468  wire ssts_spd_gen3; // Gen 3 rate negotiated
469 
470  wire ssts_det_ndnp; // no device detected, phy communication not established
471  wire ssts_det_dnp; // device detected, but phy communication not established
472  wire ssts_det_dp; // device detected, phy communication established
473  wire ssts_det_offline; // device detected, phy communication established
474  wire [3:0] ssts_det; // current value of PxSSTS.DET
475 
476  // SCR2:SControl (written by software only)
477  wire [3:0] sctl_det; // Device detection initialization requested
478  wire sctl_det_changed; // Software had written new value to sctl_det
479  wire sctl_det_reset; // clear sctl_det_changed
480 
481  wire pxci0_clear; // PxCI clear
482  wire pxci0; // pxCI current value
483  wire hba_rst_done; // HBA reset done - clear GHC.HR (and some other regs)
484 
485  wire comreset_send0; // just disabling it
486 
487 
488  wire [9:0] last_jump_addr;
489  wire [31:0] debug_dma;
490  wire [31:0] debug_dma1;
491  wire [31:0] debug_dma_h2d;
492 
493  wire unsolicited_en; // enable processing of cominit_got and PxERR.DIAG.W interrupts from
494  // this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4
495 
496 
497  assign comreset_send = comreset_send0 && 0;
498 
499  // Async FF
500  always @ (posedge mrst or posedge mclk) begin
501  if (mrst) en_port <= 0;
502  else en_port <= 1;
503  end
504 
505 /*
506  reg [1:0] port_en; //disable port signals until initialized from the hardware (currently - PLL)
507  wire ports_rst = ~port_en[1];
508  always @ (posedge mclk) begin
509  if (port_arst_any) port_en[0] <= 0;
510  else if (mrst) port_en[0] <= 1;
511 
512  if (port_arst_any) port_en[1] <= 0;
513  else if (!mrst && port_en[0]) port_en[1] <= 1;
514 
515  end
516 */
517 
518 
519  ahci_fsm// #(
520 // .READ_REG_LATENCY(2),
521 // .ADDRESS_BITS(10)
522 // )
523  ahci_fsm_i (
524  .hba_rst (mrst), // input
525  .mclk (mclk), // input
526  .was_hba_rst (was_hba_rst), // input
527  .was_port_rst (was_port_rst), // input
528 
529  .aclk (aclk), // input
530  .arst (arst), // input
531  .pgm_ad (fsm_pgm_ad), // input[17:0]
532  .pgm_wa (fsm_pgm_wa), // input
533  .pgm_wd (fsm_pgm_wd), // input
534 
535  .phy_ready (phy_ready), // input
536  .syncesc_send (syncesc_send), // output
537  .comreset_send (comreset_send0), // output
538  .syncesc_send_done (syncesc_send_done), // input
539  .cominit_got (cominit_got), // input
540  .set_offline (set_offline), // output
541 // .x_rdy_collision (x_rdy_collision), // input
542 
543  .send_R_OK (send_R_OK), // output
544  .send_R_ERR (send_R_ERR), // output
545 
546 /// .update_pending (update_regs_pending),// input
547  .update_all (update_all_regs), // output
548  .update_busy (update_regs_busy), // input
549 /// .update_gis (update_GHC__IS), // output
550 /// .update_pis (update_HBA_PORT__PxIS), // output
551 /// .update_ssts (update_HBA_PORT__PxSSTS), // output
552 /// .update_serr (update_HBA_PORT__PxSERR), // output
553 /// .update_pcmd (update_HBA_PORT__PxCMD), // output
554 /// .update_pci (update_HBA_PORT__PxCI), // output
555 /// .st01_pending (st01_pending), // input
556 /// .st10_pending (st10_pending), // input
557 /// .st_pending_reset (st_pending_reset), // output
558 // .pcmd_clear_icc (pcmd_clear_icc), // output
559 // .pcmd_esp (pcmd_esp), // output
560 // .pcmd_cr (pcmd_cr), // input
561  .pcmd_cr_set (pcmd_cr_set), // output
562  .pcmd_cr_reset (pcmd_cr_reset), // output
563 // .pcmd_fr (pcmd_fr), // output
564 // .pcmd_clear_bsy_drq (pcmd_clear_bsy_drq),// output
565  .pcmd_clo (pcmd_clo), // input
566 // .pcmd_clear_st (pcmd_clear_st), // output
567  .pcmd_st (pcmd_st), // input
568  .pfsm_started (pfsm_started), // output
569  .pcmd_st_cleared (pcmd_st_cleared), // input
570  .sirq_TFE (sirq_TFE), // output
571  .sirq_IF (sirq_IF), // output
572  .sirq_INF (sirq_INF), // output
573  .sirq_OF (sirq_OF), // output
574  .sirq_PRC (sirq_PRC), // output
575  .sirq_PC (sirq_PC), // output
576  .sirq_DP (sirq_DP), // output
577  .sirq_UF (sirq_UF), // output
578  .sirq_SDB (sirq_SDB), // output
579  .sirq_DS (sirq_DS), // output
580  .sirq_PS (sirq_PS), // output
581  .sirq_DHR (sirq_DHR), // output
582  .serr_diag_X (serr_diag_X), // input
583  .ssts_ipm_dnp (ssts_ipm_dnp), // output
584  .ssts_ipm_active (ssts_ipm_active), // output
585  .ssts_ipm_part (ssts_ipm_part), // output
586  .ssts_ipm_slumb (ssts_ipm_slumb), // output
587  .ssts_ipm_devsleep (ssts_ipm_devsleep), // output
588  .ssts_spd_dnp (ssts_spd_dnp), // output
589  .ssts_spd_gen1 (ssts_spd_gen1), // output
590  .ssts_spd_gen2 (ssts_spd_gen2), // output
591  .ssts_spd_gen3 (ssts_spd_gen3), // output
592  .ssts_det_ndnp (ssts_det_ndnp), // output
593  .ssts_det_dnp (ssts_det_dnp), // output
594  .ssts_det_dp (ssts_det_dp), // output
595  .ssts_det_offline (ssts_det_offline), // output
596  .ssts_det (ssts_det), // input[3:0]
597 /// .sctl_ipm (sctl_ipm), // input[3:0]
598 /// .sctl_spd (sctl_spd), // input[3:0]
599  .sctl_det (sctl_det), // input[3:0]
600  .sctl_det_changed (sctl_det_changed), // input
601  .sctl_det_reset (sctl_det_reset), // output
602  .hba_rst_done (hba_rst_done), // output
603  .pxci0_clear (pxci0_clear), // output
604  .pxci0 (pxci0), // input
605 
606 /// .dma_prd_done (dma_prd_done), // input
607  .dma_prd_irq_clear (dma_prd_irq_clear), // output
608  .dma_prd_irq_pend (dma_prd_irq_pend), // input
609 
610  .dma_cmd_busy (dma_cmd_busy), // input
611 /// .dma_cmd_done (dma_cmd_done), // input
612  .dma_cmd_abort (dma_cmd_abort_fsm), // output
613  .dma_abort_done (dma_abort_done), // input
614  .fis_first_invalid (frcv_first_invalid),// input
615  .fis_first_flush (frcv_first_flush), // output
616 
617  .fis_first_vld (frcv_first_vld), // input
618  .fis_type (d2h_data[7:0]), // input[7:0] FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
619  .bist_bits (d2h_data[23:16]), // bits that define built-in self test
620 
621  .get_dsfis (frcv_get_dsfis), // output
622  .get_psfis (frcv_get_psfis), // output
623  .get_rfis (frcv_get_rfis), // output
624  .get_sdbfis (frcv_get_sdbfis), // output
625  .get_ufis (frcv_get_ufis), // output
626  .get_data_fis (frcv_get_data_fis), // output
627  .get_ignore (frcv_get_ignore), // output
628 /// .get_fis_busy (frcv_busy), // input
629  .get_fis_done (frcv_done), // input
630  .fis_ok (frcv_ok), // input
631  .fis_err (frcv_err), // input
632  .fis_ferr (frcv_ferr), // input
633  .fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
634 
635  .set_update_sig (frcv_set_update_sig),// output
636 /// .pUpdateSig (frcv_pUpdateSig), // input
637 /// .sig_available (frcv_sig_available), // input
638  .update_sig (frcv_update_sig), // output
639 
640  .update_err_sts (frcv_update_err_sts),// output
641  .update_pio (frcv_update_pio), // output
642  .update_prdbc (frcv_update_prdbc), // output
643  .clear_bsy_drq (frcv_clear_bsy_drq), // output
644  .clear_bsy_set_drq (frcv_clear_bsy_set_drq), //output
645  .set_bsy (frcv_set_bsy), // output
646  .set_sts_7f (frcv_set_sts_7f), // output
647  .set_sts_80 (frcv_set_sts_80), // output
648  .clear_xfer_cntr (frcv_clear_xfer_cntr), //output Clear pXferCntr
649  .decr_dwcr (frcv_decr_dwcr), // output increment pXferCntr after transmit by data transmitted)
650  .decr_dwcw (frcv_decr_dwcw), // output increment pXferCntr after transmit by data transmitted)
651 // .decr_DXC_dw (data_out_dwords), // output[11:2] **** Probably not needed
652  .pxcmd_fre ( pcmd_fre), // input
653  .pPioXfer (pPioXfer), // input
654  .tfd_sts (tfd_sts), // input[7:0]
655 /// .tfd_err (tfd_err), // input[7:0]
656  .fis_i (fis_i), // input
657 /// .sdb_n (sdb_n), // input
658  .dma_a (dma_a), // input
659 /// .dma_d (dma_d), // input
660  .pio_i (pio_i), // input
661  .pio_d (pio_d), // input
662 /// .sactive0 (sactive0), // input
663 /// .pio_es (pio_es), // input[7:0]
664 /// .xfer_cntr (xfer_cntr[31:2]), // input[31:2]
665  .xfer_cntr_zero (xfer_cntr_zero), // input
666 
667  .fetch_cmd (fsnd_fetch_cmd), // output
668  .cfis_xmit (fsnd_cfis_xmit), // output
669  .dx_xmit (fsnd_dx_xmit), // output
670  .atapi_xmit (fsnd_atapi_xmit), // output
671  .xmit_done (fsnd_done), // input
672 /// .xmit_busy (fsnd_busy), // input
673  .clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS
674  .pCmdToIssue (fsnd_pCmdToIssue), // input
675  .dx_err (fsnd_dx_err), // input[2:0]
676 /// .ch_prdtl (prdtl), // input[15:0]
677  .ch_c (fsnd_ch_c), // input
678  .ch_b (fsnd_ch_b), // input
679  .ch_r (fsnd_ch_r), // input
680  .ch_p (fsnd_ch_p), // input
681  .ch_w (fsnd_ch_w), // input
682  .ch_a (fsnd_ch_a), // input
683 /// .ch_cfl (fsnd_ch_cfl), // input[4:0]
684 /// .dwords_sent (data_out_dwords) // input[11:0] ????
685  .unsolicited_en (unsolicited_en), // input
686  .last_jump_addr (last_jump_addr)
687  );
688 
689 wire debug_data_in_ready; // output
690 wire debug_fis_end_w; // output
691 wire[1:0] debug_fis_end_r; // output[1:0]
692 wire[1:0] debug_get_fis_busy_r; // output[1:0]
693 
694 
695 localparam DATA_TYPE_DMA = 0;
696 localparam DATA_TYPE_FIS_HEAD = 1;
697 localparam DATA_TYPE_OK = 2;
698 localparam DATA_TYPE_ERR = 3;
699 
700 reg [12:0] debug_d2h_length;
701 reg [12:0] debug_d2h_length_prev;
702 reg was_good_bad;
703 reg was_good_bad_prev;
704 
705 always @(posedge mclk) if (d2h_ready && d2h_valid) begin
706  if (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length_prev <= debug_d2h_length;
707 
708  if (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length <= 0;
709  else if (d2h_type == DATA_TYPE_DMA) debug_d2h_length <= debug_d2h_length + 1;
710 
711  if (d2h_type == DATA_TYPE_FIS_HEAD) was_good_bad_prev <= was_good_bad;
712 
713  if ((d2h_type == DATA_TYPE_OK) || (d2h_type == DATA_TYPE_ERR)) was_good_bad <= (d2h_type == DATA_TYPE_OK);
714 
715 end
716 
717  axi_ahci_regs #(
718  .ADDRESS_BITS (ADDRESS_BITS),
719  .HBA_RESET_BITS (HBA_RESET_BITS),
720  .RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
721  ) axi_ahci_regs_i (
722  .aclk (aclk), // input
723  .arst (arst), // input
724  .awaddr (awaddr), // input[31:0]
725  .awvalid (awvalid), // input
726  .awready (awready), // output
727  .awid (awid), // input[11:0]
728  .awlen (awlen), // input[3:0]
729  .awsize (awsize), // input[1:0]
730  .awburst (awburst), // input[1:0]
731  .wdata (wdata), // input[31:0]
732  .wvalid (wvalid), // input
733  .wready (wready), // output
734  .wid (wid), // input[11:0]
735  .wlast (wlast), // input
736  .wstb (wstb), // input[3:0]
737  .bvalid (bvalid), // output
738  .bready (bready), // input
739  .bid (bid), // output[11:0]
740  .bresp (bresp), // output[1:0]
741  .araddr (araddr), // input[31:0]
742  .arvalid (arvalid), // input
743  .arready (arready), // output
744  .arid (arid), // input[11:0]
745  .arlen (arlen), // input[3:0]
746  .arsize (arsize), // input[1:0]
747  .arburst (arburst), // input[1:0]
748  .rdata (rdata), // output[31:0]
749  .rvalid (rvalid), // output
750  .rready (rready), // input
751  .rid (rid), // output[11:0]
752  .rlast (rlast), // output
753  .rresp (rresp), // output[1:0]
754  .soft_write_addr (soft_write_addr), // output[9:0]
755  .soft_write_data (soft_write_data), // output[31:0]
756  .soft_write_en (soft_write_en), // output
757  .hba_arst (hba_arst), // output // does not include arst
758  .port_arst_any (port_arst_any), // async set by arst
759  .port_arst (port_arst), // output // does not include arst
760  .hba_clk (mclk), // input
761  .hba_rst (mrst), // input // deasserted when mclk is stable
762  .hba_addr (regs_addr), // input[9:0]
763  .hba_we (regs_we), // input
764  .hba_re (regs_re), // input[1:0]
765  .hba_din (regs_din), // input[31:0]
766  .hba_dout (regs_dout), // output[31:0]
767  .pgm_ad (fsm_pgm_ad), // output[17:0] reg
768  .pgm_wa (fsm_pgm_wa), // output reg
769  .pgm_wd (fsm_pgm_wd), // output reg
770  .afi_wcache (axi_wr_cache_mode),// output[3:0] reg
771  .afi_rcache (axi_rd_cache_mode),// output[3:0] reg
772  .afi_cache_set (set_axi_cache_mode), // output
773  .was_hba_rst (was_hba_rst), // output
774  .was_port_rst (was_port_rst), // output
775  .debug_in0 ({ 2'b0,
776  was_good_bad_prev,
777  debug_d2h_length_prev[12:0],
778  2'b0,
779  was_good_bad,
780  debug_d2h_length[12:0]
781  }),
782 
783 // .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
784 // debug_dma1[23:0]}), // debug_in_link), // input[31:0]
785  .debug_in1 ({debug_in_link[15:8],
786  debug_dma1[23:0]}), // debug_in_link), // input[31:0]
787  .debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
788 // .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
789  .debug_in3 ({debug_in_link[7:0],
790  frcv_busy,frcv_ok, // 2'b0,
791 `ifdef USE_DATASCOPE
792  datascope_waddr[9:0],
793 `else
794  10'b0,
795 `endif
796  frcv_err,frcv_ferr, // 2'b0,
797  last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
798 `ifdef USE_DRP
799  ,.drp_en (drp_en), // output reg
800  .drp_we (drp_we), // output reg
801  .drp_addr (drp_addr), // output[14:0] reg
802  .drp_di (drp_di), // output[15:0] reg
803  .drp_rdy (drp_rdy), // input
804  .drp_do (drp_do) // input[15:0]
805 `endif
806 
807 
808 `ifdef USE_DATASCOPE
809  ,.datascope_clk (datascope_clk), // input
810  .datascope_waddr (datascope_waddr), // input[9:0]
811  .datascope_we (datascope_we), // input
812  .datascope_di (datascope_di), // input[31:0]
813 
814  .datascope1_clk (datascope1_clk), // input
815  .datascope1_waddr (datascope1_waddr),// input[9:0]
816  .datascope1_we (datascope1_we), // input
817  .datascope1_di (datascope1_di) // input[31:0]
818 `endif
819 /// .debug_in (debug_in[31:0])
820  );
821  ahci_ctrl_stat #(
822  .ADDRESS_BITS (ADDRESS_BITS)
823  ) ahci_ctrl_stat_i (
824  .mrst (mrst), // input
825  .mclk (mclk), // input
826  .was_hba_rst (was_hba_rst), // input
827  .was_port_rst (was_port_rst), // input
828  .soft_write_addr (soft_write_addr), // input[9:0]
829  .soft_write_data (soft_write_data), // input[31:0]
830  .soft_write_en (soft_write_en), // input
831  .regs_addr (regs_saddr), // output[9:0] reg
832  .regs_we (regs_we_acs), // output reg
833  .regs_din (regs_din_from_acs), // output[31:0] reg
834  .update_pending (), /// update_regs_pending), // output
835  .update_all (update_all_regs), // input
836  .update_busy (update_regs_busy), // output
837 /// .st01_pending (st01_pending), // output reg
838 /// .st10_pending (st10_pending), // output reg
839 /// .st_pending_reset (st_pending_reset), // input
840 
841  .update_gis (1'b0), // update_GHC__IS), // input
842  .update_pis (1'b0), // update_HBA_PORT__PxIS), // input
843  .update_ssts (1'b0), // update_HBA_PORT__PxSSTS), // input
844  .update_serr (1'b0), // update_HBA_PORT__PxSERR), // input
845  .update_pcmd (1'b0), // update_HBA_PORT__PxCMD), // input
846  .update_pci (1'b0), // update_HBA_PORT__PxCI), // input
847  .update_ghc (1'b0), // update _GHC_GHC, // input
848 
849 // .pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input
850  .pcmd_esp (pcmd_esp), // input
851  .pcmd_cr (), //pcmd_cr), // output
852  .pcmd_cr_set (pcmd_cr_set), // input
853  .pcmd_cr_reset (pcmd_cr_reset), // input
854  .pcmd_fr (frcv_busy), // input
855  .pcmd_fre (pcmd_fre0), // output
856  .pcmd_clear_bsy_drq (frcv_clear_bsy_drq), // input
857  .pcmd_clo (pcmd_clo), // output
858  .pcmd_clear_st (1'b0), // pcmd_clear_st), // input
859  .pcmd_st (pcmd_st), // output
860  .pfsm_started (pfsm_started), // input
861  .pcmd_st_cleared (pcmd_st_cleared), // output reg
862  .sirq_TFE (sirq_TFE), // input
863  .sirq_IF (sirq_IF), // input
864  .sirq_INF (sirq_INF), // input
865  .sirq_OF (sirq_OF), // input
866  .sirq_PRC (sirq_PRC), // input
867  .sirq_PC (sirq_PC), // input
868  .sirq_DP (sirq_DP), // input
869  .sirq_UF (sirq_UF), // input
870  .sirq_SDB (sirq_SDB), // input
871  .sirq_DS (sirq_DS), // input
872  .sirq_PS (sirq_PS), // input
873  .sirq_DHR (sirq_DHR), // input
874  .serr_DT (serr_DT), // input
875  .serr_DS (serr_DS), // input
876  .serr_DH (serr_DH), // input
877  .serr_DC (serr_DC), // input
878  .serr_DB (serr_DB), // input
879  .serr_DW (serr_DW), // input
880  .serr_DI (serr_DI), // input
881  .serr_EE (serr_EE), // input
882  .serr_EP (serr_EP), // input
883  .serr_EC (serr_EC), // input
884  .serr_ET (serr_ET), // input
885  .serr_EM (serr_EM), // input
886  .serr_EI (serr_EI), // input
887  .serr_diag_X (serr_diag_X), // output
888  .ssts_ipm_dnp (ssts_ipm_dnp), // input
889  .ssts_ipm_active (ssts_ipm_active), // input
890  .ssts_ipm_part (ssts_ipm_part), // input
891  .ssts_ipm_slumb (ssts_ipm_slumb), // input
892  .ssts_ipm_devsleep (ssts_ipm_devsleep), // input
893  .ssts_spd_dnp (ssts_spd_dnp), // input
894  .ssts_spd_gen1 (ssts_spd_gen1), // input
895  .ssts_spd_gen2 (ssts_spd_gen2), // input
896  .ssts_spd_gen3 (ssts_spd_gen3), // input
897  .ssts_det_ndnp (ssts_det_ndnp), // input
898  .ssts_det_dnp (ssts_det_dnp), // input
899  .ssts_det_dp (ssts_det_dp), // input
900  .ssts_det_offline (ssts_det_offline), // input
901  .ssts_det (ssts_det), // output[3:0]
902  .sctl_ipm (sctl_ipm), // output[3:0] reg
903  .sctl_spd (sctl_spd), // output[3:0] reg
904  .sctl_det (sctl_det), // output[3:0] reg
905  .sctl_det_changed (sctl_det_changed), // output reg
906  .sctl_det_reset (sctl_det_reset), // input
907  .pxci0_clear (pxci0_clear), // input
908  .pxci0 (pxci0), // output
909  .hba_reset_done (hba_rst_done), // input
910  .unsolicited_en (unsolicited_en), // output
911  .irq (irq) // output reg
912  );
913 
914  ahci_dma ahci_dma_i (
915  .mrst (mrst), // input
916  .hrst (hrst), // input
917  .mclk (mclk), // input
918  .hclk (hclk), // input
919 // .ctba (regs_dout[31:7]),// input[31:7]
920  .ctba (regs_dout[31:4]),// input[31:4]
921  .ctba_ld (ctba_ld), // input
922  .prdtl (prdtl), // input[15:0]
923  .dev_wr (dev_wr), // input
924  .cmd_start (dma_cmd_start), // input
925  .prd_start (dma_prd_start), // input
926  .cmd_abort (dma_cmd_abort_xmit || dma_cmd_abort_fsm), // input
927  .axi_wr_cache_mode (axi_wr_cache_mode), // input[3:0]
928  .axi_rd_cache_mode (axi_rd_cache_mode), // input[3:0]
929  .set_axi_wr_cache_mode (set_axi_cache_mode), // input
930  .set_axi_rd_cache_mode (set_axi_cache_mode), // input
931  .ct_busy (dma_ct_busy), // output reg
932  .ct_addr (dma_ct_addr), // input[4:0]
933  .ct_re (dma_ct_re), // input[1:0]
934  .ct_data (dma_ct_data), // output[31:0] reg
935  .prd_done (), /// dma_prd_done), // output
936 
937  .prd_irq_clear (dma_prd_irq_clear),// input
938  .prd_irq_pend (dma_prd_irq_pend), // output reg
939 
940  .cmd_busy (dma_cmd_busy), // dma_cmd_busy), // output reg Some data to transmit!
941  .cmd_done (dma_cmd_done), // output
942  .abort_busy (dma_abort_busy),
943  .abort_done (dma_abort_done),
944  .axi_mismatch (axi_mismatch), // handled, but may report as an error - axi counters are 0, but calculated ones are not
945  .sys_out (dma_dout), // output[31:0]
946  .sys_dav (dma_dav), // output
947  .sys_re (dma_re), // input
948  .last_h2d_data (last_h2d_data), // output
949  .sys_in (d2h_data), // input[31:0]
950  .sys_nfull (dma_in_ready), // output
951  .sys_we (dma_we), // input
952  .extra_din (dma_extra_din), // output reg
953  .afi_awaddr (afi_awaddr), // output[31:0]
954  .afi_awvalid (afi_awvalid), // output
955  .afi_awready (afi_awready), // input
956  .afi_awid (afi_awid), // output[5:0]
957  .afi_awlock (afi_awlock), // output[1:0]
958  .afi_awcache (afi_awcache), // output[3:0] reg
959  .afi_awprot (afi_awprot), // output[2:0]
960  .afi_awlen (afi_awlen), // output[3:0]
961  .afi_awsize (afi_awsize), // output[1:0]
962  .afi_awburst (afi_awburst), // output[1:0]
963  .afi_awqos (afi_awqos), // output[3:0]
964  .afi_wdata (afi_wdata), // output[63:0]
965  .afi_wvalid (afi_wvalid), // output
966  .afi_wready (afi_wready), // input
967  .afi_wid (afi_wid), // output[5:0]
968  .afi_wlast (afi_wlast), // output
969  .afi_wstrb (afi_wstrb), // output[7:0]
970  .afi_bvalid (afi_bvalid), // input
971  .afi_bready (afi_bready), // output
972  .afi_bid (afi_bid), // input[5:0]
973  .afi_bresp (afi_bresp), // input[1:0]
974  .afi_wcount (afi_wcount), // input[7:0]
975  .afi_wacount (afi_wacount), // input[5:0]
976  .afi_wrissuecap1en (afi_wrissuecap1en), // output
977  .afi_araddr (afi_araddr), // output[31:0]
978  .afi_arvalid (afi_arvalid), // output
979  .afi_arready (afi_arready), // input
980  .afi_arid (afi_arid), // output[5:0]
981  .afi_arlock (afi_arlock), // output[1:0]
982  .afi_arcache (afi_arcache), // output[3:0] reg
983  .afi_arprot (afi_arprot), // output[2:0]
984  .afi_arlen (afi_arlen), // output[3:0]
985  .afi_arsize (afi_arsize), // output[1:0]
986  .afi_arburst (afi_arburst), // output[1:0]
987  .afi_arqos (afi_arqos), // output[3:0]
988  .afi_rdata (afi_rdata), // input[63:0]
989  .afi_rvalid (afi_rvalid), // input
990  .afi_rready (afi_rready), // output
991  .afi_rid (afi_rid), // input[5:0]
992  .afi_rlast (afi_rlast), // input
993  .afi_rresp (afi_rresp), // input[1:0]
994  .afi_rcount (afi_rcount), // input[7:0]
995  .afi_racount (afi_racount), // input[2:0]
996  .afi_rdissuecap1en (afi_rdissuecap1en), // output
997  .debug_out (debug_dma), // output[31:0]
998  .debug_out1 (debug_dma1) // output[31:0]
999  ,.debug_dma_h2d (debug_dma_h2d)
1000  );
1001 
1002  ahci_fis_receive #(
1003  .ADDRESS_BITS (ADDRESS_BITS)
1004  ) ahci_fis_receive_i (
1005  .hba_rst (mrst), // input
1006  .mclk (mclk), // input
1007  .pcmd_st_cleared (pcmd_st_cleared), // input
1008  .fis_first_vld (frcv_first_vld), // output reg
1009  .fis_first_invalid (frcv_first_invalid), // output
1010  .fis_first_flush (frcv_first_flush), // input
1011 
1012  .get_dsfis (frcv_get_dsfis), // input
1013  .get_psfis (frcv_get_psfis), // input
1014  .get_rfis (frcv_get_rfis), // input
1015  .get_sdbfis (frcv_get_sdbfis), // input
1016  .get_ufis (frcv_get_ufis), // input
1017  .get_data_fis (frcv_get_data_fis), // input
1018  .get_ignore (frcv_get_ignore), // input
1019 
1020  .get_fis_busy (frcv_busy), // output reg
1021  .get_fis_done (frcv_done), // output reg
1022  .fis_ok (frcv_ok), // output reg
1023  .fis_err (frcv_err), // output reg
1024  .fis_ferr (frcv_ferr), // output
1025 
1026  .dma_prds_done (dma_cmd_done), // input
1027  .fis_extra (frcv_extra), // output
1028 
1029  .set_update_sig (frcv_set_update_sig), // input
1030  .pUpdateSig (), /// frcv_pUpdateSig), // output
1031  .sig_available (), ///frcv_sig_available), // output reg
1032  .update_sig (frcv_update_sig), // input
1033 
1034  .update_err_sts (frcv_update_err_sts), // input
1035  .update_pio (frcv_update_pio), // input update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)
1036 
1037  .update_prdbc (frcv_update_prdbc), // input
1038  .clear_prdbc (fsnd_fetch_cmd), // input save resources - clear prdbc for every commnad
1039 
1040  .clear_bsy_drq (frcv_clear_bsy_drq), // input
1041  .clear_bsy_set_drq (frcv_clear_bsy_set_drq), // input
1042 
1043  .set_bsy (frcv_set_bsy), // input
1044  .set_sts_7f (frcv_set_sts_7f), // input
1045  .set_sts_80 (frcv_set_sts_80), // input
1046  .clear_xfer_cntr (frcv_clear_xfer_cntr), // input Clear pXferCntr
1047  .decr_dwcr (frcv_decr_dwcr), // input
1048  .decr_dwcw (frcv_decr_dwcw), // input
1049  .decr_DXC_dw (data_out_dwords), // input[11:2]
1050  .pcmd_fre (pcmd_fre), // input
1051 
1052  .pPioXfer (pPioXfer), // output reg
1053 
1054  .tfd_sts (tfd_sts), // output[7:0]
1055  .tfd_err (), /// tfd_err), // output[7:0]
1056  .fis_i (fis_i), // output reg
1057  .sdb_n (), /// sdb_n), // output reg
1058  .dma_a (dma_a), // output reg
1059  .dma_d (), /// dma_d), // output reg
1060  .pio_i (pio_i), // output reg
1061  .pio_d (pio_d), // output reg
1062  .pio_es (), /// pio_es), // output[7:0] reg
1063  .sactive0 (), /// sactive0), // output reg
1064  .xfer_cntr (xfer_cntr[31:2]), // output[31:2]
1065  .xfer_cntr_zero (xfer_cntr_zero), // output reg
1066  .data_in_dwords (), /// data_in_dwords), // output[11:0]
1067 
1068  .reg_addr (regs_waddr), // output[9:0] reg
1069  .reg_we (regs_we_freceive), // output reg
1070  .reg_data (regs_din_from_freceive), // output[31:0] reg
1071  .hba_data_in (d2h_data), // input[31:0]
1072  .hba_data_in_type (d2h_type), // input[1:0]
1073  .hba_data_in_valid (d2h_valid), // input
1074  .hba_data_in_many (d2h_many), // input
1075  .hba_data_in_ready (d2h_ready), // output
1076  .dma_in_ready (dma_in_ready), // input
1077  .dma_in_valid (dma_we) // output
1078 
1079  ,.debug_data_in_ready (debug_data_in_ready), // output
1080  .debug_fis_end_w (debug_fis_end_w), // output
1081  .debug_fis_end_r (debug_fis_end_r), // output[1:0]
1082  .debug_get_fis_busy_r (debug_get_fis_busy_r) // output[1:0]
1083  );
1084 wire ahci_fis_transmit_busy;
1085 wire [9:0] xmit_dbg_01;
1086  ahci_fis_transmit #(
1087  .PREFETCH_ALWAYS (PREFETCH_ALWAYS),
1088  .READ_REG_LATENCY (READ_REG_LATENCY),
1089  .READ_CT_LATENCY (READ_CT_LATENCY),
1090  .ADDRESS_BITS (ADDRESS_BITS)
1091  ) ahci_fis_transmit_i (
1092 // .hba_rst (mrst), // input TODO: Reset when !PxCMD.ST? pcmd_st
1093  .hba_rst (mrst || !pcmd_st), // input TODO: Reset when !PxCMD.ST? pcmd_st
1094  .mclk (mclk), // input
1095  .pcmd_st_cleared (pcmd_st_cleared), // input
1096  .fetch_cmd (fsnd_fetch_cmd), // input
1097  .cfis_xmit (fsnd_cfis_xmit), // input
1098  .dx_xmit (fsnd_dx_xmit), // input
1099  .atapi_xmit (fsnd_atapi_xmit), // input
1100 
1101  .done (fsnd_done), // output reg
1102  .busy (ahci_fis_transmit_busy), /// fsnd_busy), // output reg
1103  .clearCmdToIssue (fsnd_clearCmdToIssue), // input
1104  .pCmdToIssue (fsnd_pCmdToIssue), // output
1105  .xmit_ok (xmit_ok), // input
1106  .xmit_err (xmit_err), // input
1107  .syncesc_recv (syncesc_recv), // input
1108  .xrdy_collision (x_rdy_collision), // input
1109  .dx_err (fsnd_dx_err), // output[1:0]
1110  .ch_prdtl (prdtl), // output[15:0]
1111  .ch_c (fsnd_ch_c), // output
1112  .ch_b (fsnd_ch_b), // output
1113  .ch_r (fsnd_ch_r), // output
1114  .ch_p (fsnd_ch_p), // output
1115  .ch_w (fsnd_ch_w), // output
1116  .ch_a (fsnd_ch_a), // output
1117  .ch_cfl (), /// fsnd_ch_cfl), // output[4:0]
1118 
1119  .dwords_sent (data_out_dwords), // output[11:0] reg
1120  .reg_addr (regs_raddr), // output[9:0] reg
1121  .reg_re (regs_re_ftransmit), // output[1:0]
1122  .reg_rdata (regs_dout), // input[31:0]
1123  .xfer_cntr (xfer_cntr[31:2]), // input[31:2]
1124  .xfer_cntr_zero (xfer_cntr_zero), // input
1125  .dma_ctba_ld (ctba_ld), // output
1126  .dma_start (dma_cmd_start), // output
1127  .dma_dev_wr (dev_wr), // output
1128  .dma_ct_busy (dma_ct_busy), // input
1129  .dma_prd_start (dma_prd_start), // output reg
1130  .dma_cmd_abort (dma_cmd_abort_xmit), // output reg
1131  .ct_addr (dma_ct_addr), // output[4:0] reg
1132  .ct_re (dma_ct_re), // output[1:0]
1133  .ct_data (dma_ct_data), // input[31:0]
1134  .dma_out (dma_dout), // input[31:0]
1135  .dma_dav (dma_dav), // input
1136  .dma_re (dma_re), // output
1137  .last_h2d_data (last_h2d_data), // input
1138  .todev_data (h2d_data), // output[31:0] reg
1139  .todev_type (h2d_type), // output[1:0] reg
1140  .todev_valid (h2d_valid), // output
1141  .todev_ready (h2d_ready) // input
1142  ,.debug_01(xmit_dbg_01)
1143  );
1144 
1145 // Datascope code
1146 //`define DATASCOPE_V2
1147 // Datascope interface (write to memory that can be software-read)
1148 `define DATASCOPE_FIS_DATA 1
1149 
1150 `ifdef USE_DATASCOPE
1151 
1152  `ifdef DATASCOPE_V2
1153  reg [ADDRESS_BITS-1:0] datascope_waddr_r;
1154  reg [1:0] datascope_run;
1155  // reg [1:0] datascope_run;
1156 
1157  assign datascope_we = datascope_run[1];
1158  assign datascope_clk = mclk;
1159  assign datascope_waddr = datascope_waddr_r;
1160 
1161  assign datascope_di = {
1162  debug_dma_h2d[3], // done_flush_mclk,
1163  debug_dma_h2d[2], // dout_vld,
1164  debug_dma_h2d[1], // dout_re,
1165  debug_dma_h2d[0], // last_DW,
1166 
1167  dma_dout[27:16],
1168  debug_dma_h2d[19:18], // 2'b0
1169  debug_dma_h2d[17], // fifo_rd
1170  debug_dma_h2d[16:12], // raddr[4:0]
1171  debug_dma_h2d[11:8], //fifo_do_vld[3:0]
1172 
1173  debug_dma_h2d[7], // fifo_dav
1174  debug_dma_h2d[6], // fifo_dav2_w
1175  debug_dma_h2d[5], // fifo_dav2
1176  debug_dma_h2d[4] // flushing_mclk
1177  };
1178 
1179  // dma_dout[
1180 
1181  always @ (posedge mclk) begin
1182  if (mrst) datascope_run[0] <= 0;
1183  else if (dma_cmd_start) datascope_run[0] <= 1;
1184  else if (dma_cmd_done) datascope_run[0] <= 0;
1185 
1186  if (mrst || !datascope_run[0]) datascope_run[1] <= 0;
1187  else if (dma_dav) datascope_run[1] <= 1;
1188 
1189  if (fsnd_cfis_xmit) datascope_waddr_r <= 0;
1190  else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
1191 
1192 
1193  end
1194  //`endif // DATASCOPE_V2
1195  `else
1196  //`ifdef DATASCOPE_V1
1197  `ifdef DATASCOPE_FIS_DATA
1198  datascope_timing #(
1199  .ADDRESS_BITS(10),
1200  .FIS_LEN(5)
1201  ) datascope_timing_i (
1202  .clk (mclk), // input
1203  .rst (mrst), // input
1204  .soft_write_addr (soft_write_addr), // input[9:0]
1205  .soft_write_data (soft_write_data), // input[31:0]
1206  .soft_write_en (soft_write_en), // input
1207  .h2d_data (h2d_data), // input[31:0]
1208  .h2d_type (h2d_type), // input[1:0]
1209  .h2d_valid (h2d_valid), // input
1210  .h2d_ready (h2d_ready), // input
1211  .d2h_data (d2h_data), // input[31:0]
1212  .d2h_type (d2h_type), // input[1:0]
1213  .d2h_valid (d2h_valid), // input
1214  .d2h_ready (d2h_ready), // input
1215  .datascope_clk (datascope_clk), // output
1216  .datascope_waddr (datascope_waddr), // output[9:0] reg
1217  .datascope_we (datascope_we), // output
1218  .datascope_di (datascope_di) // output[31:0] reg
1219  );
1220 
1221  `else // DATASCOPE_FIS_DATA
1222  localparam DATASCOPE_CFIS_START=0;
1223  localparam DATASCOPE_INCOMING_POST=32;
1224 
1225  reg [ADDRESS_BITS-1:0] datascope_waddr_r=0;
1226  reg [1:0] datascope_run;
1227 
1228  reg datascope_link_run;
1229  wire datascope_is_state_send_ready = (debug_in_link[4:0] == 16);
1230  wire datascope_is_state_idle = (debug_in_link[4:0] == 22);
1231  reg datascope_was_state_send_ready;
1232  reg [3:0] datascope_id;
1233 
1234  wire datascope_incoming_start = debug_in_link[22]; // set_rcvr_wait; // start logging
1235  wire datascope_incoming_started = debug_in_phy[21:20] == 1; //
1236  wire datascope_incomining_preend = debug_in_phy[21]; // d2h_type_in[1
1237  reg [2:0] datascope_incoming_run;
1238  reg [7:0] datascope_incoming_cntr;
1239  reg datascope_receive_fis;
1240  reg [9:0] datascope_last_jump_addr=0;
1241  reg [1:0] datascope_new_jump = 0;
1242  reg [15:0] datascope_jump_cntr = 0;
1243 
1244  //last_jump_addr[9:0]
1245  always @(posedge mclk) begin
1246  if (mrst) datascope_new_jump[0] <= 0;
1247  else datascope_new_jump[0] <= datascope_last_jump_addr != last_jump_addr;
1248 
1249  if (mrst) datascope_new_jump[1] <= 0;
1250  else datascope_new_jump[1] <= datascope_new_jump[0];
1251 
1252  if (mrst) datascope_last_jump_addr <= 0;
1253  if (datascope_new_jump) datascope_last_jump_addr <= last_jump_addr;
1254 
1255  if (datascope_we) datascope_jump_cntr <= datascope_jump_cntr+1;
1256 
1257 
1258 
1259  if (mrst) datascope_receive_fis <= 0;
1260  else if (datascope_incoming_start) datascope_receive_fis <= 1;
1261  else if (frcv_get_dsfis ||
1262  frcv_get_psfis ||
1263  frcv_get_rfis ||
1264  frcv_get_sdbfis ||
1265  frcv_get_ufis ||
1266  frcv_get_data_fis ||
1267  frcv_get_ignore) datascope_receive_fis <= 0;
1268 
1269  if (mrst) datascope_incoming_run[0] <= 0;
1270  else if (datascope_incoming_start || datascope_receive_fis) datascope_incoming_run[0] <= 1;
1271  else if (datascope_incoming_cntr == 0) datascope_incoming_run[0] <= 0;
1272 
1273  if (mrst || datascope_incoming_start) datascope_incoming_run[1] <= 0;
1274  else if (datascope_incoming_run[0] && datascope_incoming_started) datascope_incoming_run[1] <= 1;
1275  else if (datascope_incoming_run[2]) datascope_incoming_run[1] <= 0;
1276 
1277  if (mrst || datascope_incoming_start) datascope_incoming_run[2] <= 0;
1278  else if (datascope_incoming_run[1] && datascope_incomining_preend) datascope_incoming_run[2] <= 1;
1279  else if (datascope_incoming_cntr == 0) datascope_incoming_run[2] <= 0;
1280 
1281  if (mrst || !datascope_incoming_run[2] ||
1282  datascope_incoming_start ||
1283  datascope_receive_fis) datascope_incoming_cntr <= DATASCOPE_INCOMING_POST;
1284  else if (|datascope_incoming_cntr) datascope_incoming_cntr <= datascope_incoming_cntr - 1;
1285 
1286  end
1287 
1288  assign datascope_clk = mclk;
1289  assign datascope_waddr = last_jump_addr;
1290  assign datascope_we = &datascope_new_jump;
1291  assign datascope_di = {2'h3, fsnd_pCmdToIssue, xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};
1292  always @(posedge mclk) begin
1293  if (mrst) datascope_run[0] <= 0;
1294  else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
1295  else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
1296 
1297  if (mrst) datascope_link_run <= 0;
1298  else if (datascope_is_state_send_ready && !datascope_was_state_send_ready) datascope_link_run <= 1; // state_send_sof
1299  else if (datascope_is_state_idle) datascope_link_run <= 0; // state_idle
1300 
1301  datascope_was_state_send_ready <= datascope_is_state_send_ready;
1302 
1303 
1304  datascope_run[1] <= datascope_run[0];
1305 
1306 
1307 
1308  if (mrst) datascope_id <= 0;
1309  else if (fsnd_cfis_xmit) datascope_id <= datascope_id + 1;
1310 
1311  end
1312  `endif // DATASCOPE_FIS_DATA
1313 
1314  `endif // DATASCOPE_V1
1315 
1316 `endif // USE_DATASCOPE
1317 endmodule
1318 
1319 module datascope_timing #(
1320  parameter ADDRESS_BITS = 10, // for datascope
1321  parameter FIS_LEN = 5 // Record this number of DWORDS in each FIS
1322  )(
1323  input clk,
1324  input rst,
1325  // receiving time punch command and 3-bit tag
1326  input [ADDRESS_BITS-1:0] soft_write_addr,
1327  input [31:0] soft_write_data,
1328  input soft_write_en,
1329 
1330  // outgoing FISes
1331  input [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
1332  input [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
1333  input h2d_valid, // output register full
1334  input h2d_ready, // send FIFO has room for data (>= 8? dwords)
1335 
1336  // Incoming FISes
1337 
1338 // Data/type FIFO, device -> host
1339  input [31:0] d2h_data, // FIFO output data
1340  input [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
1341  input d2h_valid, // Data available from the transport layer in FIFO
1342  input d2h_ready, // This module or DMA consumes DWORD
1343 
1344  output datascope_clk,
1345  output reg [ADDRESS_BITS-1:0] datascope_waddr,
1346  output datascope_we,
1347  output reg [31:0] datascope_di
1348  );
1349 // RO: Device ID
1350  localparam PCI_Header__ID__DID__ADDR = 'h60;
1351  localparam PCI_Header__ID__DID__MASK = 'hffff0000;
1352  localparam PCI_Header__ID__DID__DFLT = 'h10000;
1353 // RO: Vendor ID
1354  localparam PCI_Header__ID__VID__ADDR = 'h60;
1355  localparam PCI_Header__ID__VID__MASK = 'hffff;
1356  localparam PCI_Header__ID__VID__DFLT = 'hfffe;
1357 // RW: HBA Interrupt Disable
1358  localparam PCI_Header__CMD__ID__ADDR = 'h61;
1359  localparam PCI_Header__CMD__ID__MASK = 'h400;
1360  localparam PCI_Header__CMD__ID__DFLT = 'h0;
1361 // RO: Fast Back-to-Back Enable
1362  localparam PCI_Header__CMD__FBE__ADDR = 'h61;
1363  localparam PCI_Header__CMD__FBE__MASK = 'h200;
1364  localparam PCI_Header__CMD__FBE__DFLT = 'h0;
1365 // RO: SERR Enable
1366  localparam PCI_Header__CMD__SEE__ADDR = 'h61;
1367  localparam PCI_Header__CMD__SEE__MASK = 'h100;
1368  localparam PCI_Header__CMD__SEE__DFLT = 'h0;
1369 // RO: Reserved
1370  localparam PCI_Header__CMD__WCC__ADDR = 'h61;
1371  localparam PCI_Header__CMD__WCC__MASK = 'h80;
1372  localparam PCI_Header__CMD__WCC__DFLT = 'h0;
1373 // RO: Parity Error Response Enable
1374  localparam PCI_Header__CMD__PEE__ADDR = 'h61;
1375  localparam PCI_Header__CMD__PEE__MASK = 'h40;
1376  localparam PCI_Header__CMD__PEE__DFLT = 'h0;
1377 // RO: Reserved
1378  localparam PCI_Header__CMD__VGA__ADDR = 'h61;
1379  localparam PCI_Header__CMD__VGA__MASK = 'h20;
1380  localparam PCI_Header__CMD__VGA__DFLT = 'h0;
1381 // RO: Reserved
1382  localparam PCI_Header__CMD__MWIE__ADDR = 'h61;
1383  localparam PCI_Header__CMD__MWIE__MASK = 'h10;
1384  localparam PCI_Header__CMD__MWIE__DFLT = 'h0;
1385 // RO: Reserved
1386  localparam PCI_Header__CMD__SCE__ADDR = 'h61;
1387  localparam PCI_Header__CMD__SCE__MASK = 'h8;
1388  localparam PCI_Header__CMD__SCE__DFLT = 'h0;
1389 // RW: Bus Master Enable (0 - stops any DMA)
1390  localparam PCI_Header__CMD__BME__ADDR = 'h61;
1391  localparam PCI_Header__CMD__BME__MASK = 'h4;
1392  localparam PCI_Header__CMD__BME__DFLT = 'h0;
1393 // RW: Memory Space enable (here - always?)
1394  localparam PCI_Header__CMD__MSE__ADDR = 'h61;
1395  localparam PCI_Header__CMD__MSE__MASK = 'h2;
1396  localparam PCI_Header__CMD__MSE__DFLT = 'h0;
1397 // RO: Enable IO space access (only for legacy IDE)
1398  localparam PCI_Header__CMD__IOSE__ADDR = 'h61;
1399  localparam PCI_Header__CMD__IOSE__MASK = 'h1;
1400  localparam PCI_Header__CMD__IOSE__DFLT = 'h0;
1401 // RWC: Detected Parity Error
1402  localparam PCI_Header__STS__DPE__ADDR = 'h61;
1403  localparam PCI_Header__STS__DPE__MASK = 'h80000000;
1404  localparam PCI_Header__STS__DPE__DFLT = 'h0;
1405 // RWC: Signaled System Error (HBA SERR)
1406  localparam PCI_Header__STS__SSE__ADDR = 'h61;
1407  localparam PCI_Header__STS__SSE__MASK = 'h40000000;
1408  localparam PCI_Header__STS__SSE__DFLT = 'h0;
1409 // RWC: Received Master Abort
1410  localparam PCI_Header__STS__RMA__ADDR = 'h61;
1411  localparam PCI_Header__STS__RMA__MASK = 'h20000000;
1412  localparam PCI_Header__STS__RMA__DFLT = 'h0;
1413 // RWC: Received Target Abort
1414  localparam PCI_Header__STS__RTA__ADDR = 'h61;
1415  localparam PCI_Header__STS__RTA__MASK = 'h10000000;
1416  localparam PCI_Header__STS__RTA__DFLT = 'h0;
1417 // RWC: Signaled Target Abort
1418  localparam PCI_Header__STS__STA__ADDR = 'h61;
1419  localparam PCI_Header__STS__STA__MASK = 'h8000000;
1420  localparam PCI_Header__STS__STA__DFLT = 'h0;
1421 // RO: PCI DEVSEL Timing
1422  localparam PCI_Header__STS__DEVT__ADDR = 'h61;
1423  localparam PCI_Header__STS__DEVT__MASK = 'h6000000;
1424  localparam PCI_Header__STS__DEVT__DFLT = 'h0;
1425 // RWC: Master Data Parity Error Detected
1426  localparam PCI_Header__STS__DPD__ADDR = 'h61;
1427  localparam PCI_Header__STS__DPD__MASK = 'h1000000;
1428  localparam PCI_Header__STS__DPD__DFLT = 'h0;
1429 // RO: Fast Back-To-Back Capable
1430  localparam PCI_Header__STS__FBC__ADDR = 'h61;
1431  localparam PCI_Header__STS__FBC__MASK = 'h800000;
1432  localparam PCI_Header__STS__FBC__DFLT = 'h0;
1433 // RO: 66 MHz Capable
1434  localparam PCI_Header__STS__C66__ADDR = 'h61;
1435  localparam PCI_Header__STS__C66__MASK = 'h200000;
1436  localparam PCI_Header__STS__C66__DFLT = 'h0;
1437 // RO: Capabilities List (PCI power management mandatory)
1438  localparam PCI_Header__STS__CL__ADDR = 'h61;
1439  localparam PCI_Header__STS__CL__MASK = 'h100000;
1440  localparam PCI_Header__STS__CL__DFLT = 'h100000;
1441 // RO: Interrupt Status (1 - asserted)
1442  localparam PCI_Header__STS__IS__ADDR = 'h61;
1443  localparam PCI_Header__STS__IS__MASK = 'h80000;
1444  localparam PCI_Header__STS__IS__DFLT = 'h0;
1445 // RO: HBA Revision ID
1446  localparam PCI_Header__RID__RID__ADDR = 'h62;
1447  localparam PCI_Header__RID__RID__MASK = 'hff;
1448  localparam PCI_Header__RID__RID__DFLT = 'h2;
1449 // RO: Base Class Code: 1 - Mass Storage Device
1450  localparam PCI_Header__CC__BCC__ADDR = 'h62;
1451  localparam PCI_Header__CC__BCC__MASK = 'hff000000;
1452  localparam PCI_Header__CC__BCC__DFLT = 'h1000000;
1453 // RO: Sub Class Code: 0x06 - SATA Device
1454  localparam PCI_Header__CC__SCC__ADDR = 'h62;
1455  localparam PCI_Header__CC__SCC__MASK = 'hff0000;
1456  localparam PCI_Header__CC__SCC__DFLT = 'h60000;
1457 // RO: Programming Interface: 1 - AHCI HBA major rev 1
1458  localparam PCI_Header__CC__PI__ADDR = 'h62;
1459  localparam PCI_Header__CC__PI__MASK = 'hff0000;
1460  localparam PCI_Header__CC__PI__DFLT = 'h10000;
1461 // RW: Cache Line Size
1462  localparam PCI_Header__CLS__CLS__ADDR = 'h63;
1463  localparam PCI_Header__CLS__CLS__MASK = 'hff;
1464  localparam PCI_Header__CLS__CLS__DFLT = 'h0;
1465 // RW: Master Latency Timer
1466  localparam PCI_Header__MLT__MLT__ADDR = 'h63;
1467  localparam PCI_Header__MLT__MLT__MASK = 'hff00;
1468  localparam PCI_Header__MLT__MLT__DFLT = 'h0;
1469 // RO: Multi-Function Device
1470  localparam PCI_Header__HTYPE__MFDT__ADDR = 'h63;
1471  localparam PCI_Header__HTYPE__MFDT__MASK = 'h8000;
1472  localparam PCI_Header__HTYPE__MFDT__DFLT = 'h0;
1473 // RO: Header Layout 0 - HBA uses a target device layout
1474  localparam PCI_Header__HTYPE__HL__ADDR = 'h63;
1475  localparam PCI_Header__HTYPE__HL__MASK = 'h7f00;
1476  localparam PCI_Header__HTYPE__HL__DFLT = 'h0;
1477 // RO: AHCI Base Address high bits, normally RW, but here RO to get to MAXIGP1 space
1478  localparam PCI_Header__ABAR__BA__ADDR = 'h69;
1479  localparam PCI_Header__ABAR__BA__MASK = 'hfffffff0;
1480  localparam PCI_Header__ABAR__BA__DFLT = 'h80000000;
1481 // RO: Prefetchable (this is not)
1482  localparam PCI_Header__ABAR__PF__ADDR = 'h69;
1483  localparam PCI_Header__ABAR__PF__MASK = 'h8;
1484  localparam PCI_Header__ABAR__PF__DFLT = 'h0;
1485 // RO: Type (0 - any 32-bit address, here it is hard-mapped
1486  localparam PCI_Header__ABAR__TP__ADDR = 'h69;
1487  localparam PCI_Header__ABAR__TP__MASK = 'h6;
1488  localparam PCI_Header__ABAR__TP__DFLT = 'h0;
1489 // RO: Resource Type Indicator: 0 - memory address
1490  localparam PCI_Header__ABAR__RTE__ADDR = 'h69;
1491  localparam PCI_Header__ABAR__RTE__MASK = 'h1;
1492  localparam PCI_Header__ABAR__RTE__DFLT = 'h0;
1493 // RO: SubSystem ID
1494  localparam PCI_Header__SS__SSID__ADDR = 'h6b;
1495  localparam PCI_Header__SS__SSID__MASK = 'hffff0000;
1496  localparam PCI_Header__SS__SSID__DFLT = 'h10000;
1497 // RO: SubSystem Vendor ID
1498  localparam PCI_Header__SS__SSVID__ADDR = 'h6b;
1499  localparam PCI_Header__SS__SSVID__MASK = 'hffff;
1500  localparam PCI_Header__SS__SSVID__DFLT = 'hfffe;
1501 // RO: ROM Base Address
1502  localparam PCI_Header__EROM__RBA__ADDR = 'h6c;
1503  localparam PCI_Header__EROM__RBA__MASK = 'hffffffff;
1504  localparam PCI_Header__EROM__RBA__DFLT = 'h0;
1505 // RO: Capabilities pointer
1506  localparam PCI_Header__CAP__CAP__ADDR = 'h6d;
1507  localparam PCI_Header__CAP__CAP__MASK = 'hff;
1508  localparam PCI_Header__CAP__CAP__DFLT = 'h40;
1509 // RO: Interrupt pin
1510  localparam PCI_Header__INTR__IPIN__ADDR = 'h6f;
1511  localparam PCI_Header__INTR__IPIN__MASK = 'hff00;
1512  localparam PCI_Header__INTR__IPIN__DFLT = 'h100;
1513 // RW: Interrupt Line
1514  localparam PCI_Header__INTR__ILINE__ADDR = 'h6f;
1515  localparam PCI_Header__INTR__ILINE__MASK = 'hff;
1516  localparam PCI_Header__INTR__ILINE__DFLT = 'h0;
1517 // RO: Minimal Grant
1518  localparam PCI_Header__MGNT__MGNT__ADDR = 'h6f;
1519  localparam PCI_Header__MGNT__MGNT__MASK = 'hff0000;
1520  localparam PCI_Header__MGNT__MGNT__DFLT = 'h0;
1521 // RO: Maximal Latency
1522  localparam PCI_Header__MLAT__MLAT__ADDR = 'h6f;
1523  localparam PCI_Header__MLAT__MLAT__MASK = 'hff000000;
1524  localparam PCI_Header__MLAT__MLAT__DFLT = 'h0;
1525 // RO: Next Capability pointer
1526  localparam PMCAP__PID__NEXT__ADDR = 'h70;
1527  localparam PMCAP__PID__NEXT__MASK = 'hff00;
1528  localparam PMCAP__PID__NEXT__DFLT = 'h0;
1529 // RO: This is PCI Power Management Capability
1530  localparam PMCAP__PID__CID__ADDR = 'h70;
1531  localparam PMCAP__PID__CID__MASK = 'hff;
1532  localparam PMCAP__PID__CID__DFLT = 'h1;
1533 // RO: PME_SUPPORT bits:'b01000
1534  localparam PMCAP__PC__PSUP__ADDR = 'h70;
1535  localparam PMCAP__PC__PSUP__MASK = 'hf8000000;
1536  localparam PMCAP__PC__PSUP__DFLT = 'h40000000;
1537 // RO: D2 Support - no
1538  localparam PMCAP__PC__D2S__ADDR = 'h70;
1539  localparam PMCAP__PC__D2S__MASK = 'h4000000;
1540  localparam PMCAP__PC__D2S__DFLT = 'h0;
1541 // RO: D1 Support - no
1542  localparam PMCAP__PC__D1S__ADDR = 'h70;
1543  localparam PMCAP__PC__D1S__MASK = 'h2000000;
1544  localparam PMCAP__PC__D1S__DFLT = 'h0;
1545 // RO: Maximal D3cold current
1546  localparam PMCAP__PC__AUXC__ADDR = 'h70;
1547  localparam PMCAP__PC__AUXC__MASK = 'h1c00000;
1548  localparam PMCAP__PC__AUXC__DFLT = 'h0;
1549 // RO: Device-specific initialization required
1550  localparam PMCAP__PC__DSI__ADDR = 'h70;
1551  localparam PMCAP__PC__DSI__MASK = 'h200000;
1552  localparam PMCAP__PC__DSI__DFLT = 'h0;
1553 // RO: PCI clock required to generate PME
1554  localparam PMCAP__PC__PMEC__ADDR = 'h70;
1555  localparam PMCAP__PC__PMEC__MASK = 'h80000;
1556  localparam PMCAP__PC__PMEC__DFLT = 'h0;
1557 // RO: Revision of Power Management Specification support version
1558  localparam PMCAP__PC__VS__ADDR = 'h70;
1559  localparam PMCAP__PC__VS__MASK = 'h70000;
1560  localparam PMCAP__PC__VS__DFLT = 'h0;
1561 // RWC: PME Status, set by hardware when HBA generates PME
1562  localparam PMCAP__PMCS__PMES__ADDR = 'h71;
1563  localparam PMCAP__PMCS__PMES__MASK = 'h8000;
1564  localparam PMCAP__PMCS__PMES__DFLT = 'h0;
1565 // RW: PME Enable
1566  localparam PMCAP__PMCS__PMEE__ADDR = 'h71;
1567  localparam PMCAP__PMCS__PMEE__MASK = 'h100;
1568  localparam PMCAP__PMCS__PMEE__DFLT = 'h0;
1569 // RW: Power State
1570  localparam PMCAP__PMCS__PS__ADDR = 'h71;
1571  localparam PMCAP__PMCS__PS__MASK = 'h3;
1572  localparam PMCAP__PMCS__PS__DFLT = 'h0;
1573 // RO: Supports 64-bit Addressing - no
1574  localparam GHC__CAP__S64A__ADDR = 'h0;
1575  localparam GHC__CAP__S64A__MASK = 'h80000000;
1576  localparam GHC__CAP__S64A__DFLT = 'h0;
1577 // RO: Supports Native Command Queuing - no
1578  localparam GHC__CAP__SNCQ__ADDR = 'h0;
1579  localparam GHC__CAP__SNCQ__MASK = 'h40000000;
1580  localparam GHC__CAP__SNCQ__DFLT = 'h0;
1581 // RO: Supports SNotification Register - no
1582  localparam GHC__CAP__SSNTF__ADDR = 'h0;
1583  localparam GHC__CAP__SSNTF__MASK = 'h20000000;
1584  localparam GHC__CAP__SSNTF__DFLT = 'h0;
1585 // RO: Supports Mechanical Presence Switch - no
1586  localparam GHC__CAP__SMPS__ADDR = 'h0;
1587  localparam GHC__CAP__SMPS__MASK = 'h10000000;
1588  localparam GHC__CAP__SMPS__DFLT = 'h0;
1589 // RO: Supports Staggered Spin-up - no
1590  localparam GHC__CAP__SSS__ADDR = 'h0;
1591  localparam GHC__CAP__SSS__MASK = 'h8000000;
1592  localparam GHC__CAP__SSS__DFLT = 'h0;
1593 // RO: Supports Aggressive Link Power Management - no
1594  localparam GHC__CAP__SALP__ADDR = 'h0;
1595  localparam GHC__CAP__SALP__MASK = 'h4000000;
1596  localparam GHC__CAP__SALP__DFLT = 'h0;
1597 // RO: Supports Activity LED - no
1598  localparam GHC__CAP__SAL__ADDR = 'h0;
1599  localparam GHC__CAP__SAL__MASK = 'h2000000;
1600  localparam GHC__CAP__SAL__DFLT = 'h0;
1601 // RO: Supports Command List Override - no (not capable of clearing BSY and DRQ bits, needs soft reset
1602  localparam GHC__CAP__SCLO__ADDR = 'h0;
1603  localparam GHC__CAP__SCLO__MASK = 'h1000000;
1604  localparam GHC__CAP__SCLO__DFLT = 'h0;
1605 // RO: Interface Maximal speed: 2 - Gen2, 3 - Gen3
1606  localparam GHC__CAP__ISS__ADDR = 'h0;
1607  localparam GHC__CAP__ISS__MASK = 'hf00000;
1608  localparam GHC__CAP__ISS__DFLT = 'h200000;
1609 // RO: AHCI only (0 - legacy too)
1610  localparam GHC__CAP__SAM__ADDR = 'h0;
1611  localparam GHC__CAP__SAM__MASK = 'h40000;
1612  localparam GHC__CAP__SAM__DFLT = 'h40000;
1613 // RO: Supports Port Multiplier - no
1614  localparam GHC__CAP__SPM__ADDR = 'h0;
1615  localparam GHC__CAP__SPM__MASK = 'h20000;
1616  localparam GHC__CAP__SPM__DFLT = 'h0;
1617 // RO: Supports FIS-based switching of the Port Multiplier - no
1618  localparam GHC__CAP__FBSS__ADDR = 'h0;
1619  localparam GHC__CAP__FBSS__MASK = 'h10000;
1620  localparam GHC__CAP__FBSS__DFLT = 'h0;
1621 // RO: PIO Multiple DRQ block - no
1622  localparam GHC__CAP__PMD__ADDR = 'h0;
1623  localparam GHC__CAP__PMD__MASK = 'h8000;
1624  localparam GHC__CAP__PMD__DFLT = 'h0;
1625 // RO: Slumber State Capable - no
1626  localparam GHC__CAP__SSC__ADDR = 'h0;
1627  localparam GHC__CAP__SSC__MASK = 'h4000;
1628  localparam GHC__CAP__SSC__DFLT = 'h0;
1629 // RO: Partial State Capable - no
1630  localparam GHC__CAP__PSC__ADDR = 'h0;
1631  localparam GHC__CAP__PSC__MASK = 'h2000;
1632  localparam GHC__CAP__PSC__DFLT = 'h0;
1633 // RO: Number of Command Slots, 0-based (0 means 1?)
1634  localparam GHC__CAP__NSC__ADDR = 'h0;
1635  localparam GHC__CAP__NSC__MASK = 'h1f00;
1636  localparam GHC__CAP__NSC__DFLT = 'h0;
1637 // RO: Command Completion Coalescing - no
1638  localparam GHC__CAP__CCCS__ADDR = 'h0;
1639  localparam GHC__CAP__CCCS__MASK = 'h80;
1640  localparam GHC__CAP__CCCS__DFLT = 'h0;
1641 // RO: Enclosure Management - no
1642  localparam GHC__CAP__EMS__ADDR = 'h0;
1643  localparam GHC__CAP__EMS__MASK = 'h40;
1644  localparam GHC__CAP__EMS__DFLT = 'h0;
1645 // RO: External SATA connector - yes
1646  localparam GHC__CAP__SXS__ADDR = 'h0;
1647  localparam GHC__CAP__SXS__MASK = 'h20;
1648  localparam GHC__CAP__SXS__DFLT = 'h20;
1649 // RO: Number of Ports, 0-based (0 means 1?)
1650  localparam GHC__CAP__NP__ADDR = 'h0;
1651  localparam GHC__CAP__NP__MASK = 'h1f;
1652  localparam GHC__CAP__NP__DFLT = 'h0;
1653 // RO: AHCI enable (0 - legacy)
1654  localparam GHC__GHC__AE__ADDR = 'h1;
1655  localparam GHC__GHC__AE__MASK = 'h80000000;
1656  localparam GHC__GHC__AE__DFLT = 'h80000000;
1657 // RO: MSI Revert to Single Message
1658  localparam GHC__GHC__MRSM__ADDR = 'h1;
1659  localparam GHC__GHC__MRSM__MASK = 'h4;
1660  localparam GHC__GHC__MRSM__DFLT = 'h0;
1661 // RW: Interrupt Enable (all ports)
1662  localparam GHC__GHC__IE__ADDR = 'h1;
1663  localparam GHC__GHC__IE__MASK = 'h2;
1664  localparam GHC__GHC__IE__DFLT = 'h0;
1665 // RW1: HBA reset (COMINIT, ...). Set by software, cleared by hardware, section 10.4.3
1666  localparam GHC__GHC__HR__ADDR = 'h1;
1667  localparam GHC__GHC__HR__MASK = 'h1;
1668  localparam GHC__GHC__HR__DFLT = 'h0;
1669 // RWC: Interrupt Pending Status (per port)
1670  localparam GHC__IS__IPS__ADDR = 'h2;
1671  localparam GHC__IS__IPS__MASK = 'hffffffff;
1672  localparam GHC__IS__IPS__DFLT = 'h0;
1673 // RO: Ports Implemented
1674  localparam GHC__PI__PI__ADDR = 'h3;
1675  localparam GHC__PI__PI__MASK = 'hffffffff;
1676  localparam GHC__PI__PI__DFLT = 'h1;
1677 // RO: AHCI Major Version 1.
1678  localparam GHC__VS__MJR__ADDR = 'h4;
1679  localparam GHC__VS__MJR__MASK = 'hffff0000;
1680  localparam GHC__VS__MJR__DFLT = 'h10000;
1681 // RO: AHCI Minor Version 3.1
1682  localparam GHC__VS__MNR__ADDR = 'h4;
1683  localparam GHC__VS__MNR__MASK = 'hffff;
1684  localparam GHC__VS__MNR__DFLT = 'h301;
1685 // RO: DevSleep Entrance from Slumber Only
1686  localparam GHC__CAP2__DESO__ADDR = 'h9;
1687  localparam GHC__CAP2__DESO__MASK = 'h20;
1688  localparam GHC__CAP2__DESO__DFLT = 'h0;
1689 // RO: Supports Aggressive Device Sleep Management
1690  localparam GHC__CAP2__SADM__ADDR = 'h9;
1691  localparam GHC__CAP2__SADM__MASK = 'h10;
1692  localparam GHC__CAP2__SADM__DFLT = 'h0;
1693 // RO: Supports Device Sleep
1694  localparam GHC__CAP2__SDS__ADDR = 'h9;
1695  localparam GHC__CAP2__SDS__MASK = 'h8;
1696  localparam GHC__CAP2__SDS__DFLT = 'h0;
1697 // RO: Automatic Partial to Slumber Transitions
1698  localparam GHC__CAP2__APST__ADDR = 'h9;
1699  localparam GHC__CAP2__APST__MASK = 'h4;
1700  localparam GHC__CAP2__APST__DFLT = 'h0;
1701 // RO: NVMHCI Present (section 10.15)
1702  localparam GHC__CAP2__NVMP__ADDR = 'h9;
1703  localparam GHC__CAP2__NVMP__MASK = 'h2;
1704  localparam GHC__CAP2__NVMP__DFLT = 'h0;
1705 // RO: BIOS/OS Handoff - not supported
1706  localparam GHC__CAP2__BOH__ADDR = 'h9;
1707  localparam GHC__CAP2__BOH__MASK = 'h1;
1708  localparam GHC__CAP2__BOH__DFLT = 'h0;
1709 // RW: Command List Base Address (1KB aligned)
1710  localparam HBA_PORT__PxCLB__CLB__ADDR = 'h40;
1711  localparam HBA_PORT__PxCLB__CLB__MASK = 'hfffffc00;
1712  localparam HBA_PORT__PxCLB__CLB__DFLT = 'h80000800;
1713 // RW: Command List Base Address (1KB aligned)
1714  localparam HBA_PORT__PxFB__CLB__ADDR = 'h42;
1715  localparam HBA_PORT__PxFB__CLB__MASK = 'hffffff00;
1716  localparam HBA_PORT__PxFB__CLB__DFLT = 'h80000c00;
1717 // RWC: Cold Port Detect Status
1718  localparam HBA_PORT__PxIS__CPDS__ADDR = 'h44;
1719  localparam HBA_PORT__PxIS__CPDS__MASK = 'h80000000;
1720  localparam HBA_PORT__PxIS__CPDS__DFLT = 'h0;
1721 // RWC: Task File Error Status
1722  localparam HBA_PORT__PxIS__TFES__ADDR = 'h44;
1723  localparam HBA_PORT__PxIS__TFES__MASK = 'h40000000;
1724  localparam HBA_PORT__PxIS__TFES__DFLT = 'h0;
1725 // RWC: Host Bus (PCI) Fatal error
1726  localparam HBA_PORT__PxIS__HBFS__ADDR = 'h44;
1727  localparam HBA_PORT__PxIS__HBFS__MASK = 'h20000000;
1728  localparam HBA_PORT__PxIS__HBFS__DFLT = 'h0;
1729 // RWC: ECC error R/W system memory
1730  localparam HBA_PORT__PxIS__HBDS__ADDR = 'h44;
1731  localparam HBA_PORT__PxIS__HBDS__MASK = 'h10000000;
1732  localparam HBA_PORT__PxIS__HBDS__DFLT = 'h0;
1733 // RWC: Interface Fatal Error Status (sect. 6.1.2)
1734  localparam HBA_PORT__PxIS__IFS__ADDR = 'h44;
1735  localparam HBA_PORT__PxIS__IFS__MASK = 'h8000000;
1736  localparam HBA_PORT__PxIS__IFS__DFLT = 'h0;
1737 // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
1738  localparam HBA_PORT__PxIS__INFS__ADDR = 'h44;
1739  localparam HBA_PORT__PxIS__INFS__MASK = 'h4000000;
1740  localparam HBA_PORT__PxIS__INFS__DFLT = 'h0;
1741 // RWC: Overflow Status
1742  localparam HBA_PORT__PxIS__OFS__ADDR = 'h44;
1743  localparam HBA_PORT__PxIS__OFS__MASK = 'h1000000;
1744  localparam HBA_PORT__PxIS__OFS__DFLT = 'h0;
1745 // RWC: Incorrect Port Multiplier Status
1746  localparam HBA_PORT__PxIS__IPMS__ADDR = 'h44;
1747  localparam HBA_PORT__PxIS__IPMS__MASK = 'h800000;
1748  localparam HBA_PORT__PxIS__IPMS__DFLT = 'h0;
1749 // RO: PhyRdy changed Status
1750  localparam HBA_PORT__PxIS__PRCS__ADDR = 'h44;
1751  localparam HBA_PORT__PxIS__PRCS__MASK = 'h400000;
1752  localparam HBA_PORT__PxIS__PRCS__DFLT = 'h0;
1753 // RWC: Device Mechanical Presence Status
1754  localparam HBA_PORT__PxIS__DMPS__ADDR = 'h44;
1755  localparam HBA_PORT__PxIS__DMPS__MASK = 'h80;
1756  localparam HBA_PORT__PxIS__DMPS__DFLT = 'h0;
1757 // RO: Port Connect Change Status
1758  localparam HBA_PORT__PxIS__PCS__ADDR = 'h44;
1759  localparam HBA_PORT__PxIS__PCS__MASK = 'h40;
1760  localparam HBA_PORT__PxIS__PCS__DFLT = 'h0;
1761 // RWC: Descriptor Processed
1762  localparam HBA_PORT__PxIS__DPS__ADDR = 'h44;
1763  localparam HBA_PORT__PxIS__DPS__MASK = 'h20;
1764  localparam HBA_PORT__PxIS__DPS__DFLT = 'h0;
1765 // RO: Unknown FIS
1766  localparam HBA_PORT__PxIS__UFS__ADDR = 'h44;
1767  localparam HBA_PORT__PxIS__UFS__MASK = 'h10;
1768  localparam HBA_PORT__PxIS__UFS__DFLT = 'h0;
1769 // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
1770  localparam HBA_PORT__PxIS__SDBS__ADDR = 'h44;
1771  localparam HBA_PORT__PxIS__SDBS__MASK = 'h8;
1772  localparam HBA_PORT__PxIS__SDBS__DFLT = 'h0;
1773 // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
1774  localparam HBA_PORT__PxIS__DSS__ADDR = 'h44;
1775  localparam HBA_PORT__PxIS__DSS__MASK = 'h4;
1776  localparam HBA_PORT__PxIS__DSS__DFLT = 'h0;
1777 // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
1778  localparam HBA_PORT__PxIS__PSS__ADDR = 'h44;
1779  localparam HBA_PORT__PxIS__PSS__MASK = 'h2;
1780  localparam HBA_PORT__PxIS__PSS__DFLT = 'h0;
1781 // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
1782  localparam HBA_PORT__PxIS__DHRS__ADDR = 'h44;
1783  localparam HBA_PORT__PxIS__DHRS__MASK = 'h1;
1784  localparam HBA_PORT__PxIS__DHRS__DFLT = 'h0;
1785 // RW: Cold Port Detect Enable
1786  localparam HBA_PORT__PxIE__CPDE__ADDR = 'h45;
1787  localparam HBA_PORT__PxIE__CPDE__MASK = 'h80000000;
1788  localparam HBA_PORT__PxIE__CPDE__DFLT = 'h0;
1789 // RW: Task File Error Enable
1790  localparam HBA_PORT__PxIE__TFEE__ADDR = 'h45;
1791  localparam HBA_PORT__PxIE__TFEE__MASK = 'h40000000;
1792  localparam HBA_PORT__PxIE__TFEE__DFLT = 'h0;
1793 // RW: Host Bus (PCI) Fatal Error Enable
1794  localparam HBA_PORT__PxIE__HBFE__ADDR = 'h45;
1795  localparam HBA_PORT__PxIE__HBFE__MASK = 'h20000000;
1796  localparam HBA_PORT__PxIE__HBFE__DFLT = 'h0;
1797 // RW: ECC Error R/W System Memory Enable
1798  localparam HBA_PORT__PxIE__HBDE__ADDR = 'h45;
1799  localparam HBA_PORT__PxIE__HBDE__MASK = 'h10000000;
1800  localparam HBA_PORT__PxIE__HBDE__DFLT = 'h0;
1801 // RW: Interface Fatal Error Enable (sect. 6.1.2)
1802  localparam HBA_PORT__PxIE__IFE__ADDR = 'h45;
1803  localparam HBA_PORT__PxIE__IFE__MASK = 'h8000000;
1804  localparam HBA_PORT__PxIE__IFE__DFLT = 'h0;
1805 // RW: Interface Non-Fatal Error Enable (sect. 6.1.2)
1806  localparam HBA_PORT__PxIE__INFE__ADDR = 'h45;
1807  localparam HBA_PORT__PxIE__INFE__MASK = 'h4000000;
1808  localparam HBA_PORT__PxIE__INFE__DFLT = 'h0;
1809 // RW: Overflow Enable
1810  localparam HBA_PORT__PxIE__OFE__ADDR = 'h45;
1811  localparam HBA_PORT__PxIE__OFE__MASK = 'h1000000;
1812  localparam HBA_PORT__PxIE__OFE__DFLT = 'h0;
1813 // RW: Incorrect Port Multiplier Enable
1814  localparam HBA_PORT__PxIE__IPME__ADDR = 'h45;
1815  localparam HBA_PORT__PxIE__IPME__MASK = 'h800000;
1816  localparam HBA_PORT__PxIE__IPME__DFLT = 'h0;
1817 // RW: PhyRdy changed Enable
1818  localparam HBA_PORT__PxIE__PRCE__ADDR = 'h45;
1819  localparam HBA_PORT__PxIE__PRCE__MASK = 'h400000;
1820  localparam HBA_PORT__PxIE__PRCE__DFLT = 'h0;
1821 // RO: Device Mechanical Presence Interrupt Enable
1822  localparam HBA_PORT__PxIE__DMPE__ADDR = 'h45;
1823  localparam HBA_PORT__PxIE__DMPE__MASK = 'h80;
1824  localparam HBA_PORT__PxIE__DMPE__DFLT = 'h0;
1825 // RW: Port Connect Change Interrupt Enable
1826  localparam HBA_PORT__PxIE__PCE__ADDR = 'h45;
1827  localparam HBA_PORT__PxIE__PCE__MASK = 'h40;
1828  localparam HBA_PORT__PxIE__PCE__DFLT = 'h0;
1829 // RW: Descriptor Processed Interrupt Enable
1830  localparam HBA_PORT__PxIE__DPE__ADDR = 'h45;
1831  localparam HBA_PORT__PxIE__DPE__MASK = 'h20;
1832  localparam HBA_PORT__PxIE__DPE__DFLT = 'h0;
1833 // RW: Unknown FIS
1834  localparam HBA_PORT__PxIE__UFE__ADDR = 'h45;
1835  localparam HBA_PORT__PxIE__UFE__MASK = 'h10;
1836  localparam HBA_PORT__PxIE__UFE__DFLT = 'h0;
1837 // RW: Device Bits Interrupt Enable
1838  localparam HBA_PORT__PxIE__SDBE__ADDR = 'h45;
1839  localparam HBA_PORT__PxIE__SDBE__MASK = 'h8;
1840  localparam HBA_PORT__PxIE__SDBE__DFLT = 'h0;
1841 // RW: DMA Setup FIS Interrupt Enable
1842  localparam HBA_PORT__PxIE__DSE__ADDR = 'h45;
1843  localparam HBA_PORT__PxIE__DSE__MASK = 'h4;
1844  localparam HBA_PORT__PxIE__DSE__DFLT = 'h0;
1845 // RW: PIO Setup FIS Interrupt Enable
1846  localparam HBA_PORT__PxIE__PSE__ADDR = 'h45;
1847  localparam HBA_PORT__PxIE__PSE__MASK = 'h2;
1848  localparam HBA_PORT__PxIE__PSE__DFLT = 'h0;
1849 // RW: D2H Register FIS Interrupt Enable
1850  localparam HBA_PORT__PxIE__DHRE__ADDR = 'h45;
1851  localparam HBA_PORT__PxIE__DHRE__MASK = 'h1;
1852  localparam HBA_PORT__PxIE__DHRE__DFLT = 'h0;
1853 // RW: Interface Communication Control
1854  localparam HBA_PORT__PxCMD__ICC__ADDR = 'h46;
1855  localparam HBA_PORT__PxCMD__ICC__MASK = 'hf0000000;
1856  localparam HBA_PORT__PxCMD__ICC__DFLT = 'h0;
1857 // RO: Aggressive Slumber/Partial - not implemented
1858  localparam HBA_PORT__PxCMD__ASP__ADDR = 'h46;
1859  localparam HBA_PORT__PxCMD__ASP__MASK = 'h8000000;
1860  localparam HBA_PORT__PxCMD__ASP__DFLT = 'h0;
1861 // RO: Aggressive Link Power Management Enable - not implemented
1862  localparam HBA_PORT__PxCMD__ALPE__ADDR = 'h46;
1863  localparam HBA_PORT__PxCMD__ALPE__MASK = 'h4000000;
1864  localparam HBA_PORT__PxCMD__ALPE__DFLT = 'h0;
1865 // RW: Drive LED on ATAPI enable
1866  localparam HBA_PORT__PxCMD__DLAE__ADDR = 'h46;
1867  localparam HBA_PORT__PxCMD__DLAE__MASK = 'h2000000;
1868  localparam HBA_PORT__PxCMD__DLAE__DFLT = 'h0;
1869 // RW: Device is ATAPI (for activity LED)
1870  localparam HBA_PORT__PxCMD__ATAPI__ADDR = 'h46;
1871  localparam HBA_PORT__PxCMD__ATAPI__MASK = 'h1000000;
1872  localparam HBA_PORT__PxCMD__ATAPI__DFLT = 'h0;
1873 // RW: Automatic Partial to Slumber Transitions Enabled
1874  localparam HBA_PORT__PxCMD__APSTE__ADDR = 'h46;
1875  localparam HBA_PORT__PxCMD__APSTE__MASK = 'h800000;
1876  localparam HBA_PORT__PxCMD__APSTE__DFLT = 'h0;
1877 // RO: FIS-Based Switching Capable Port - not implemented
1878  localparam HBA_PORT__PxCMD__FBSCP__ADDR = 'h46;
1879  localparam HBA_PORT__PxCMD__FBSCP__MASK = 'h400000;
1880  localparam HBA_PORT__PxCMD__FBSCP__DFLT = 'h0;
1881 // RO: External SATA port
1882  localparam HBA_PORT__PxCMD__ESP__ADDR = 'h46;
1883  localparam HBA_PORT__PxCMD__ESP__MASK = 'h200000;
1884  localparam HBA_PORT__PxCMD__ESP__DFLT = 'h200000;
1885 // RO: Cold Presence Detection
1886  localparam HBA_PORT__PxCMD__CPD__ADDR = 'h46;
1887  localparam HBA_PORT__PxCMD__CPD__MASK = 'h100000;
1888  localparam HBA_PORT__PxCMD__CPD__DFLT = 'h0;
1889 // RO: Mechanical Presence Switch Attached to Port
1890  localparam HBA_PORT__PxCMD__MPSP__ADDR = 'h46;
1891  localparam HBA_PORT__PxCMD__MPSP__MASK = 'h80000;
1892  localparam HBA_PORT__PxCMD__MPSP__DFLT = 'h0;
1893 // RO: Hot Plug Capable Port
1894  localparam HBA_PORT__PxCMD__HPCP__ADDR = 'h46;
1895  localparam HBA_PORT__PxCMD__HPCP__MASK = 'h40000;
1896  localparam HBA_PORT__PxCMD__HPCP__DFLT = 'h40000;
1897 // RW: Port Multiplier Attached - not implemented (software should write this bit)
1898  localparam HBA_PORT__PxCMD__PMA__ADDR = 'h46;
1899  localparam HBA_PORT__PxCMD__PMA__MASK = 'h20000;
1900  localparam HBA_PORT__PxCMD__PMA__DFLT = 'h0;
1901 // RO: Cold Presence State
1902  localparam HBA_PORT__PxCMD__CPS__ADDR = 'h46;
1903  localparam HBA_PORT__PxCMD__CPS__MASK = 'h10000;
1904  localparam HBA_PORT__PxCMD__CPS__DFLT = 'h0;
1905 // RO: Command List Running (section 5.3.2)
1906  localparam HBA_PORT__PxCMD__CR__ADDR = 'h46;
1907  localparam HBA_PORT__PxCMD__CR__MASK = 'h8000;
1908  localparam HBA_PORT__PxCMD__CR__DFLT = 'h0;
1909 // RO: FIS Receive Running (section 10.3.2)
1910  localparam HBA_PORT__PxCMD__FR__ADDR = 'h46;
1911  localparam HBA_PORT__PxCMD__FR__MASK = 'h4000;
1912  localparam HBA_PORT__PxCMD__FR__DFLT = 'h0;
1913 // RO: Mechanical Presence Switch State
1914  localparam HBA_PORT__PxCMD__MPSS__ADDR = 'h46;
1915  localparam HBA_PORT__PxCMD__MPSS__MASK = 'h2000;
1916  localparam HBA_PORT__PxCMD__MPSS__DFLT = 'h0;
1917 // RO: Current Command Slot (when PxCMD.ST 1-> ) should be reset to 0, when 0->1 - highest priority is 0
1918  localparam HBA_PORT__PxCMD__CCS__ADDR = 'h46;
1919  localparam HBA_PORT__PxCMD__CCS__MASK = 'h1f00;
1920  localparam HBA_PORT__PxCMD__CCS__DFLT = 'h0;
1921 // RW: FIS Receive Enable (enable after FIS memory is set)
1922  localparam HBA_PORT__PxCMD__FRE__ADDR = 'h46;
1923  localparam HBA_PORT__PxCMD__FRE__MASK = 'h10;
1924  localparam HBA_PORT__PxCMD__FRE__DFLT = 'h0;
1925 // RW1: Command List Override
1926  localparam HBA_PORT__PxCMD__CLO__ADDR = 'h46;
1927  localparam HBA_PORT__PxCMD__CLO__MASK = 'h8;
1928  localparam HBA_PORT__PxCMD__CLO__DFLT = 'h0;
1929 // RO: Power On Device (RW with Cold Presence Detection)
1930  localparam HBA_PORT__PxCMD__POD__ADDR = 'h46;
1931  localparam HBA_PORT__PxCMD__POD__MASK = 'h4;
1932  localparam HBA_PORT__PxCMD__POD__DFLT = 'h4;
1933 // RO: Spin-Up Device (RW with Staggered Spin-Up Support)
1934  localparam HBA_PORT__PxCMD__SUD__ADDR = 'h46;
1935  localparam HBA_PORT__PxCMD__SUD__MASK = 'h2;
1936  localparam HBA_PORT__PxCMD__SUD__DFLT = 'h2;
1937 // RW: Start (HBA may process commands). See section 10.3.1
1938  localparam HBA_PORT__PxCMD__ST__ADDR = 'h46;
1939  localparam HBA_PORT__PxCMD__ST__MASK = 'h1;
1940  localparam HBA_PORT__PxCMD__ST__DFLT = 'h0;
1941 // RO: Latest Copy of Task File Error Register
1942  localparam HBA_PORT__PxTFD__ERR__ADDR = 'h48;
1943  localparam HBA_PORT__PxTFD__ERR__MASK = 'hff00;
1944  localparam HBA_PORT__PxTFD__ERR__DFLT = 'h0;
1945 // RO: Latest Copy of Task File Status Register: BSY
1946  localparam HBA_PORT__PxTFD__STS__BSY__ADDR = 'h48;
1947  localparam HBA_PORT__PxTFD__STS__BSY__MASK = 'h80;
1948  localparam HBA_PORT__PxTFD__STS__BSY__DFLT = 'h0;
1949 // RO: Latest Copy of Task File Status Register: command-specific bits 4..6
1950  localparam HBA_PORT__PxTFD__STS__64__ADDR = 'h48;
1951  localparam HBA_PORT__PxTFD__STS__64__MASK = 'h70;
1952  localparam HBA_PORT__PxTFD__STS__64__DFLT = 'h0;
1953 // RO: Latest Copy of Task File Status Register: DRQ
1954  localparam HBA_PORT__PxTFD__STS__DRQ__ADDR = 'h48;
1955  localparam HBA_PORT__PxTFD__STS__DRQ__MASK = 'h8;
1956  localparam HBA_PORT__PxTFD__STS__DRQ__DFLT = 'h0;
1957 // RO: Latest Copy of Task File Status Register: command-specific bits 1..2
1958  localparam HBA_PORT__PxTFD__STS__12__ADDR = 'h48;
1959  localparam HBA_PORT__PxTFD__STS__12__MASK = 'h6;
1960  localparam HBA_PORT__PxTFD__STS__12__DFLT = 'h0;
1961 // RO: Latest Copy of Task File Status Register: ERR
1962  localparam HBA_PORT__PxTFD__STS__ERR__ADDR = 'h48;
1963  localparam HBA_PORT__PxTFD__STS__ERR__MASK = 'h1;
1964  localparam HBA_PORT__PxTFD__STS__ERR__DFLT = 'h0;
1965 // RO: Data in the first D2H Register FIS
1966  localparam HBA_PORT__PxSIG__SIG__ADDR = 'h49;
1967  localparam HBA_PORT__PxSIG__SIG__MASK = 'hffffffff;
1968  localparam HBA_PORT__PxSIG__SIG__DFLT = 'hffffffff;
1969 // RO: Interface Power Management
1970  localparam HBA_PORT__PxSSTS__IPM__ADDR = 'h4a;
1971  localparam HBA_PORT__PxSSTS__IPM__MASK = 'hf00;
1972  localparam HBA_PORT__PxSSTS__IPM__DFLT = 'h0;
1973 // RO: Interface Speed
1974  localparam HBA_PORT__PxSSTS__SPD__ADDR = 'h4a;
1975  localparam HBA_PORT__PxSSTS__SPD__MASK = 'hf0;
1976  localparam HBA_PORT__PxSSTS__SPD__DFLT = 'h0;
1977 // RO: Device Detection (should be detected if COMINIT is received)
1978  localparam HBA_PORT__PxSSTS__DET__ADDR = 'h4a;
1979  localparam HBA_PORT__PxSSTS__DET__MASK = 'hf;
1980  localparam HBA_PORT__PxSSTS__DET__DFLT = 'h0;
1981 // RO: Port Multiplier Port - not used by AHCI
1982  localparam HBA_PORT__PxSCTL__PMP__ADDR = 'h4b;
1983  localparam HBA_PORT__PxSCTL__PMP__MASK = 'hf0000;
1984  localparam HBA_PORT__PxSCTL__PMP__DFLT = 'h0;
1985 // RO: Select Power Management - not used by AHCI
1986  localparam HBA_PORT__PxSCTL__SPM__ADDR = 'h4b;
1987  localparam HBA_PORT__PxSCTL__SPM__MASK = 'hf000;
1988  localparam HBA_PORT__PxSCTL__SPM__DFLT = 'h0;
1989 // RW: Interface Power Management Transitions Allowed
1990  localparam HBA_PORT__PxSCTL__IPM__ADDR = 'h4b;
1991  localparam HBA_PORT__PxSCTL__IPM__MASK = 'hf00;
1992  localparam HBA_PORT__PxSCTL__IPM__DFLT = 'h0;
1993 // RW: Interface Highest Speed
1994  localparam HBA_PORT__PxSCTL__SPD__ADDR = 'h4b;
1995  localparam HBA_PORT__PxSCTL__SPD__MASK = 'hf0;
1996  localparam HBA_PORT__PxSCTL__SPD__DFLT = 'h0;
1997 // RW: Device Detection Initialization
1998  localparam HBA_PORT__PxSCTL__DET__ADDR = 'h4b;
1999  localparam HBA_PORT__PxSCTL__DET__MASK = 'hf;
2000  localparam HBA_PORT__PxSCTL__DET__DFLT = 'h0;
2001 // RWC: Exchanged (set on COMINIT), reflected in PxIS.PCS
2002  localparam HBA_PORT__PxSERR__DIAG__X__ADDR = 'h4c;
2003  localparam HBA_PORT__PxSERR__DIAG__X__MASK = 'h4000000;
2004  localparam HBA_PORT__PxSERR__DIAG__X__DFLT = 'h0;
2005 // RWC: Unknown FIS
2006  localparam HBA_PORT__PxSERR__DIAG__F__ADDR = 'h4c;
2007  localparam HBA_PORT__PxSERR__DIAG__F__MASK = 'h2000000;
2008  localparam HBA_PORT__PxSERR__DIAG__F__DFLT = 'h0;
2009 // RWC: Transport state transition error
2010  localparam HBA_PORT__PxSERR__DIAG__T__ADDR = 'h4c;
2011  localparam HBA_PORT__PxSERR__DIAG__T__MASK = 'h1000000;
2012  localparam HBA_PORT__PxSERR__DIAG__T__DFLT = 'h0;
2013 // RWC: Link sequence error
2014  localparam HBA_PORT__PxSERR__DIAG__S__ADDR = 'h4c;
2015  localparam HBA_PORT__PxSERR__DIAG__S__MASK = 'h800000;
2016  localparam HBA_PORT__PxSERR__DIAG__S__DFLT = 'h0;
2017 // RWC: Handshake Error (i.e. Device got CRC error)
2018  localparam HBA_PORT__PxSERR__DIAG__H__ADDR = 'h4c;
2019  localparam HBA_PORT__PxSERR__DIAG__H__MASK = 'h400000;
2020  localparam HBA_PORT__PxSERR__DIAG__H__DFLT = 'h0;
2021 // RWC: CRC error in Link layer
2022  localparam HBA_PORT__PxSERR__DIAG__C__ADDR = 'h4c;
2023  localparam HBA_PORT__PxSERR__DIAG__C__MASK = 'h200000;
2024  localparam HBA_PORT__PxSERR__DIAG__C__DFLT = 'h0;
2025 // RWC: Disparity Error - not used by AHCI
2026  localparam HBA_PORT__PxSERR__DIAG__D__ADDR = 'h4c;
2027  localparam HBA_PORT__PxSERR__DIAG__D__MASK = 'h100000;
2028  localparam HBA_PORT__PxSERR__DIAG__D__DFLT = 'h0;
2029 // RWC: 10B to 8B decode error
2030  localparam HBA_PORT__PxSERR__DIAG__B__ADDR = 'h4c;
2031  localparam HBA_PORT__PxSERR__DIAG__B__MASK = 'h80000;
2032  localparam HBA_PORT__PxSERR__DIAG__B__DFLT = 'h0;
2033 // RWC: COMMWAKE signal was detected
2034  localparam HBA_PORT__PxSERR__DIAG__W__ADDR = 'h4c;
2035  localparam HBA_PORT__PxSERR__DIAG__W__MASK = 'h40000;
2036  localparam HBA_PORT__PxSERR__DIAG__W__DFLT = 'h0;
2037 // RWC: PHY Internal Error
2038  localparam HBA_PORT__PxSERR__DIAG__I__ADDR = 'h4c;
2039  localparam HBA_PORT__PxSERR__DIAG__I__MASK = 'h20000;
2040  localparam HBA_PORT__PxSERR__DIAG__I__DFLT = 'h0;
2041 // RWC: PhyRdy changed. Reflected in PxIS.PRCS bit.
2042  localparam HBA_PORT__PxSERR__DIAG__N__ADDR = 'h4c;
2043  localparam HBA_PORT__PxSERR__DIAG__N__MASK = 'h10000;
2044  localparam HBA_PORT__PxSERR__DIAG__N__DFLT = 'h0;
2045 // RWC: Internal Error
2046  localparam HBA_PORT__PxSERR__ERR__E__ADDR = 'h4c;
2047  localparam HBA_PORT__PxSERR__ERR__E__MASK = 'h800;
2048  localparam HBA_PORT__PxSERR__ERR__E__DFLT = 'h0;
2049 // RWC: Protocol Error - a violation of SATA protocol detected
2050  localparam HBA_PORT__PxSERR__ERR__P__ADDR = 'h4c;
2051  localparam HBA_PORT__PxSERR__ERR__P__MASK = 'h400;
2052  localparam HBA_PORT__PxSERR__ERR__P__DFLT = 'h0;
2053 // RWC: Persistent Communication or Data Integrity Error
2054  localparam HBA_PORT__PxSERR__ERR__C__ADDR = 'h4c;
2055  localparam HBA_PORT__PxSERR__ERR__C__MASK = 'h200;
2056  localparam HBA_PORT__PxSERR__ERR__C__DFLT = 'h0;
2057 // RWC: Transient Data Integrity Error (error not recovered by the interface)
2058  localparam HBA_PORT__PxSERR__ERR__T__ADDR = 'h4c;
2059  localparam HBA_PORT__PxSERR__ERR__T__MASK = 'h100;
2060  localparam HBA_PORT__PxSERR__ERR__T__DFLT = 'h0;
2061 // RWC: Communication between the device and host was lost but re-established
2062  localparam HBA_PORT__PxSERR__ERR__M__ADDR = 'h4c;
2063  localparam HBA_PORT__PxSERR__ERR__M__MASK = 'h2;
2064  localparam HBA_PORT__PxSERR__ERR__M__DFLT = 'h0;
2065 // RWC: Recovered Data integrity Error
2066  localparam HBA_PORT__PxSERR__ERR__I__ADDR = 'h4c;
2067  localparam HBA_PORT__PxSERR__ERR__I__MASK = 'h1;
2068  localparam HBA_PORT__PxSERR__ERR__I__DFLT = 'h0;
2069 // RW1: Device Status: bit per Port, for TAG in native queued command
2070  localparam HBA_PORT__PxSACT__DS__ADDR = 'h4d;
2071  localparam HBA_PORT__PxSACT__DS__MASK = 'hffffffff;
2072  localparam HBA_PORT__PxSACT__DS__DFLT = 'h0;
2073 // RW1: Command Issued: bit per Port, only set when PxCMD.ST==1, also cleared by PxCMD.ST: 1->0 by soft
2074  localparam HBA_PORT__PxCI__CI__ADDR = 'h4e;
2075  localparam HBA_PORT__PxCI__CI__MASK = 'hffffffff;
2076  localparam HBA_PORT__PxCI__CI__DFLT = 'h0;
2077 // RWC: PM Notify (bit per PM port)
2078  localparam HBA_PORT__PxSNTF__PMN__ADDR = 'h4f;
2079  localparam HBA_PORT__PxSNTF__PMN__MASK = 'hffff;
2080  localparam HBA_PORT__PxSNTF__PMN__DFLT = 'h0;
2081 // RO: Device with Error
2082  localparam HBA_PORT__PxFBS__DWE__ADDR = 'h50;
2083  localparam HBA_PORT__PxFBS__DWE__MASK = 'hf0000;
2084  localparam HBA_PORT__PxFBS__DWE__DFLT = 'h0;
2085 // RO: Active Device Optimization
2086  localparam HBA_PORT__PxFBS__ADO__ADDR = 'h50;
2087  localparam HBA_PORT__PxFBS__ADO__MASK = 'hf000;
2088  localparam HBA_PORT__PxFBS__ADO__DFLT = 'h0;
2089 // RW: Device To Issue
2090  localparam HBA_PORT__PxFBS__DEV__ADDR = 'h50;
2091  localparam HBA_PORT__PxFBS__DEV__MASK = 'hf00;
2092  localparam HBA_PORT__PxFBS__DEV__DFLT = 'h0;
2093 // RO: Single Device Error
2094  localparam HBA_PORT__PxFBS__SDE__ADDR = 'h50;
2095  localparam HBA_PORT__PxFBS__SDE__MASK = 'h4;
2096  localparam HBA_PORT__PxFBS__SDE__DFLT = 'h0;
2097 // RW1: Device Error Clear
2098  localparam HBA_PORT__PxFBS__DEC__ADDR = 'h50;
2099  localparam HBA_PORT__PxFBS__DEC__MASK = 'h2;
2100  localparam HBA_PORT__PxFBS__DEC__DFLT = 'h0;
2101 // RW: Enable
2102  localparam HBA_PORT__PxFBS__EN__ADDR = 'h50;
2103  localparam HBA_PORT__PxFBS__EN__MASK = 'h1;
2104  localparam HBA_PORT__PxFBS__EN__DFLT = 'h0;
2105 // RO: DITO Multiplier
2106  localparam HBA_PORT__PxDEVSLP__DM__ADDR = 'h51;
2107  localparam HBA_PORT__PxDEVSLP__DM__MASK = 'h1e000000;
2108  localparam HBA_PORT__PxDEVSLP__DM__DFLT = 'h0;
2109 // RW: Device Sleep Idle Timeout (section 8.5.1.1.1)
2110  localparam HBA_PORT__PxDEVSLP__DITO__ADDR = 'h51;
2111  localparam HBA_PORT__PxDEVSLP__DITO__MASK = 'h1ff8000;
2112  localparam HBA_PORT__PxDEVSLP__DITO__DFLT = 'h0;
2113 // RW: Minimum Device Sleep Assertion Time
2114  localparam HBA_PORT__PxDEVSLP__MDAT__ADDR = 'h51;
2115  localparam HBA_PORT__PxDEVSLP__MDAT__MASK = 'h7c00;
2116  localparam HBA_PORT__PxDEVSLP__MDAT__DFLT = 'h0;
2117 // RW: Device Sleep Exit Timeout
2118  localparam HBA_PORT__PxDEVSLP__DETO__ADDR = 'h51;
2119  localparam HBA_PORT__PxDEVSLP__DETO__MASK = 'h3fc;
2120  localparam HBA_PORT__PxDEVSLP__DETO__DFLT = 'h0;
2121 // RO: Device Sleep Present
2122  localparam HBA_PORT__PxDEVSLP__DSP__ADDR = 'h51;
2123  localparam HBA_PORT__PxDEVSLP__DSP__MASK = 'h2;
2124  localparam HBA_PORT__PxDEVSLP__DSP__DFLT = 'h0;
2125 // RO: Aggressive Device Sleep Enable
2126  localparam HBA_PORT__PxDEVSLP__ADSE__ADDR = 'h51;
2127  localparam HBA_PORT__PxDEVSLP__ADSE__MASK = 'h1;
2128  localparam HBA_PORT__PxDEVSLP__ADSE__DFLT = 'h0;
2129 // RW: SAXIHP write channel cache mode
2130  localparam HBA_PORT__AFI_CACHE__WR_CM__ADDR = 'h5c;
2131  localparam HBA_PORT__AFI_CACHE__WR_CM__MASK = 'hf0;
2132  localparam HBA_PORT__AFI_CACHE__WR_CM__DFLT = 'h30;
2133 // RW: SAXIHP read channel cache mode
2134  localparam HBA_PORT__AFI_CACHE__RD_CM__ADDR = 'h5c;
2135  localparam HBA_PORT__AFI_CACHE__RD_CM__MASK = 'hf;
2136  localparam HBA_PORT__AFI_CACHE__RD_CM__DFLT = 'h3;
2137 // RW: Address/not data for programming AHCI state machine
2138  localparam HBA_PORT__PGM_AHCI_SM__AnD__ADDR = 'h5d;
2139  localparam HBA_PORT__PGM_AHCI_SM__AnD__MASK = 'h1000000;
2140  localparam HBA_PORT__PGM_AHCI_SM__AnD__DFLT = 'h0;
2141 // RW: Program address/data for programming AHCI state machine
2142  localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d;
2143  localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff;
2144  localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h0;
2145 // RW: 3-bit tag to add to the recorded timestamp
2146  localparam HBA_PORT__PunchTime__TAG__ADDR = 'h5e;
2147  localparam HBA_PORT__PunchTime__TAG__MASK = 'h7;
2148  localparam HBA_PORT__PunchTime__TAG__DFLT = 'h0;
2149 
2150 
2151  reg [2:0] punch_tag;
2152  wire write_tag_w = soft_write_en && (soft_write_addr[ADDRESS_BITS-1:0] == HBA_PORT__PunchTime__TAG__ADDR);
2153  reg pend_punch_time;
2154  wire write_punch_time = pend_punch_time && !fis_start && !fis_run && !fis_run_d;
2155  reg fis_run;
2156  reg fis_run_d;
2157  reg fis_we; // recording FIS data (until end or max len)
2158  reg [12:0] fis_len;
2159  reg [12:0] fis_left;
2160  reg [31:0] fis_data;
2161  reg [27:0] cur_time;
2162  reg was_h2d_last;
2163 
2164  wire fis_start = (h2d_valid && h2d_ready && (h2d_type == 1)) ||
2165  (d2h_valid && d2h_ready && (d2h_type == 1));
2166  wire fis_end = (d2h_valid? (d2h_valid && d2h_ready && d2h_type[1]): was_h2d_last);
2167 // wire fis_end_we = (fis_left == 0) || fis_end;
2168 
2169  wire pre_we_w = fis_run && (d2h_valid?(d2h_valid && d2h_ready):(h2d_valid && h2d_ready));
2170  reg pre_we_r;
2171  reg we_r;
2172  assign datascope_we = we_r;
2173  assign datascope_clk = clk;
2174 
2175  always @ (posedge clk) begin
2176  was_h2d_last <= h2d_type[1] && h2d_valid && h2d_ready;
2177 
2178  if (rst) cur_time <= 0;
2179  else cur_time <= cur_time + 1;
2180 
2181  if (write_tag_w) punch_tag <= soft_write_data[2:0];
2182 
2183  if (rst) pend_punch_time <= 0;
2184  else if (write_tag_w) pend_punch_time <= 1;
2185  else if (write_punch_time) pend_punch_time <= 0;
2186 
2187  if (write_punch_time || fis_start) datascope_di <= {write_punch_time?{1'b1,punch_tag}:{3'b0,d2h_valid},cur_time};
2188  else if (fis_we) datascope_di <= fis_data;
2189  else if (!fis_run && fis_run_d) datascope_di <= {19'h7fff8, fis_len};
2190 
2191  pre_we_r <= pre_we_w || fis_start ;
2192 
2193  we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
2194 
2195  if (fis_start) fis_left <= FIS_LEN - 1;
2196  else if (pre_we_w) fis_left <= fis_left - 1;
2197 
2198  if (rst) fis_we <= 0;
2199  else if (fis_start) fis_we <= 1;
2200  else if ((fis_left == 0) || fis_end) fis_we <= 0;
2201 
2202  if (rst) fis_run <= 0;
2203  else if (fis_start) fis_run <= 1;
2204  else if (fis_end) fis_run <= 0;
2205 
2206  fis_run_d <= fis_run;
2207 
2208  if (fis_start) fis_len <= d2h_valid? 0 : 1;
2209  else if (pre_we_w) fis_len <= fis_len + 1;
2210 
2211  if (fis_start || pre_we_w) fis_data <= d2h_valid ? d2h_data : h2d_data;
2212 
2213  if (rst) datascope_waddr <= 0;
2214  else if (we_r) datascope_waddr <= datascope_waddr + 1;
2215 
2216  end
2217 
2218 endmodule
2219 
2220 
ahci_fis_receive.13224hba_data_in_ready
13224hba_data_in_ready
Definition: ahci_fis_receive.v:120
ahci_top.13720bresp
[ 1:0] 13720bresp
Definition: ahci_top.v:69
ahci_top.13730rready
13730rready
Definition: ahci_top.v:81
ahci_fis_receive.13189update_err_sts
13189update_err_sts
Definition: ahci_fis_receive.v:68
ahci_fis_receive.13174get_sdbfis
13174get_sdbfis
Definition: ahci_fis_receive.v:52
axi_ahci_regs.14041awready
14041awready
Definition: axi_ahci_regs.v:57
ahci_dma.12893afi_rready
12893afi_rready
Definition: ahci_dma.v:144
axi_ahci_regs.14068rresp
[ 1:0] 14068rresp
Definition: axi_ahci_regs.v:88
ahci_top.13965ssts_spd_gen2
13965ssts_spd_gen2wire
Definition: ahci_top.v:467
ahci_top.13945sirq_TFE
13945sirq_TFEwire
Definition: ahci_top.v:439
ahci_top.13719bid
[11:0] 13719bid
Definition: ahci_top.v:68
ahci_fis_receive.13205tfd_err
[7:0] 13205tfd_err
Definition: ahci_fis_receive.v:94
ahci_fis_receive.13216data_in_dwords
[11:0] 13216data_in_dwords
Definition: ahci_fis_receive.v:106
ahci_top.13888frcv_get_ufis
13888frcv_get_ufiswire
Definition: ahci_top.v:322
ahci_fsm.13414pfsm_started
13414pfsm_started
Definition: ahci_fsm.v:64
ahci_top.13887frcv_get_sdbfis
13887frcv_get_sdbfiswire
Definition: ahci_top.v:321
ahci_fis_transmit.13316ch_prdtl
[15:0] 13316ch_prdtl
Definition: ahci_fis_transmit.v:63
ahci_dma.12827prdtl
[15:0] 12827prdtl
Definition: ahci_dma.v:53
axi_ahci_regs.14084pgm_wd
reg 14084pgm_wd
Definition: axi_ahci_regs.v:113
ahci_dma.12838ct_re
[ 1:0] 12838ct_re
Definition: ahci_dma.v:71
ahci_top.13988DATA_TYPE_DMA
13988DATA_TYPE_DMA0
Definition: ahci_top.v:695
ahci_top.13846regs_re
13846regs_rewire[1:0]
Definition: ahci_top.v:246
ahci_top.13969ssts_det_dp
13969ssts_det_dpwire
Definition: ahci_top.v:472
ahci_ctrl_stat.12722serr_DS
12722serr_DS
Definition: ahci_ctrl_stat.v:101
ahci_top.13982debug_dma_h2d
13982debug_dma_h2dwire[31:0]
Definition: ahci_top.v:491
ahci_fsm.13402arst
13402arst
Definition: ahci_fsm.v:43
ahci_dma.12826ctba_ld
12826ctba_ld
Definition: ahci_dma.v:52
ahci_top.13842regs_raddr
13842regs_raddrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:241
ahci_fis_transmit.13315dx_err
[ 2:0] 13315dx_err
Definition: ahci_fis_transmit.v:61
ahci_fis_receive.13168fis_first_vld
reg 13168fis_first_vld
Definition: ahci_fis_receive.v:44
ahci_top.13703hrst
13703hrst
Definition: ahci_top.v:48
ahci_top.13701port_arst_any
13701port_arst_any
Definition: ahci_top.v:46
ahci_top.13876dma_re
13876dma_rewire
Definition: ahci_top.v:302
ahci_top.13840regs_saddr
13840regs_saddrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:239
ahci_fis_receive.13226dma_in_valid
13226dma_in_valid
Definition: ahci_fis_receive.v:124
ahci_top.13874dma_dout
13874dma_doutwire[31:0]
Definition: ahci_top.v:300
ahci_fis_receive.13225dma_in_ready
13225dma_in_ready
Definition: ahci_fis_receive.v:123
axi_ahci_regs.14098drp_rdy
14098drp_rdy
Definition: axi_ahci_regs.v:132
ahci_fis_transmit.13324dwords_sent
reg [11:0] 13324dwords_sent
Definition: ahci_fis_transmit.v:72
ahci_top.13753afi_bid
[ 5:0] 13753afi_bid
Definition: ahci_top.v:109
ahci_top.13782d2h_data
[31:0] 13782d2h_data
Definition: ahci_top.v:147
ahci_top.13910tfd_sts
13910tfd_stswire[7:0]
Definition: ahci_top.v:356
ahci_fsm.13435ssts_ipm_dnp
13435ssts_ipm_dnp
Definition: ahci_fsm.v:118
ahci_dma.12900debug_out
[31:0] 12900debug_out
Definition: ahci_dma.v:153
axi_ahci_regs.14040awvalid
14040awvalid
Definition: axi_ahci_regs.v:56
ahci_dma.12886afi_arprot
[ 2:0] 12886afi_arprot
Definition: ahci_dma.v:136
ahci_dma.12840prd_done
12840prd_done
Definition: ahci_dma.v:76
ahci_fis_receive.13198clear_xfer_cntr
13198clear_xfer_cntr
Definition: ahci_fis_receive.v:78
ahci_fis_receive.13211pio_d
reg 13211pio_d
Definition: ahci_fis_receive.v:100
ahci_dma.12888afi_arsize
[ 1:0] 12888afi_arsize
Definition: ahci_dma.v:138
datascope_timing.14025fis_left
14025fis_leftreg[12:0]
Definition: ahci_top.v:1260
ahci_top.13696arst
13696arst
Definition: ahci_top.v:40
ahci_fsm.13399was_hba_rst
13399was_hba_rst
Definition: ahci_fsm.v:38
ahci_ctrl_stat.12726serr_DW
12726serr_DW
Definition: ahci_ctrl_stat.v:105
ahci_top.13898frcv_set_sts_80
13898frcv_set_sts_80wire
Definition: ahci_top.v:336
ahci_fis_receive.13194clear_bsy_set_drq
13194clear_bsy_set_drq
Definition: ahci_fis_receive.v:73
ahci_top.axi_ahci_regs
axi_ahci_regs_i axi_ahci_regs
Definition: ahci_top.v:717
ahci_fis_receive.13230debug_get_fis_busy_r
[1:0] 13230debug_get_fis_busy_r
Definition: ahci_fis_receive.v:129
ahci_ctrl_stat.12723serr_DH
12723serr_DH
Definition: ahci_ctrl_stat.v:102
datascope_timing.14003soft_write_data
[31:0] 14003soft_write_data
Definition: ahci_top.v:1228
ahci_fis_transmit.13326reg_re
[ 1:0] 13326reg_re
Definition: ahci_fis_transmit.v:76
ahci_fsm.13453pxci0_clear
13453pxci0_clear
Definition: ahci_fsm.v:144
ahci_top.13754afi_bresp
[ 1:0] 13754afi_bresp
Definition: ahci_top.v:110
ahci_dma.12901debug_out1
[31:0] 12901debug_out1
Definition: ahci_dma.v:154
ahci_ctrl_stat.12694update_pcmd
12694update_pcmd
Definition: ahci_ctrl_stat.v:59
ahci_dma.12889afi_arburst
[ 1:0] 12889afi_arburst
Definition: ahci_dma.v:139
ahci_top.13697mclk
13697mclk
Definition: ahci_top.v:41
ahci_top.13976pxci0
13976pxci0wire
Definition: ahci_top.v:482
ahci_fis_transmit.13330dma_ctba_ld
13330dma_ctba_ld
Definition: ahci_fis_transmit.v:84
ahci_dma.12877afi_wcount
[ 7:0] 12877afi_wcount
Definition: ahci_dma.v:125
ahci_ctrl_stat.12711sirq_INF
12711sirq_INF
Definition: ahci_ctrl_stat.v:87
ahci_top.13987debug_get_fis_busy_r
13987debug_get_fis_busy_rwire[1:0]
Definition: ahci_top.v:692
ahci_top.ahci_dma
ahci_dma_i ahci_dma
Definition: ahci_top.v:912
ahci_dma.12856afi_awaddr
[31:0] 12856afi_awaddr
Definition: ahci_dma.v:101
ahci_top.13845en_port
13845en_portreg
Definition: ahci_top.v:245
ahci_ctrl_stat.12716sirq_UF
12716sirq_UF
Definition: ahci_ctrl_stat.v:92
ahci_top.13905frcv_err
13905frcv_errwire
Definition: ahci_top.v:345
ahci_top.13724arid
[11:0] 13724arid
Definition: ahci_top.v:74
ahci_top.13878dma_in_ready
13878dma_in_readywire
Definition: ahci_top.v:305
ahci_top.13852dev_wr
13852dev_wrwire
Definition: ahci_top.v:271
ahci_top.13942pcmd_clo
13942pcmd_clowire
Definition: ahci_top.v:433
ahci_top.13784d2h_valid
13784d2h_valid
Definition: ahci_top.v:149
ahci_top.13961ssts_ipm_slumb
13961ssts_ipm_slumbwire
Definition: ahci_top.v:462
ahci_fis_receive.13175get_ufis
13175get_ufis
Definition: ahci_fis_receive.v:53
ahci_fis_transmit.13319ch_r
13319ch_r
Definition: ahci_fis_transmit.v:66
ahci_top.13863dma_ct_busy
13863dma_ct_busywire
Definition: ahci_top.v:286
ahci_top.13865dma_ct_re
13865dma_ct_rewire[1:0]
Definition: ahci_top.v:288
ahci_top.13847regs_we
13847regs_wewire
Definition: ahci_top.v:247
datascope_timing.13999FIS_LEN
13999FIS_LEN5
Definition: ahci_top.v:1222
ahci_dma.12881afi_arvalid
12881afi_arvalid
Definition: ahci_dma.v:131
ahci_top.13700port_arst
13700port_arst
Definition: ahci_top.v:45
ahci_fis_transmit.13322ch_a
13322ch_a
Definition: ahci_fis_transmit.v:69
ahci_fsm.13451sctl_det_reset
13451sctl_det_reset
Definition: ahci_fsm.v:140
ahci_top.13861axi_rd_cache_mode
13861axi_rd_cache_modewire[3:0]
Definition: ahci_top.v:284
ahci_top.13775afi_rcount
[ 7:0] 13775afi_rcount
Definition: ahci_top.v:136
ahci_top.13750afi_wstrb
[ 7:0] 13750afi_wstrb
Definition: ahci_top.v:105
ahci_ctrl_stat.12681soft_write_addr
[ADDRESS_BITS-1:0] 12681soft_write_addr
Definition: ahci_ctrl_stat.v:39
ahci_top.13913pio_i
13913pio_iwire
Definition: ahci_top.v:363
ahci_top.13715wlast
13715wlast
Definition: ahci_top.v:63
axi_ahci_regs.14062arburst
[ 1:0] 14062arburst
Definition: axi_ahci_regs.v:81
ahci_top.13960ssts_ipm_part
13960ssts_ipm_partwire
Definition: ahci_top.v:461
ahci_top.13822drp_addr
[14:0] 13822drp_addr
Definition: ahci_top.v:206
ahci_fis_transmit.13347debug_01
[9:0] 13347debug_01
Definition: ahci_fis_transmit.v:109
ahci_dma.12825ctba
[31:4] 12825ctba
Definition: ahci_dma.v:51
ahci_top.13907frcv_extra
13907frcv_extrawire
Definition: ahci_top.v:347
axi_ahci_regs.14096drp_addr
reg [14:0] 14096drp_addr
Definition: axi_ahci_regs.v:130
ahci_fsm.13412send_R_OK
13412send_R_OK
Definition: ahci_fsm.v:57
axi_ahci_regs.14104datascope1_clk
14104datascope1_clk
Definition: axi_ahci_regs.v:142
datascope_timing.14033we_r
14033we_rreg
Definition: ahci_top.v:1272
ahci_top.13932data_out_dwords
13932data_out_dwordswire[11:0]
Definition: ahci_top.v:399
ahci_ctrl_stat.12750sctl_spd
reg [3:0] 12750sctl_spd
Definition: ahci_ctrl_stat.v:138
ahci_fsm.13508ch_r
13508ch_r
Definition: ahci_fsm.v:240
axi_ahci_regs.14048wready
14048wready
Definition: axi_ahci_regs.v:65
ahci_top.13981debug_dma1
13981debug_dma1wire[31:0]
Definition: ahci_top.v:490
ahci_ctrl_stat.12736ssts_ipm_active
12736ssts_ipm_active
Definition: ahci_ctrl_stat.v:120
ahci_top.13974sctl_det_reset
13974sctl_det_resetwire
Definition: ahci_top.v:479
ahci_dma.12850sys_re
12850sys_re
Definition: ahci_dma.v:89
ahci_dma.12854sys_we
12854sys_we
Definition: ahci_dma.v:95
ahci_top.13926fsnd_ch_c
13926fsnd_ch_cwire
Definition: ahci_top.v:391
ahci_fsm.13492tfd_sts
[7:0] 13492tfd_sts
Definition: ahci_fsm.v:204
ahci_top.13812serr_EI
13812serr_EI
Definition: ahci_top.v:185
datascope_timing.14000clk
14000clk
Definition: ahci_top.v:1224
ahci_fis_receive.13167pcmd_st_cleared
13167pcmd_st_cleared
Definition: ahci_fis_receive.v:42
ahci_top.13727arburst
[ 1:0] 13727arburst
Definition: ahci_top.v:77
ahci_fsm.13441ssts_spd_gen1
13441ssts_spd_gen1
Definition: ahci_fsm.v:125
ahci_fsm.13447ssts_det_offline
13447ssts_det_offline
Definition: ahci_fsm.v:132
ahci_dma.12875afi_bid
[ 5:0] 12875afi_bid
Definition: ahci_dma.v:122
ahci_top.13818datascope1_we
13818datascope1_we
Definition: ahci_top.v:198
ahci_top.13853dma_cmd_start
13853dma_cmd_startwire
Definition: ahci_top.v:272
ahci_dma.12835set_axi_rd_cache_mode
12835set_axi_rd_cache_mode
Definition: ahci_dma.v:64
ahci_top.13833soft_write_addr
13833soft_write_addrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:227
axi_ahci_regs.14093debug_in3
[31:0] 14093debug_in3
Definition: axi_ahci_regs.v:126
ahci_top.13834soft_write_data
13834soft_write_datawire[31:0]
Definition: ahci_top.v:228
ahci_fis_receive.13202pcmd_fre
13202pcmd_fre
Definition: ahci_fis_receive.v:83
ahci_top.13884frcv_get_dsfis
13884frcv_get_dsfiswire
Definition: ahci_top.v:318
ahci_top.13921fsnd_atapi_xmit
13921fsnd_atapi_xmitwire
Definition: ahci_top.v:382
ahci_top.13815irq
13815irq
Definition: ahci_top.v:192
ahci_top.13791pcmd_st_cleared
13791pcmd_st_cleared
Definition: ahci_top.v:159
ahci_top.13856dma_cmd_abort_fsm
13856dma_cmd_abort_fsmwire
Definition: ahci_top.v:275
ahci_top.13908frcv_set_update_sig
13908frcv_set_update_sigwire
Definition: ahci_top.v:349
ahci_ctrl_stat.12679was_hba_rst
12679was_hba_rst
Definition: ahci_ctrl_stat.v:35
ahci_dma.12862afi_awprot
[ 2:0] 12862afi_awprot
Definition: ahci_dma.v:107
ahci_top.13814sctl_spd
[3:0] 13814sctl_spd
Definition: ahci_top.v:188
ahci_fis_transmit.13308busy
reg 13308busy
Definition: ahci_fis_transmit.v:49
ahci_top.13709awsize
[ 1:0] 13709awsize
Definition: ahci_top.v:56
ahci_fsm.13457dma_cmd_busy
13457dma_cmd_busy
Definition: ahci_fsm.v:151
ahci_fis_transmit.13310pCmdToIssue
13310pCmdToIssue
Definition: ahci_fis_transmit.v:52
ahci_fis_transmit.13334dma_prd_start
reg 13334dma_prd_start
Definition: ahci_fis_transmit.v:89
ahci_top.13958ssts_ipm_dnp
13958ssts_ipm_dnpwire
Definition: ahci_top.v:459
ahci_top.13707awid
[11:0] 13707awid
Definition: ahci_top.v:54
ahci_fsm.13471get_ignore
13471get_ignore
Definition: ahci_fsm.v:172
ahci_top.13760afi_arready
13760afi_arready
Definition: ahci_top.v:119
ahci_dma.12884afi_arlock
[ 1:0] 12884afi_arlock
Definition: ahci_dma.v:134
ahci_dma.12874afi_bready
12874afi_bready
Definition: ahci_dma.v:121
ahci_top.13711wdata
[31:0] 13711wdata
Definition: ahci_top.v:59
ahci_fis_transmit.13337ct_re
[ 1:0] 13337ct_re
Definition: ahci_fis_transmit.v:94
axi_ahci_regs.14069soft_write_addr
[ADDRESS_BITS-1:0] 14069soft_write_addr
Definition: axi_ahci_regs.v:92
axi_ahci_regs.14078hba_we
14078hba_we
Definition: axi_ahci_regs.v:104
ahci_top.13825drp_do
[15:0] 13825drp_do
Definition: ahci_top.v:209
ahci_ctrl_stat.12693update_serr
12693update_serr
Definition: ahci_ctrl_stat.v:58
axi_ahci_regs.14097drp_di
reg [15:0] 14097drp_di
Definition: axi_ahci_regs.v:131
ahci_top.13885frcv_get_psfis
13885frcv_get_psfiswire
Definition: ahci_top.v:319
axi_ahci_regs.14075hba_clk
14075hba_clk
Definition: axi_ahci_regs.v:101
ahci_top.13930fsnd_ch_w
13930fsnd_ch_wwire
Definition: ahci_top.v:395
ahci_top.13695aclk
13695aclk
Definition: ahci_top.v:39
ahci_fis_receive.13188update_sig
13188update_sig
Definition: ahci_fis_receive.v:67
ahci_top.13915pPioXfer
13915pPioXferwire
Definition: ahci_top.v:366
ahci_fis_transmit.13343todev_data
reg [31:0] 13343todev_data
Definition: ahci_fis_transmit.v:104
ahci_fsm.13473fis_ok
13473fis_ok
Definition: ahci_fsm.v:175
ahci_top.13919fsnd_cfis_xmit
13919fsnd_cfis_xmitwire
Definition: ahci_top.v:379
ahci_fis_transmit.13317ch_c
13317ch_c
Definition: ahci_fis_transmit.v:64
axi_ahci_regs.14102datascope_we
14102datascope_we
Definition: axi_ahci_regs.v:139
ahci_fsm.13479update_err_sts
13479update_err_sts
Definition: ahci_fsm.v:187
ahci_top.13787phy_ready
[ 1:0] 13787phy_ready
Definition: ahci_top.v:155
ahci_ctrl_stat.12728serr_EE
12728serr_EE
Definition: ahci_ctrl_stat.v:109
axi_ahci_regs.14074port_arst_any
14074port_arst_any
Definition: axi_ahci_regs.v:98
datascope_timing.14006h2d_type
[ 1:0] 14006h2d_type
Definition: ahci_top.v:1233
ahci_ctrl_stat.12743ssts_spd_gen3
12743ssts_spd_gen3
Definition: ahci_ctrl_stat.v:128
ahci_fis_receive.13192clear_prdbc
13192clear_prdbc
Definition: ahci_fis_receive.v:71
ahci_dma.12896afi_rresp
[ 1:0] 12896afi_rresp
Definition: ahci_dma.v:147
axi_ahci_regs.14105datascope1_waddr
[ADDRESS_BITS-1:0] 14105datascope1_waddr
Definition: axi_ahci_regs.v:143
ahci_fsm.13461fis_first_flush
13461fis_first_flush
Definition: ahci_fsm.v:159
ahci_top.13900frcv_decr_dwcw
13900frcv_decr_dwcwwire
Definition: ahci_top.v:338
ahci_fis_transmit.13307done
reg 13307done
Definition: ahci_fis_transmit.v:48
ahci_fis_receive.13204tfd_sts
[7:0] 13204tfd_sts
Definition: ahci_fis_receive.v:92
ahci_top.13752afi_bready
13752afi_bready
Definition: ahci_top.v:108
ahci_dma.12887afi_arlen
[ 3:0] 12887afi_arlen
Definition: ahci_dma.v:137
ahci_top.13758afi_araddr
[31:0] 13758afi_araddr
Definition: ahci_top.v:117
ahci_dma.12846abort_done
12846abort_done
Definition: ahci_dma.v:82
ahci_top.13848regs_addr
13848regs_addrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:250
ahci_top.13780h2d_valid
13780h2d_valid
Definition: ahci_top.v:143
ahci_fsm.13480update_pio
13480update_pio
Definition: ahci_fsm.v:188
ahci_dma.12865afi_awburst
[ 1:0] 12865afi_awburst
Definition: ahci_dma.v:110
ahci_fis_receive.13180fis_ok
reg 13180fis_ok
Definition: ahci_fis_receive.v:58
axi_ahci_regs.14090debug_in0
[31:0] 14090debug_in0
Definition: axi_ahci_regs.v:123
ahci_top.13911fis_i
13911fis_iwire
Definition: ahci_top.v:359
ahci_top.13785d2h_many
13785d2h_many
Definition: ahci_top.v:150
ahci_top.13962ssts_ipm_devsleep
13962ssts_ipm_devsleepwire
Definition: ahci_top.v:463
ahci_ctrl_stat.12682soft_write_data
[31:0] 12682soft_write_data
Definition: ahci_ctrl_stat.v:40
ahci_top.13778h2d_data
[31:0] 13778h2d_data
Definition: ahci_top.v:141
ahci_fsm.13463fis_type
[7:0] 13463fis_type
Definition: ahci_fsm.v:162
ahci_ctrl_stat.12717sirq_SDB
12717sirq_SDB
Definition: ahci_ctrl_stat.v:93
ahci_dma.12898afi_racount
[ 2:0] 12898afi_racount
Definition: ahci_dma.v:150
axi_ahci_regs.14085afi_wcache
reg [ 3:0] 14085afi_wcache
Definition: axi_ahci_regs.v:118
ahci_dma.12868afi_wvalid
12868afi_wvalid
Definition: ahci_dma.v:114
ahci_top.13698mrst
13698mrst
Definition: ahci_top.v:42
ahci_fis_transmit.13342last_h2d_data
13342last_h2d_data
Definition: ahci_fis_transmit.v:101
ahci_top.13713wready
13713wready
Definition: ahci_top.v:61
ahci_top.ahci_fsm
ahci_fsm_i ahci_fsm
Definition: ahci_top.v:519
ahci_ctrl_stat.12698pcmd_cr
12698pcmd_cr
Definition: ahci_ctrl_stat.v:70
ahci_top.13978comreset_send0
13978comreset_send0wire
Definition: ahci_top.v:485
ahci_top.13879dma_we
13879dma_wewire
Definition: ahci_top.v:306
ahci_ctrl_stat.12756hba_reset_done
12756hba_reset_done
Definition: ahci_ctrl_stat.v:146
ahci_dma.12859afi_awid
[ 5:0] 12859afi_awid
Definition: ahci_dma.v:104
ahci_fsm.13403pgm_ad
[17:0] 13403pgm_ad
Definition: ahci_fsm.v:44
ahci_fis_transmit.13301mclk
13301mclk
Definition: ahci_fis_transmit.v:37
ahci_top.13967ssts_det_ndnp
13967ssts_det_ndnpwire
Definition: ahci_top.v:470
ahci_top.13744afi_awqos
[ 3:0] 13744afi_awqos
Definition: ahci_top.v:98
ahci_top.13748afi_wid
[ 5:0] 13748afi_wid
Definition: ahci_top.v:103
ahci_top.13869dma_cmd_busy
13869dma_cmd_busywire
Definition: ahci_top.v:293
ahci_top.13986debug_fis_end_r
13986debug_fis_end_rwire[1:0]
Definition: ahci_top.v:691
datascope_timing.14008h2d_ready
14008h2d_ready
Definition: ahci_top.v:1235
ahci_fsm.13408syncesc_send_done
13408syncesc_send_done
Definition: ahci_fsm.v:52
axi_ahci_regs.14089was_port_rst
14089was_port_rst
Definition: axi_ahci_regs.v:122
ahci_fis_transmit.13329xfer_cntr_zero
13329xfer_cntr_zero
Definition: ahci_fis_transmit.v:81
datascope_timing.14010d2h_type
[ 1:0] 14010d2h_type
Definition: ahci_top.v:1241
axi_ahci_regs.14099drp_do
[15:0] 14099drp_do
Definition: axi_ahci_regs.v:133
ahci_top.13927fsnd_ch_b
13927fsnd_ch_bwire
Definition: ahci_top.v:392
ahci_fis_transmit.13325reg_addr
reg [ADDRESS_BITS-1:0] 13325reg_addr
Definition: ahci_fis_transmit.v:75
ahci_fsm.13507ch_b
13507ch_b
Definition: ahci_fsm.v:239
ahci_dma.12864afi_awsize
[ 1:0] 12864afi_awsize
Definition: ahci_dma.v:109
ahci_fsm.13478update_sig
13478update_sig
Definition: ahci_fsm.v:183
ahci_dma.12902debug_dma_h2d
[31:0] 12902debug_dma_h2d
Definition: ahci_dma.v:156
ahci_top.13798send_R_OK
13798send_R_OK
Definition: ahci_top.v:167
datascope_timing.14022fis_run_d
14022fis_run_dreg
Definition: ahci_top.v:1257
ahci_top.13940pcmd_fre0
13940pcmd_fre0wire
Definition: ahci_top.v:430
ahci_fis_receive.13179get_fis_done
reg 13179get_fis_done
Definition: ahci_fis_receive.v:57
ahci_top.13917xfer_cntr_zero
13917xfer_cntr_zerowire
Definition: ahci_top.v:371
ahci_fis_transmit.13305dx_xmit
13305dx_xmit
Definition: ahci_fis_transmit.v:43
ahci_dma.12880afi_araddr
[31:0] 12880afi_araddr
Definition: ahci_dma.v:130
ahci_fsm.13485set_sts_7f
13485set_sts_7f
Definition: ahci_fsm.v:195
ahci_top.13790syncesc_recv
13790syncesc_recv
Definition: ahci_top.v:158
ahci_fis_transmit.13311xmit_ok
13311xmit_ok
Definition: ahci_fis_transmit.v:57
ahci_top.13970ssts_det_offline
13970ssts_det_offlinewire
Definition: ahci_top.v:473
ahci_top
Definition: ahci_top.v:28
ahci_fsm.13491pPioXfer
13491pPioXfer
Definition: ahci_fsm.v:203
datascope_timing.14028was_h2d_last
14028was_h2d_lastreg
Definition: ahci_top.v:1263
ahci_top.13737afi_awid
[ 5:0] 13737afi_awid
Definition: ahci_top.v:91
ahci_top.13867dma_prd_irq_clear
13867dma_prd_irq_clearwire
Definition: ahci_top.v:291
ahci_ctrl_stat.12751sctl_det
reg [3:0] 12751sctl_det
Definition: ahci_ctrl_stat.v:139
ahci_fsm.13452hba_rst_done
13452hba_rst_done
Definition: ahci_fsm.v:142
ahci_top.13858fsm_pgm_wa
13858fsm_pgm_wawire
Definition: ahci_top.v:279
ahci_top.13920fsnd_dx_xmit
13920fsnd_dx_xmitwire
Definition: ahci_top.v:380
ahci_fis_receive.13176get_data_fis
13176get_data_fis
Definition: ahci_fis_receive.v:54
ahci_ctrl_stat.12753sctl_det_reset
12753sctl_det_reset
Definition: ahci_ctrl_stat.v:141
ahci_fsm.13445ssts_det_dnp
13445ssts_det_dnp
Definition: ahci_fsm.v:130
ahci_top.13993debug_d2h_length_prev
13993debug_d2h_length_prevreg[12:0]
Definition: ahci_top.v:701
ahci_top.13743afi_awburst
[ 1:0] 13743afi_awburst
Definition: ahci_top.v:97
ahci_fsm.13407syncesc_send
13407syncesc_send
Definition: ahci_fsm.v:51
ahci_dma.12842prd_irq_pend
reg 12842prd_irq_pend
Definition: ahci_dma.v:78
ahci_top.13769afi_rdata
[63:0] 13769afi_rdata
Definition: ahci_top.v:129
ahci_top.13953sirq_SDB
13953sirq_SDBwire
Definition: ahci_top.v:447
ahci_top.13866dma_ct_data
13866dma_ct_datawire[31:0]
Definition: ahci_top.v:289
ahci_ctrl_stat.12734serr_diag_X
12734serr_diag_X
Definition: ahci_ctrl_stat.v:115
ahci_fsm.13467get_rfis
13467get_rfis
Definition: ahci_fsm.v:168
axi_ahci_regs.14050wlast
14050wlast
Definition: axi_ahci_regs.v:67
axi_ahci_regs.14052bvalid
14052bvalid
Definition: axi_ahci_regs.v:70
ahci_top.13991DATA_TYPE_ERR
13991DATA_TYPE_ERR3
Definition: ahci_top.v:698
ahci_fsm.13477set_update_sig
13477set_update_sig
Definition: ahci_fsm.v:180
ahci_ctrl_stat.12704pcmd_clo
12704pcmd_clo
Definition: ahci_ctrl_stat.v:76
ahci_top.13968ssts_det_dnp
13968ssts_det_dnpwire
Definition: ahci_top.v:471
ahci_top.13857fsm_pgm_ad
13857fsm_pgm_adwire[17:0]
Definition: ahci_top.v:278
ahci_fis_receive.13185set_update_sig
13185set_update_sig
Definition: ahci_fis_receive.v:63
ahci_top.13935update_all_regs
13935update_all_regswire
Definition: ahci_top.v:406
ahci_dma.12876afi_bresp
[ 1:0] 12876afi_bresp
Definition: ahci_dma.v:123
ahci_ctrl_stat.12697pcmd_esp
12697pcmd_esp
Definition: ahci_ctrl_stat.v:69
axi_ahci_regs.14046wdata
[31:0] 14046wdata
Definition: axi_ahci_regs.v:63
ahci_top.13963ssts_spd_dnp
13963ssts_spd_dnpwire
Definition: ahci_top.v:465
ahci_dma.12822hrst
12822hrst
Definition: ahci_dma.v:44
ahci_fis_receive.13212pio_es
[7:0] 13212pio_es
Definition: ahci_fis_receive.v:101
axi_ahci_regs.14054bid
[11:0] 14054bid
Definition: axi_ahci_regs.v:72
ahci_top.13796set_offline
13796set_offline
Definition: ahci_top.v:164
ahci_fsm.13400was_port_rst
13400was_port_rst
Definition: ahci_fsm.v:39
ahci_ctrl_stat.12700pcmd_cr_reset
12700pcmd_cr_reset
Definition: ahci_ctrl_stat.v:72
ahci_fsm.13448ssts_det
[3:0] 13448ssts_det
Definition: ahci_fsm.v:133
ahci_top.ahci_fis_transmit
ahci_fis_transmit_i ahci_fis_transmit
Definition: ahci_top.v:1084
ahci_top.13891frcv_update_err_sts
13891frcv_update_err_stswire
Definition: ahci_top.v:327
ahci_fsm.13464bist_bits
[7:0] 13464bist_bits
Definition: ahci_fsm.v:163
axi_ahci_regs.14079hba_re
[1:0] 14079hba_re
Definition: axi_ahci_regs.v:106
axi_ahci_regs.14056araddr
[31:0] 14056araddr
Definition: axi_ahci_regs.v:75
ahci_ctrl_stat.12706pcmd_st
12706pcmd_st
Definition: ahci_ctrl_stat.v:78
ahci_top.13786d2h_ready
13786d2h_ready
Definition: ahci_top.v:151
axi_ahci_regs.14071soft_write_en
14071soft_write_en
Definition: axi_ahci_regs.v:94
ahci_fis_receive.13215xfer_cntr_zero
13215xfer_cntr_zero
Definition: ahci_fis_receive.v:105
ahci_fis_receive.13220hba_data_in
[31:0] 13220hba_data_in
Definition: ahci_fis_receive.v:116
ahci_ctrl_stat.12678mclk
12678mclk
Definition: ahci_ctrl_stat.v:34
ahci_dma.12833axi_rd_cache_mode
[3:0] 12833axi_rd_cache_mode
Definition: ahci_dma.v:62
ahci_ctrl_stat.12705pcmd_clear_st
12705pcmd_clear_st
Definition: ahci_ctrl_stat.v:77
ahci_top.13929fsnd_ch_p
13929fsnd_ch_pwire
Definition: ahci_top.v:394
ahci_top.13718bready
13718bready
Definition: ahci_top.v:67
ahci_ctrl_stat.12708pcmd_st_cleared
reg 12708pcmd_st_cleared
Definition: ahci_ctrl_stat.v:81
ahci_fsm.13429sirq_UF
13429sirq_UF
Definition: ahci_fsm.v:104
ahci_top.13694FREQ_METER_WIDTH
13694FREQ_METER_WIDTH12
Definition: ahci_top.v:36
ahci_fsm.13503clearCmdToIssue
13503clearCmdToIssue
Definition: ahci_fsm.v:230
ahci_top.13816datascope1_clk
13816datascope1_clk
Definition: ahci_top.v:196
ahci_top.13973sctl_det_changed
13973sctl_det_changedwire
Definition: ahci_top.v:478
ahci_top.13717bvalid
13717bvalid
Definition: ahci_top.v:66
ahci_fsm.13444ssts_det_ndnp
13444ssts_det_ndnp
Definition: ahci_fsm.v:129
ahci_top.13975pxci0_clear
13975pxci0_clearwire
Definition: ahci_top.v:481
ahci_top.13821drp_we
13821drp_we
Definition: ahci_top.v:205
ahci_top.13747afi_wready
13747afi_wready
Definition: ahci_top.v:102
axi_ahci_regs.14047wvalid
14047wvalid
Definition: axi_ahci_regs.v:64
ahci_top.13770afi_rvalid
13770afi_rvalid
Definition: ahci_top.v:130
ahci_fsm.13426sirq_PRC
13426sirq_PRC
Definition: ahci_fsm.v:101
ahci_dma.12857afi_awvalid
12857afi_awvalid
Definition: ahci_dma.v:102
datascope_timing.14013datascope_clk
14013datascope_clk
Definition: ahci_top.v:1245
ahci_fsm.13489decr_dwcw
13489decr_dwcw
Definition: ahci_fsm.v:200
ahci_top.13864dma_ct_addr
13864dma_ct_addrwire[4:0]
Definition: ahci_top.v:287
datascope_timing.14015datascope_we
14015datascope_we
Definition: ahci_top.v:1247
ahci_top.13692HBA_RESET_BITS
13692HBA_RESET_BITS9
Definition: ahci_top.v:34
ahci_fis_transmit.13333dma_ct_busy
13333dma_ct_busy
Definition: ahci_fis_transmit.v:87
ahci_top.13944pfsm_started
13944pfsm_startedwire
Definition: ahci_top.v:436
axi_ahci_regs.14039awaddr
[31:0] 14039awaddr
Definition: axi_ahci_regs.v:55
ahci_top.datascope_timing
datascope_timing_i datascope_timing
Definition: ahci_top.v:1163
ahci_fis_receive.13183dma_prds_done
13183dma_prds_done
Definition: ahci_fis_receive.v:61
ahci_top.13899frcv_decr_dwcr
13899frcv_decr_dwcrwire
Definition: ahci_top.v:337
ahci_fis_receive.13166mclk
13166mclk
Definition: ahci_fis_receive.v:41
ahci_fis_receive.13187sig_available
reg 13187sig_available
Definition: ahci_fis_receive.v:65
ahci_top.13809serr_EC
13809serr_EC
Definition: ahci_top.v:182
axi_ahci_regs.14059arid
[11:0] 14059arid
Definition: axi_ahci_regs.v:78
ahci_fsm.13442ssts_spd_gen2
13442ssts_spd_gen2
Definition: ahci_fsm.v:126
ahci_dma.12861afi_awcache
reg [ 3:0] 12861afi_awcache
Definition: ahci_dma.v:106
datascope_timing.14019pend_punch_time
14019pend_punch_timereg
Definition: ahci_top.v:1254
ahci_ctrl_stat.12695update_pci
12695update_pci
Definition: ahci_ctrl_stat.v:60
ahci_dma.12892afi_rvalid
12892afi_rvalid
Definition: ahci_dma.v:143
ahci_fis_transmit.13327reg_rdata
[31:0] 13327reg_rdata
Definition: ahci_fis_transmit.v:77
ahci_dma.12872afi_wstrb
[ 7:0] 12872afi_wstrb
Definition: ahci_dma.v:118
ahci_top.13789xmit_err
13789xmit_err
Definition: ahci_top.v:157
ahci_top.13802serr_DH
13802serr_DH
Definition: ahci_top.v:173
datascope_timing.14014datascope_waddr
reg [ADDRESS_BITS-1:0] 14014datascope_waddr
Definition: ahci_top.v:1246
ahci_fis_receive.13191update_prdbc
13191update_prdbc
Definition: ahci_fis_receive.v:70
ahci_top.13872dma_abort_done
13872dma_abort_donewire
Definition: ahci_top.v:297
axi_ahci_regs.14058arready
14058arready
Definition: axi_ahci_regs.v:77
ahci_fsm.13465get_dsfis
13465get_dsfis
Definition: ahci_fsm.v:166
ahci_fis_receive.13217reg_addr
reg [ADDRESS_BITS-1:0] 13217reg_addr
Definition: ahci_fis_receive.v:112
ahci_top.13992debug_d2h_length
13992debug_d2h_lengthreg[12:0]
Definition: ahci_top.v:700
ahci_fsm.13487clear_xfer_cntr
13487clear_xfer_cntr
Definition: ahci_fsm.v:197
axi_ahci_regs.14072hba_arst
14072hba_arst
Definition: axi_ahci_regs.v:96
ahci_top.13712wvalid
13712wvalid
Definition: ahci_top.v:60
datascope_timing.14009d2h_data
[31:0] 14009d2h_data
Definition: ahci_top.v:1240
ahci_fis_receive.13177get_ignore
13177get_ignore
Definition: ahci_fis_receive.v:55
ahci_top.13805serr_DW
13805serr_DW
Definition: ahci_top.v:176
ahci_ctrl_stat.12735ssts_ipm_dnp
12735ssts_ipm_dnp
Definition: ahci_ctrl_stat.v:119
ahci_top.13751afi_bvalid
13751afi_bvalid
Definition: ahci_top.v:107
ahci_top.13949sirq_PRC
13949sirq_PRCwire
Definition: ahci_top.v:443
ahci_dma.12871afi_wlast
12871afi_wlast
Definition: ahci_dma.v:117
ahci_fis_transmit.13335dma_cmd_abort
reg 13335dma_cmd_abort
Definition: ahci_fis_transmit.v:90
ahci_top.13895frcv_clear_bsy_set_drq
13895frcv_clear_bsy_set_drqwire
Definition: ahci_top.v:332
ahci_fis_transmit.13321ch_w
13321ch_w
Definition: ahci_fis_transmit.v:68
ahci_fis_receive.13222hba_data_in_valid
13222hba_data_in_valid
Definition: ahci_fis_receive.v:118
ahci_ctrl_stat.12688update_all
12688update_all
Definition: ahci_ctrl_stat.v:52
ahci_dma.12831cmd_abort
12831cmd_abort
Definition: ahci_dma.v:57
ahci_fsm.13482clear_bsy_drq
13482clear_bsy_drq
Definition: ahci_fsm.v:191
ahci_top.13793syncesc_send_done
13793syncesc_send_done
Definition: ahci_top.v:161
ahci_ctrl_stat.12737ssts_ipm_part
12737ssts_ipm_part
Definition: ahci_ctrl_stat.v:121
ahci_dma.12821mrst
12821mrst
Definition: ahci_dma.v:43
ahci_dma.12823mclk
12823mclk
Definition: ahci_dma.v:46
ahci_top.13894frcv_clear_bsy_drq
13894frcv_clear_bsy_drqwire
Definition: ahci_top.v:331
datascope_timing.14024fis_len
14024fis_lenreg[12:0]
Definition: ahci_top.v:1259
ahci_fsm.13438ssts_ipm_slumb
13438ssts_ipm_slumb
Definition: ahci_fsm.v:121
ahci_top.13813sctl_ipm
[3:0] 13813sctl_ipm
Definition: ahci_top.v:187
ahci_fis_receive.13182fis_ferr
13182fis_ferr
Definition: ahci_fis_receive.v:60
ahci_dma.12870afi_wid
[ 5:0] 12870afi_wid
Definition: ahci_dma.v:116
axi_ahci_regs.14053bready
14053bready
Definition: axi_ahci_regs.v:71
ahci_fsm.13440ssts_spd_dnp
13440ssts_spd_dnp
Definition: ahci_fsm.v:124
ahci_top.13860axi_wr_cache_mode
13860axi_wr_cache_modewire[3:0]
Definition: ahci_top.v:283
ahci_ctrl_stat.12719sirq_PS
12719sirq_PS
Definition: ahci_ctrl_stat.v:95
ahci_top.13794comreset_send
13794comreset_send
Definition: ahci_top.v:162
ahci_top.13901frcv_clear_xfer_cntr
13901frcv_clear_xfer_cntrwire
Definition: ahci_top.v:339
ahci_fsm.13474fis_err
13474fis_err
Definition: ahci_fsm.v:176
ahci_top.13881frcv_first_vld
13881frcv_first_vldwire
Definition: ahci_top.v:313
ahci_fsm.13424sirq_INF
13424sirq_INF
Definition: ahci_fsm.v:99
ahci_dma.12839ct_data
reg [31:0] 12839ct_data
Definition: ahci_dma.v:72
ahci_fsm.13469get_ufis
13469get_ufis
Definition: ahci_fsm.v:170
ahci_fsm.13432sirq_PS
13432sirq_PS
Definition: ahci_fsm.v:107
axi_ahci_regs.14077hba_addr
[ADDRESS_BITS-1:0] 14077hba_addr
Definition: axi_ahci_regs.v:103
ahci_fsm.13500dx_xmit
13500dx_xmit
Definition: ahci_fsm.v:224
ahci_fsm.13404pgm_wa
13404pgm_wa
Definition: ahci_fsm.v:45
ahci_top.13892frcv_update_pio
13892frcv_update_piowire
Definition: ahci_top.v:328
ahci_fsm.13496pio_d
13496pio_d
Definition: ahci_fsm.v:212
ahci_top.13947sirq_INF
13947sirq_INFwire
Definition: ahci_top.v:441
axi_ahci_regs.14086afi_rcache
reg [ 3:0] 14086afi_rcache
Definition: axi_ahci_regs.v:119
ahci_fsm.13437ssts_ipm_part
13437ssts_ipm_part
Definition: ahci_fsm.v:120
ahci_top.13896frcv_set_bsy
13896frcv_set_bsywire
Definition: ahci_top.v:334
ahci_fsm.13504pCmdToIssue
13504pCmdToIssue
Definition: ahci_fsm.v:231
ahci_fis_receive.13207sdb_n
reg 13207sdb_n
Definition: ahci_fis_receive.v:96
ahci_top.13788xmit_ok
13788xmit_ok
Definition: ahci_top.v:156
ahci_top.13723arready
13723arready
Definition: ahci_top.v:73
ahci_top.13851prdtl
13851prdtlwire[15:0]
Definition: ahci_top.v:269
ahci_top.13882frcv_first_invalid
13882frcv_first_invalidwire
Definition: ahci_top.v:315
ahci_fsm.13470get_data_fis
13470get_data_fis
Definition: ahci_fsm.v:171
ahci_ctrl_stat.12739ssts_ipm_devsleep
12739ssts_ipm_devsleep
Definition: ahci_ctrl_stat.v:123
axi_ahci_regs.14063rdata
[31:0] 14063rdata
Definition: axi_ahci_regs.v:83
ahci_top.13893frcv_update_prdbc
13893frcv_update_prdbcwire
Definition: ahci_top.v:330
ahci_top.13835soft_write_en
13835soft_write_enwire
Definition: ahci_top.v:229
ahci_top.13850ctba_ld
13850ctba_ldwire
Definition: ahci_top.v:268
ahci_top.13729rvalid
13729rvalid
Definition: ahci_top.v:80
ahci_dma.12897afi_rcount
[ 7:0] 12897afi_rcount
Definition: ahci_dma.v:149
datascope_timing.14020write_punch_time
14020write_punch_timewire
Definition: ahci_top.v:1255
ahci_top.13706awready
13706awready
Definition: ahci_top.v:53
ahci_top.13844regs_dout
13844regs_doutwire[31:0]
Definition: ahci_top.v:243
axi_ahci_regs.14088was_hba_rst
14088was_hba_rst
Definition: axi_ahci_regs.v:121
axi_ahci_regs.14061arsize
[ 1:0] 14061arsize
Definition: axi_ahci_regs.v:80
ahci_top.13776afi_racount
[ 2:0] 13776afi_racount
Definition: ahci_top.v:137
ahci_ctrl_stat.12746ssts_det_dp
12746ssts_det_dp
Definition: ahci_ctrl_stat.v:132
ahci_top.13843regs_din_from_freceive
13843regs_din_from_freceivewire[31:0]
Definition: ahci_top.v:242
ahci_top.13922fsnd_done
13922fsnd_donewire
Definition: ahci_top.v:384
ahci_top.13990DATA_TYPE_OK
13990DATA_TYPE_OK2
Definition: ahci_top.v:697
ahci_ctrl_stat.12714sirq_PC
12714sirq_PC
Definition: ahci_ctrl_stat.v:90
ahci_ctrl_stat.12725serr_DB
12725serr_DB
Definition: ahci_ctrl_stat.v:104
ahci_fis_transmit.13300hba_rst
13300hba_rst
Definition: ahci_fis_transmit.v:36
ahci_top.13983unsolicited_en
13983unsolicited_enwire
Definition: ahci_top.v:493
ahci_top.13689READ_REG_LATENCY
13689READ_REG_LATENCY2
Definition: ahci_top.v:30
ahci_fis_receive.13178get_fis_busy
13178get_fis_busy
Definition: ahci_fis_receive.v:56
ahci_top.13766afi_arsize
[ 1:0] 13766afi_arsize
Definition: ahci_top.v:125
ahci_top.13941pcmd_fre
13941pcmd_frewire
Definition: ahci_top.v:431
ahci_fis_transmit.13344todev_type
reg [ 1:0] 13344todev_type
Definition: ahci_fis_transmit.v:105
ahci_fis_transmit.13302pcmd_st_cleared
13302pcmd_st_cleared
Definition: ahci_fis_transmit.v:38
axi_ahci_regs.14049wid
[11:0] 14049wid
Definition: axi_ahci_regs.v:66
datascope_timing.14030fis_end
14030fis_endwire
Definition: ahci_top.v:1267
ahci_top.13836regs_we_acs
13836regs_we_acswire
Definition: ahci_top.v:234
ahci_top.13736afi_awready
13736afi_awready
Definition: ahci_top.v:90
ahci_top.13756afi_wacount
[ 5:0] 13756afi_wacount
Definition: ahci_top.v:113
axi_ahci_regs.14106datascope1_we
14106datascope1_we
Definition: axi_ahci_regs.v:144
ahci_ctrl_stat.12738ssts_ipm_slumb
12738ssts_ipm_slumb
Definition: ahci_ctrl_stat.v:122
ahci_top.13903frcv_done
13903frcv_donewire
Definition: ahci_top.v:343
ahci_top.13807serr_EE
13807serr_EE
Definition: ahci_top.v:180
ahci_ctrl_stat.12683soft_write_en
12683soft_write_en
Definition: ahci_ctrl_stat.v:41
ahci_top.13837regs_din_from_acs
13837regs_din_from_acswire[31:0]
Definition: ahci_top.v:236
ahci_fis_receive.13190update_pio
13190update_pio
Definition: ahci_fis_receive.v:69
ahci_dma.12885afi_arcache
reg [ 3:0] 12885afi_arcache
Definition: ahci_dma.v:135
datascope_timing.14016datascope_di
reg [31:0] 14016datascope_di
Definition: ahci_top.v:1248
ahci_dma.12849sys_dav
12849sys_dav
Definition: ahci_dma.v:87
datascope_timing.14001rst
14001rst
Definition: ahci_top.v:1225
ahci_fsm.13398mclk
13398mclk
Definition: ahci_fsm.v:37
ahci_fsm.13495pio_i
13495pio_i
Definition: ahci_fsm.v:211
ahci_ctrl_stat.12748ssts_det
[3:0] 12748ssts_det
Definition: ahci_ctrl_stat.v:134
ahci_top.13819datascope1_di
[31:0] 13819datascope1_di
Definition: ahci_top.v:199
ahci_dma.12867afi_wdata
[63:0] 12867afi_wdata
Definition: ahci_dma.v:113
ahci_fis_receive.13197set_sts_80
13197set_sts_80
Definition: ahci_fis_receive.v:76
ahci_ctrl_stat.12701pcmd_fr
12701pcmd_fr
Definition: ahci_ctrl_stat.v:73
axi_ahci_regs.14044awsize
[ 1:0] 14044awsize
Definition: axi_ahci_regs.v:60
ahci_top.13731rid
[11:0] 13731rid
Definition: ahci_top.v:82
ahci_top.13710awburst
[ 1:0] 13710awburst
Definition: ahci_top.v:57
ahci_fis_receive.13195set_bsy
13195set_bsy
Definition: ahci_fis_receive.v:74
ahci_top.13824drp_rdy
13824drp_rdy
Definition: ahci_top.v:208
ahci_ctrl_stat.12696update_ghc
12696update_ghc
Definition: ahci_ctrl_stat.v:61
ahci_fis_transmit.13338ct_data
[31:0] 13338ct_data
Definition: ahci_fis_transmit.v:95
axi_ahci_regs.14091debug_in1
[31:0] 14091debug_in1
Definition: axi_ahci_regs.v:124
datascope_timing.14021fis_run
14021fis_runreg
Definition: ahci_top.v:1256
ahci_fsm.13505dx_err
[ 2:0] 13505dx_err
Definition: ahci_fsm.v:235
ahci_fsm.13418pcmd_cr_reset
13418pcmd_cr_reset
Definition: ahci_fsm.v:85
ahci_top.13726arsize
[ 1:0] 13726arsize
Definition: ahci_top.v:76
ahci_fsm.13434serr_diag_X
13434serr_diag_X
Definition: ahci_fsm.v:113
ahci_fis_transmit.13309clearCmdToIssue
13309clearCmdToIssue
Definition: ahci_fis_transmit.v:51
ahci_dma.12860afi_awlock
[ 1:0] 12860afi_awlock
Definition: ahci_dma.v:105
ahci_top.13759afi_arvalid
13759afi_arvalid
Definition: ahci_top.v:118
axi_ahci_regs.14057arvalid
14057arvalid
Definition: axi_ahci_regs.v:76
axi_ahci_regs.14100datascope_clk
14100datascope_clk
Definition: axi_ahci_regs.v:137
ahci_fsm.13468get_sdbfis
13468get_sdbfis
Definition: ahci_fsm.v:169
ahci_dma.12882afi_arready
12882afi_arready
Definition: ahci_dma.v:132
ahci_ctrl_stat.12715sirq_DP
12715sirq_DP
Definition: ahci_ctrl_stat.v:91
ahci_dma.12858afi_awready
12858afi_awready
Definition: ahci_dma.v:103
ahci_fsm.13422sirq_TFE
13422sirq_TFE
Definition: ahci_fsm.v:97
ahci_fsm.13409comreset_send
13409comreset_send
Definition: ahci_fsm.v:53
ahci_ctrl_stat.12707pfsm_started
12707pfsm_started
Definition: ahci_ctrl_stat.v:80
ahci_ctrl_stat.12744ssts_det_ndnp
12744ssts_det_ndnp
Definition: ahci_ctrl_stat.v:130
ahci_top.13757afi_wrissuecap1en
13757afi_wrissuecap1en
Definition: ahci_top.v:114
axi_ahci_regs.14042awid
[11:0] 14042awid
Definition: axi_ahci_regs.v:58
ahci_top.13996ahci_fis_transmit_busy
13996ahci_fis_transmit_busywire
Definition: ahci_top.v:1082
ahci_top.13870dma_cmd_done
13870dma_cmd_donewire
Definition: ahci_top.v:294
ahci_top.13688PREFETCH_ALWAYS
13688PREFETCH_ALWAYS0
Definition: ahci_top.v:29
ahci_fis_transmit.13339dma_out
[31:0] 13339dma_out
Definition: ahci_fis_transmit.v:98
ahci_ctrl_stat.12685regs_we
reg 12685regs_we
Definition: ahci_ctrl_stat.v:45
ahci_top.13716wstb
[ 3:0] 13716wstb
Definition: ahci_top.v:64
ahci_fis_transmit.13346todev_ready
13346todev_ready
Definition: ahci_fis_transmit.v:107
ahci_top.13931fsnd_ch_a
13931fsnd_ch_awire
Definition: ahci_top.v:396
ahci_fis_receive.13213sactive0
reg 13213sactive0
Definition: ahci_fis_receive.v:102
ahci_ctrl_stat.12687update_pending
12687update_pending
Definition: ahci_ctrl_stat.v:51
ahci_top.13708awlen
[ 3:0] 13708awlen
Definition: ahci_top.v:55
ahci_ctrl_stat.12686regs_din
reg [31:0] 12686regs_din
Definition: ahci_ctrl_stat.v:48
ahci_fis_receive.13210pio_i
reg 13210pio_i
Definition: ahci_fis_receive.v:99
ahci_fis_receive.13181fis_err
reg 13181fis_err
Definition: ahci_fis_receive.v:59
axi_ahci_regs.14082pgm_ad
reg [17:0] 14082pgm_ad
Definition: axi_ahci_regs.v:111
ahci_fsm.13476fis_extra
13476fis_extra
Definition: ahci_fsm.v:178
ahci_dma.12879afi_wrissuecap1en
12879afi_wrissuecap1en
Definition: ahci_dma.v:127
ahci_top.13702hclk
13702hclk
Definition: ahci_top.v:47
ahci_fsm.13436ssts_ipm_active
13436ssts_ipm_active
Definition: ahci_fsm.v:119
axi_ahci_regs.14060arlen
[ 3:0] 14060arlen
Definition: axi_ahci_regs.v:79
ahci_fsm.13423sirq_IF
13423sirq_IF
Definition: ahci_fsm.v:98
ahci_top.13806serr_DI
13806serr_DI
Definition: ahci_top.v:177
ahci_top.13936update_regs_busy
13936update_regs_busywire
Definition: ahci_top.v:407
ahci_ctrl_stat.12721serr_DT
12721serr_DT
Definition: ahci_ctrl_stat.v:100
ahci_top.13880dma_extra_din
13880dma_extra_dinwire
Definition: ahci_top.v:307
ahci_fsm.13506ch_c
13506ch_c
Definition: ahci_fsm.v:238
ahci_fsm.13481update_prdbc
13481update_prdbc
Definition: ahci_fsm.v:190
ahci_top.13855dma_cmd_abort_xmit
13855dma_cmd_abort_xmitwire
Definition: ahci_top.v:274
ahci_fsm.13493fis_i
13493fis_i
Definition: ahci_fsm.v:207
ahci_dma.12866afi_awqos
[ 3:0] 12866afi_awqos
Definition: ahci_dma.v:111
ahci_fis_receive.13223hba_data_in_many
13223hba_data_in_many
Definition: ahci_fis_receive.v:119
ahci_ctrl_stat.12724serr_DC
12724serr_DC
Definition: ahci_ctrl_stat.v:103
ahci_ctrl_stat.12752sctl_det_changed
reg 12752sctl_det_changed
Definition: ahci_ctrl_stat.v:140
ahci_fsm.13443ssts_spd_gen3
13443ssts_spd_gen3
Definition: ahci_fsm.v:127
ahci_top.13883frcv_first_flush
13883frcv_first_flushwire
Definition: ahci_top.v:316
ahci_top.13762afi_arlock
[ 1:0] 13762afi_arlock
Definition: ahci_top.v:121
ahci_ctrl_stat.12710sirq_IF
12710sirq_IF
Definition: ahci_ctrl_stat.v:86
ahci_fsm.13462fis_first_vld
13462fis_first_vld
Definition: ahci_fsm.v:161
datascope_timing.14023fis_we
14023fis_wereg
Definition: ahci_top.v:1258
axi_ahci_regs.14080hba_din
[31:0] 14080hba_din
Definition: axi_ahci_regs.v:107
ahci_top.13804serr_DB
13804serr_DB
Definition: ahci_top.v:175
ahci_top.13810serr_ET
13810serr_ET
Definition: ahci_top.v:183
ahci_top.13820drp_en
13820drp_en
Definition: ahci_top.v:204
ahci_top.13733rresp
[ 1:0] 13733rresp
Definition: ahci_top.v:84
axi_ahci_regs.14076hba_rst
14076hba_rst
Definition: axi_ahci_regs.v:102
ahci_fis_transmit.13328xfer_cntr
[31:2] 13328xfer_cntr
Definition: ahci_fis_transmit.v:80
ahci_top.13918fsnd_fetch_cmd
13918fsnd_fetch_cmdwire
Definition: ahci_top.v:377
ahci_ctrl_stat.12754pxci0_clear
12754pxci0_clear
Definition: ahci_ctrl_stat.v:143
axi_ahci_regs.14083pgm_wa
reg 14083pgm_wa
Definition: axi_ahci_regs.v:112
ahci_fsm.13486set_sts_80
13486set_sts_80
Definition: ahci_fsm.v:196
ahci_fis_receive.13228debug_fis_end_w
13228debug_fis_end_w
Definition: ahci_fis_receive.v:127
ahci_top.ahci_ctrl_stat
ahci_ctrl_stat_i ahci_ctrl_stat
Definition: ahci_top.v:819
ahci_fsm.13510ch_w
13510ch_w
Definition: ahci_fsm.v:242
ahci_top.13956sirq_DHR
13956sirq_DHRwire
Definition: ahci_top.v:450
ahci_fis_transmit.13312xmit_err
13312xmit_err
Definition: ahci_fis_transmit.v:58
ahci_top.13735afi_awvalid
13735afi_awvalid
Definition: ahci_top.v:89
ahci_fsm.13512unsolicited_en
13512unsolicited_en
Definition: ahci_fsm.v:244
ahci_top.13829datascope_clk
13829datascope_clkwire
Definition: ahci_top.v:219
ahci_dma.12841prd_irq_clear
12841prd_irq_clear
Definition: ahci_dma.v:77
ahci_top.13803serr_DC
13803serr_DC
Definition: ahci_top.v:174
ahci_fsm.13430sirq_SDB
13430sirq_SDB
Definition: ahci_fsm.v:105
axi_ahci_regs.14037aclk
14037aclk
Definition: axi_ahci_regs.v:51
ahci_fis_receive.13165hba_rst
13165hba_rst
Definition: ahci_fis_receive.v:40
ahci_fis_transmit.13332dma_dev_wr
13332dma_dev_wr
Definition: ahci_fis_transmit.v:86
ahci_top.13928fsnd_ch_r
13928fsnd_ch_rwire
Definition: ahci_top.v:393
ahci_ctrl_stat.12691update_pis
12691update_pis
Definition: ahci_ctrl_stat.v:56
ahci_ctrl_stat.12745ssts_det_dnp
12745ssts_det_dnp
Definition: ahci_ctrl_stat.v:131
ahci_top.13749afi_wlast
13749afi_wlast
Definition: ahci_top.v:104
ahci_top.13714wid
[11:0] 13714wid
Definition: ahci_top.v:62
ahci_top.13832datascope_di
13832datascope_diwire[31:0]
Definition: ahci_top.v:222
ahci_ctrl_stat.12729serr_EP
12729serr_EP
Definition: ahci_ctrl_stat.v:110
axi_ahci_regs.14066rid
[11:0] 14066rid
Definition: axi_ahci_regs.v:86
ahci_top.13761afi_arid
[ 5:0] 13761afi_arid
Definition: ahci_top.v:120
ahci_fsm.13439ssts_ipm_devsleep
13439ssts_ipm_devsleep
Definition: ahci_fsm.v:122
ahci_top.13889frcv_get_data_fis
13889frcv_get_data_fiswire
Definition: ahci_top.v:323
ahci_fsm.13446ssts_det_dp
13446ssts_det_dp
Definition: ahci_fsm.v:131
axi_ahci_regs.14038arst
14038arst
Definition: axi_ahci_regs.v:52
ahci_top.13721araddr
[31:0] 13721araddr
Definition: ahci_top.v:71
ahci_top.13745afi_wdata
[63:0] 13745afi_wdata
Definition: ahci_top.v:100
ahci_dma.12844cmd_done
12844cmd_done
Definition: ahci_dma.v:80
ahci_dma.12832axi_wr_cache_mode
[3:0] 12832axi_wr_cache_mode
Definition: ahci_dma.v:61
datascope_timing.14002soft_write_addr
[ADDRESS_BITS-1:0] 14002soft_write_addr
Definition: ahci_top.v:1227
ahci_fis_receive.13171get_dsfis
13171get_dsfis
Definition: ahci_fis_receive.v:49
ahci_top.13732rlast
13732rlast
Definition: ahci_top.v:83
ahci_fis_receive.13221hba_data_in_type
[ 1:0] 13221hba_data_in_type
Definition: ahci_fis_receive.v:117
ahci_dma.12837ct_addr
[ 4:0] 12837ct_addr
Definition: ahci_dma.v:70
axi_ahci_regs.14081hba_dout
[31:0] 14081hba_dout
Definition: axi_ahci_regs.v:108
ahci_fsm.13497xfer_cntr_zero
13497xfer_cntr_zero
Definition: ahci_fsm.v:217
ahci_top.13795cominit_got
13795cominit_got
Definition: ahci_top.v:163
axi_ahci_regs.14073port_arst
14073port_arst
Definition: axi_ahci_regs.v:97
ahci_top.13925fsnd_dx_err
13925fsnd_dx_errwire[2:0]
Definition: ahci_top.v:390
ahci_top.13914pio_d
13914pio_dwire
Definition: ahci_top.v:364
ahci_dma.12824hclk
12824hclk
Definition: ahci_dma.v:47
ahci_fsm.13459dma_abort_done
13459dma_abort_done
Definition: ahci_fsm.v:154
ahci_fsm.13460fis_first_invalid
13460fis_first_invalid
Definition: ahci_fsm.v:158
ahci_ctrl_stat.12690update_gis
12690update_gis
Definition: ahci_ctrl_stat.v:55
ahci_dma.12853sys_nfull
12853sys_nfull
Definition: ahci_dma.v:94
datascope_timing.14027cur_time
14027cur_timereg[27:0]
Definition: ahci_top.v:1262
ahci_top.13909frcv_update_sig
13909frcv_update_sigwire
Definition: ahci_top.v:352
ahci_top.13886frcv_get_rfis
13886frcv_get_rfiswire
Definition: ahci_top.v:320
ahci_top.13755afi_wcount
[ 7:0] 13755afi_wcount
Definition: ahci_top.v:112
ahci_fis_receive.13201decr_DXC_dw
[11:0] 13201decr_DXC_dw
Definition: ahci_fis_receive.v:81
ahci_top.13950sirq_PC
13950sirq_PCwire
Definition: ahci_top.v:444
ahci_dma.12852sys_in
[31:0] 12852sys_in
Definition: ahci_dma.v:93
ahci_top.13808serr_EP
13808serr_EP
Definition: ahci_top.v:181
ahci_fis_receive.13206fis_i
reg 13206fis_i
Definition: ahci_fis_receive.v:95
ahci_fis_transmit.13304cfis_xmit
13304cfis_xmit
Definition: ahci_fis_transmit.v:42
ahci_ctrl_stat.12757unsolicited_en
12757unsolicited_en
Definition: ahci_ctrl_stat.v:147
ahci_fsm.13413send_R_ERR
13413send_R_ERR
Definition: ahci_fsm.v:58
ahci_top.13704awaddr
[31:0] 13704awaddr
Definition: ahci_top.v:51
ahci_top.13777afi_rdissuecap1en
13777afi_rdissuecap1en
Definition: ahci_top.v:138
ahci_fis_transmit.13340dma_dav
13340dma_dav
Definition: ahci_fis_transmit.v:99
ahci_top.13939pcmd_cr_reset
13939pcmd_cr_resetwire
Definition: ahci_top.v:427
ahci_fis_receive.13203pPioXfer
reg 13203pPioXfer
Definition: ahci_fis_receive.v:91
ahci_fis_transmit.13331dma_start
13331dma_start
Definition: ahci_fis_transmit.v:85
ahci_fsm.13420pcmd_st
13420pcmd_st
Definition: ahci_fsm.v:92
ahci_fsm.13488decr_dwcr
13488decr_dwcr
Definition: ahci_fsm.v:199
ahci_top.13912dma_a
13912dma_awire
Definition: ahci_top.v:361
ahci_fis_receive.13196set_sts_7f
13196set_sts_7f
Definition: ahci_fis_receive.v:75
axi_ahci_regs.14051wstb
[ 3:0] 14051wstb
Definition: axi_ahci_regs.v:68
ahci_top.13699hba_arst
13699hba_arst
Definition: ahci_top.v:44
ahci_top.13838regs_we_freceive
13838regs_we_freceivewire
Definition: ahci_top.v:237
ahci_fis_receive.13169fis_first_invalid
13169fis_first_invalid
Definition: ahci_fis_receive.v:46
ahci_top.13997xmit_dbg_01
13997xmit_dbg_01wire[9:0]
Definition: ahci_top.v:1083
ahci_top.13984debug_data_in_ready
13984debug_data_in_readywire
Definition: ahci_top.v:689
ahci_fsm.13427sirq_PC
13427sirq_PC
Definition: ahci_fsm.v:102
ahci_top.13827debug_in_phy
[31:0] 13827debug_in_phy
Definition: ahci_top.v:212
ahci_fsm.13454pxci0
13454pxci0
Definition: ahci_fsm.v:145
ahci_fis_transmit.13314xrdy_collision
13314xrdy_collision
Definition: ahci_fis_transmit.v:60
datascope_timing.14029fis_start
14029fis_startwire
Definition: ahci_top.v:1265
datascope_timing.13998ADDRESS_BITS
13998ADDRESS_BITS10
Definition: ahci_top.v:1221
ahci_top.13767afi_arburst
[ 1:0] 13767afi_arburst
Definition: ahci_top.v:126
ahci_top.13841regs_waddr
13841regs_waddrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:240
datascope_timing.14012d2h_ready
14012d2h_ready
Definition: ahci_top.v:1243
ahci_dma.12891afi_rdata
[63:0] 12891afi_rdata
Definition: ahci_dma.v:142
ahci_ctrl_stat.12727serr_DI
12727serr_DI
Definition: ahci_ctrl_stat.v:106
ahci_ctrl_stat.12699pcmd_cr_set
12699pcmd_cr_set
Definition: ahci_ctrl_stat.v:71
ahci_ctrl_stat.12755pxci0
12755pxci0
Definition: ahci_ctrl_stat.v:144
ahci_fsm.13416update_busy
13416update_busy
Definition: ahci_fsm.v:69
ahci_ctrl_stat.12730serr_EC
12730serr_EC
Definition: ahci_ctrl_stat.v:111
ahci_top.13979last_jump_addr
13979last_jump_addrwire[9:0]
Definition: ahci_top.v:488
datascope_timing.14005h2d_data
[31:0] 14005h2d_data
Definition: ahci_top.v:1232
ahci_fsm.13502xmit_done
13502xmit_done
Definition: ahci_fsm.v:227
ahci_fsm.13490pxcmd_fre
13490pxcmd_fre
Definition: ahci_fsm.v:202
axi_ahci_regs.14064rvalid
14064rvalid
Definition: axi_ahci_regs.v:84
ahci_fis_transmit.13336ct_addr
reg [ 4:0] 13336ct_addr
Definition: ahci_fis_transmit.v:93
ahci_top.13693RESET_TO_FIRST_ACCESS
13693RESET_TO_FIRST_ACCESS1
Definition: ahci_top.v:35
ahci_dma.12869afi_wready
12869afi_wready
Definition: ahci_dma.v:115
ahci_top.13951sirq_DP
13951sirq_DPwire
Definition: ahci_top.v:445
ahci_top.13828debug_in_link
[31:0] 13828debug_in_link
Definition: ahci_top.v:213
axi_ahci_regs.14101datascope_waddr
[ADDRESS_BITS-1:0] 14101datascope_waddr
Definition: axi_ahci_regs.v:138
ahci_top.13873axi_mismatch
13873axi_mismatchwire
Definition: ahci_top.v:298
ahci_top.13959ssts_ipm_active
13959ssts_ipm_activewire
Definition: ahci_top.v:460
ahci_top.13980debug_dma
13980debug_dmawire[31:0]
Definition: ahci_top.v:489
ahci_top.13792syncesc_send
13792syncesc_send
Definition: ahci_top.v:160
ahci_ctrl_stat.12740ssts_spd_dnp
12740ssts_spd_dnp
Definition: ahci_ctrl_stat.v:125
ahci_dma.12836ct_busy
reg 12836ct_busy
Definition: ahci_dma.v:68
ahci_fis_receive.13172get_psfis
13172get_psfis
Definition: ahci_fis_receive.v:50
ahci_top.13741afi_awlen
[ 3:0] 13741afi_awlen
Definition: ahci_top.v:95
ahci_top.13768afi_arqos
[ 3:0] 13768afi_arqos
Definition: ahci_top.v:127
ahci_dma.12851last_h2d_data
12851last_h2d_data
Definition: ahci_dma.v:90
ahci_dma.12830prd_start
12830prd_start
Definition: ahci_dma.v:56
ahci_dma.12878afi_wacount
[ 5:0] 12878afi_wacount
Definition: ahci_dma.v:126
ahci_dma.12847axi_mismatch
12847axi_mismatch
Definition: ahci_dma.v:83
ahci_fis_receive.13173get_rfis
13173get_rfis
Definition: ahci_fis_receive.v:51
ahci_fsm.13458dma_cmd_abort
13458dma_cmd_abort
Definition: ahci_fsm.v:153
ahci_fsm.13425sirq_OF
13425sirq_OF
Definition: ahci_fsm.v:100
ahci_top.13773afi_rlast
13773afi_rlast
Definition: ahci_top.v:133
ahci_ctrl_stat.12747ssts_det_offline
12747ssts_det_offline
Definition: ahci_ctrl_stat.v:133
ahci_top.DATASCOPE_FIS_DATA
feature DATASCOPE_FIS_DATA 1
Definition: ahci_top.v:1146
ahci_top.13739afi_awcache
[ 3:0] 13739afi_awcache
Definition: ahci_top.v:93
ahci_fsm.13419pcmd_clo
13419pcmd_clo
Definition: ahci_fsm.v:90
ahci_dma.12845abort_busy
12845abort_busy
Definition: ahci_dma.v:81
axi_ahci_regs.14094drp_en
reg 14094drp_en
Definition: axi_ahci_regs.v:128
ahci_fis_transmit.13345todev_valid
13345todev_valid
Definition: ahci_fis_transmit.v:106
axi_ahci_regs.14055bresp
[ 1:0] 14055bresp
Definition: axi_ahci_regs.v:73
ahci_top.13994was_good_bad
13994was_good_badreg
Definition: ahci_top.v:702
ahci_top.13964ssts_spd_gen1
13964ssts_spd_gen1wire
Definition: ahci_top.v:466
ahci_fsm.13499cfis_xmit
13499cfis_xmit
Definition: ahci_fsm.v:223
ahci_top.13937pcmd_esp
13937pcmd_espwire
Definition: ahci_top.v:424
ahci_dma.12895afi_rlast
12895afi_rlast
Definition: ahci_dma.v:146
ahci_ctrl_stat.12720sirq_DHR
12720sirq_DHR
Definition: ahci_ctrl_stat.v:96
datascope_timing.14011d2h_valid
14011d2h_valid
Definition: ahci_top.v:1242
ahci_fsm.13498fetch_cmd
13498fetch_cmd
Definition: ahci_fsm.v:221
ahci_top.13740afi_awprot
[ 2:0] 13740afi_awprot
Definition: ahci_top.v:94
ahci_fsm.13405pgm_wd
13405pgm_wd
Definition: ahci_fsm.v:46
ahci_fsm.13397hba_rst
13397hba_rst
Definition: ahci_fsm.v:36
ahci_top.13817datascope1_waddr
[ADDRESS_BITS-1:0] 13817datascope1_waddr
Definition: ahci_top.v:197
axi_ahci_regs.14070soft_write_data
[31:0] 14070soft_write_data
Definition: axi_ahci_regs.v:93
ahci_ctrl_stat.12684regs_addr
reg [ADDRESS_BITS-1:0] 12684regs_addr
Definition: ahci_ctrl_stat.v:44
ahci_top.13774afi_rresp
[ 1:0] 13774afi_rresp
Definition: ahci_top.v:134
ahci_fis_receive.13229debug_fis_end_r
[1:0] 13229debug_fis_end_r
Definition: ahci_fis_receive.v:128
ahci_fis_receive.13186pUpdateSig
13186pUpdateSig
Definition: ahci_fis_receive.v:64
ahci_ctrl_stat.12731serr_ET
12731serr_ET
Definition: ahci_ctrl_stat.v:112
ahci_top.13722arvalid
13722arvalid
Definition: ahci_top.v:72
ahci_dma.12894afi_rid
[ 5:0] 12894afi_rid
Definition: ahci_dma.v:145
ahci_top.13742afi_awsize
[ 1:0] 13742afi_awsize
Definition: ahci_top.v:96
ahci_ctrl_stat.12677mrst
12677mrst
Definition: ahci_ctrl_stat.v:33
ahci_fsm.13406phy_ready
[1:0] 13406phy_ready
Definition: ahci_fsm.v:50
axi_ahci_regs.14087afi_cache_set
14087afi_cache_set
Definition: axi_ahci_regs.v:120
ahci_top.13985debug_fis_end_w
13985debug_fis_end_wwire
Definition: ahci_top.v:690
ahci_dma.12883afi_arid
[ 5:0] 12883afi_arid
Definition: ahci_dma.v:133
ahci_top.13966ssts_spd_gen3
13966ssts_spd_gen3wire
Definition: ahci_top.v:468
datascope_timing.14018write_tag_w
14018write_tag_wwire
Definition: ahci_top.v:1253
datascope_timing.14032pre_we_r
14032pre_we_rreg
Definition: ahci_top.v:1271
ahci_top.13691ADDRESS_BITS
13691ADDRESS_BITS10
Definition: ahci_top.v:33
ahci_fsm.13513last_jump_addr
reg [ 9:0] 13513last_jump_addr
Definition: ahci_fsm.v:247
ahci_fsm.13449sctl_det
[3:0] 13449sctl_det
Definition: ahci_fsm.v:138
ahci_top.13831datascope_we
13831datascope_wewire
Definition: ahci_top.v:221
ahci_top.13725arlen
[ 3:0] 13725arlen
Definition: ahci_top.v:75
ahci_top.13955sirq_PS
13955sirq_PSwire
Definition: ahci_top.v:449
ahci_top.13854dma_prd_start
13854dma_prd_startwire
Definition: ahci_top.v:273
axi_ahci_regs.14045awburst
[ 1:0] 14045awburst
Definition: axi_ahci_regs.v:61
ahci_top.13763afi_arcache
[ 3:0] 13763afi_arcache
Definition: ahci_top.v:122
ahci_fis_transmit.13323ch_cfl
[4:0] 13323ch_cfl
Definition: ahci_fis_transmit.v:70
ahci_top.13839regs_re_ftransmit
13839regs_re_ftransmitwire[1:0]
Definition: ahci_top.v:238
ahci_top.13989DATA_TYPE_FIS_HEAD
13989DATA_TYPE_FIS_HEAD1
Definition: ahci_top.v:696
ahci_fis_receive.13218reg_we
reg 13218reg_we
Definition: ahci_fis_receive.v:113
ahci_fis_transmit.13318ch_b
13318ch_b
Definition: ahci_fis_transmit.v:65
ahci_top.13954sirq_DS
13954sirq_DSwire
Definition: ahci_top.v:448
ahci_dma.12890afi_arqos
[ 3:0] 12890afi_arqos
Definition: ahci_dma.v:140
ahci_top.13906frcv_ferr
13906frcv_ferrwire
Definition: ahci_top.v:346
ahci_top.13764afi_arprot
[ 2:0] 13764afi_arprot
Definition: ahci_top.v:123
ahci_top.13957serr_diag_X
13957serr_diag_Xwire
Definition: ahci_top.v:454
ahci_ctrl_stat.12703pcmd_clear_bsy_drq
12703pcmd_clear_bsy_drq
Definition: ahci_ctrl_stat.v:75
ahci_top.13977hba_rst_done
13977hba_rst_donewire
Definition: ahci_top.v:483
ahci_ctrl_stat.12702pcmd_fre
12702pcmd_fre
Definition: ahci_ctrl_stat.v:74
ahci_top.13800serr_DT
13800serr_DT
Definition: ahci_top.v:171
ahci_top.13811serr_EM
13811serr_EM
Definition: ahci_top.v:184
ahci_fsm.13431sirq_DS
13431sirq_DS
Definition: ahci_fsm.v:106
ahci_top.13823drp_di
[15:0] 13823drp_di
Definition: ahci_top.v:207
ahci_fsm.13509ch_p
13509ch_p
Definition: ahci_fsm.v:241
ahci_fsm.13411set_offline
13411set_offline
Definition: ahci_fsm.v:55
ahci_fis_transmit.13341dma_re
13341dma_re
Definition: ahci_fis_transmit.v:100
ahci_top.13971ssts_det
13971ssts_detwire[3:0]
Definition: ahci_top.v:474
ahci_top.13783d2h_type
[ 1:0] 13783d2h_type
Definition: ahci_top.v:148
ahci_top.13972sctl_det
13972sctl_detwire[3:0]
Definition: ahci_top.v:477
ahci_top.13904frcv_ok
13904frcv_okwire
Definition: ahci_top.v:344
ahci_fis_receive.13227debug_data_in_ready
13227debug_data_in_ready
Definition: ahci_fis_receive.v:126
ahci_top.13797x_rdy_collision
13797x_rdy_collision
Definition: ahci_top.v:165
ahci_fis_receive.13214xfer_cntr
[31:2] 13214xfer_cntr
Definition: ahci_fis_receive.v:104
ahci_fis_receive.13209dma_d
reg 13209dma_d
Definition: ahci_fis_receive.v:98
axi_ahci_regs.14107datascope1_di
[31:0] 14107datascope1_di
Definition: axi_ahci_regs.v:145
ahci_dma.12863afi_awlen
[ 3:0] 12863afi_awlen
Definition: ahci_dma.v:108
ahci_dma.12873afi_bvalid
12873afi_bvalid
Definition: ahci_dma.v:120
datascope_timing.14026fis_data
14026fis_datareg[31:0]
Definition: ahci_top.v:1261
ahci_top.13690READ_CT_LATENCY
13690READ_CT_LATENCY2
Definition: ahci_top.v:32
axi_ahci_regs.14092debug_in2
[31:0] 14092debug_in2
Definition: axi_ahci_regs.v:125
ahci_fis_receive.13193clear_bsy_drq
13193clear_bsy_drq
Definition: ahci_fis_receive.v:72
ahci_top.13849regs_din
13849regs_dinwire[31:0]
Definition: ahci_top.v:260
ahci_top.13934was_port_rst
13934was_port_rstwire
Definition: ahci_top.v:402
ahci_top.13952sirq_UF
13952sirq_UFwire
Definition: ahci_top.v:446
ahci_dma.12899afi_rdissuecap1en
12899afi_rdissuecap1en
Definition: ahci_dma.v:151
ahci_top.13801serr_DS
13801serr_DS
Definition: ahci_top.v:172
ahci_fis_transmit.13320ch_p
13320ch_p
Definition: ahci_fis_transmit.v:67
axi_ahci_regs.14067rlast
14067rlast
Definition: axi_ahci_regs.v:87
ahci_fsm.13483clear_bsy_set_drq
13483clear_bsy_set_drq
Definition: ahci_fsm.v:192
ahci_top.13995was_good_bad_prev
13995was_good_bad_prevreg
Definition: ahci_top.v:703
ahci_dma.12855extra_din
12855extra_din
Definition: ahci_dma.v:97
ahci_ctrl_stat.12713sirq_PRC
12713sirq_PRC
Definition: ahci_ctrl_stat.v:89
ahci_ctrl_stat.12732serr_EM
12732serr_EM
Definition: ahci_ctrl_stat.v:113
datascope_timing.14007h2d_valid
14007h2d_valid
Definition: ahci_top.v:1234
ahci_top.13916xfer_cntr
13916xfer_cntrwire[31:2]
Definition: ahci_top.v:370
ahci_ctrl_stat.12749sctl_ipm
reg [3:0] 12749sctl_ipm
Definition: ahci_ctrl_stat.v:137
ahci_top.13890frcv_get_ignore
13890frcv_get_ignorewire
Definition: ahci_top.v:324
ahci_top.13746afi_wvalid
13746afi_wvalid
Definition: ahci_top.v:101
ahci_ctrl_stat.12680was_port_rst
12680was_port_rst
Definition: ahci_ctrl_stat.v:36
ahci_dma.12834set_axi_wr_cache_mode
12834set_axi_wr_cache_mode
Definition: ahci_dma.v:63
ahci_fsm.13475fis_ferr
13475fis_ferr
Definition: ahci_fsm.v:177
ahci_top.13875dma_dav
13875dma_davwire
Definition: ahci_top.v:301
ahci_top.13830datascope_waddr
13830datascope_waddrwire[ADDRESS_BITS-1:0]
Definition: ahci_top.v:220
ahci_top.13765afi_arlen
[ 3:0] 13765afi_arlen
Definition: ahci_top.v:124
ahci_dma.12848sys_out
[31:0] 12848sys_out
Definition: ahci_dma.v:86
ahci_fis_transmit.13303fetch_cmd
13303fetch_cmd
Definition: ahci_fis_transmit.v:40
ahci_dma.12829cmd_start
12829cmd_start
Definition: ahci_dma.v:55
ahci_top.13897frcv_set_sts_7f
13897frcv_set_sts_7fwire
Definition: ahci_top.v:335
ahci_fsm.13455dma_prd_irq_clear
13455dma_prd_irq_clear
Definition: ahci_fsm.v:149
ahci_top.13871dma_abort_busy
13871dma_abort_busywire
Definition: ahci_top.v:296
ahci_ctrl_stat.12742ssts_spd_gen2
12742ssts_spd_gen2
Definition: ahci_ctrl_stat.v:127
ahci_top.13734afi_awaddr
[31:0] 13734afi_awaddr
Definition: ahci_top.v:88
axi_ahci_regs.14043awlen
[ 3:0] 14043awlen
Definition: axi_ahci_regs.v:59
ahci_ctrl_stat.12741ssts_spd_gen1
12741ssts_spd_gen1
Definition: ahci_ctrl_stat.v:126
ahci_dma.12843cmd_busy
reg 12843cmd_busy
Definition: ahci_dma.v:79
ahci_top.13902frcv_busy
13902frcv_busywire
Definition: ahci_top.v:342
ahci_fsm.13501atapi_xmit
13501atapi_xmit
Definition: ahci_fsm.v:226
ahci_top.13862set_axi_cache_mode
13862set_axi_cache_modewire
Definition: ahci_top.v:285
ahci_top.13943pcmd_st
13943pcmd_stwire
Definition: ahci_top.v:435
ahci_ctrl_stat.12758irq
reg 12758irq
Definition: ahci_ctrl_stat.v:152
ahci_fis_transmit.13306atapi_xmit
13306atapi_xmit
Definition: ahci_fis_transmit.v:45
ahci_top.13779h2d_type
[ 1:0] 13779h2d_type
Definition: ahci_top.v:142
ahci_top.13799send_R_ERR
13799send_R_ERR
Definition: ahci_top.v:168
ahci_top.13781h2d_ready
13781h2d_ready
Definition: ahci_top.v:144
ahci_fis_transmit.13313syncesc_recv
13313syncesc_recv
Definition: ahci_fis_transmit.v:59
ahci_dma.12828dev_wr
12828dev_wr
Definition: ahci_dma.v:54
ahci_fis_receive.13219reg_data
reg [31:0] 13219reg_data
Definition: ahci_fis_receive.v:114
ahci_top.13728rdata
[31:0] 13728rdata
Definition: ahci_top.v:79
axi_ahci_regs.14065rready
14065rready
Definition: axi_ahci_regs.v:85
ahci_ctrl_stat.12733serr_EI
12733serr_EI
Definition: ahci_ctrl_stat.v:114
ahci_fsm.13421pcmd_st_cleared
13421pcmd_st_cleared
Definition: ahci_fsm.v:93
ahci_top.ahci_fis_receive
ahci_fis_receive_i ahci_fis_receive
Definition: ahci_top.v:1000
ahci_ctrl_stat.12692update_ssts
12692update_ssts
Definition: ahci_ctrl_stat.v:57
ahci_fsm.13415update_all
13415update_all
Definition: ahci_fsm.v:68
ahci_fsm.13484set_bsy
13484set_bsy
Definition: ahci_fsm.v:194
datascope_timing.14031pre_we_w
14031pre_we_wwire
Definition: ahci_top.v:1270
ahci_fsm.13466get_psfis
13466get_psfis
Definition: ahci_fsm.v:167
ahci_fis_receive.13184fis_extra
13184fis_extra
Definition: ahci_fis_receive.v:62
ahci_fsm.13472get_fis_done
13472get_fis_done
Definition: ahci_fsm.v:174
ahci_fsm.13450sctl_det_changed
13450sctl_det_changed
Definition: ahci_fsm.v:139
ahci_top.13877last_h2d_data
13877last_h2d_datawire
Definition: ahci_top.v:303
datascope_timing.14017punch_tag
14017punch_tagreg[2:0]
Definition: ahci_top.v:1252
ahci_top.13924fsnd_pCmdToIssue
13924fsnd_pCmdToIssuewire
Definition: ahci_top.v:389
ahci_fsm.13428sirq_DP
13428sirq_DP
Definition: ahci_fsm.v:103
ahci_fsm.13433sirq_DHR
13433sirq_DHR
Definition: ahci_fsm.v:108
ahci_top.13946sirq_IF
13946sirq_IFwire
Definition: ahci_top.v:440
ahci_fsm.13417pcmd_cr_set
13417pcmd_cr_set
Definition: ahci_fsm.v:84
ahci_ctrl_stat.12709sirq_TFE
12709sirq_TFE
Definition: ahci_ctrl_stat.v:85
ahci_fis_receive.13170fis_first_flush
13170fis_first_flush
Definition: ahci_fis_receive.v:47
ahci_top.13868dma_prd_irq_pend
13868dma_prd_irq_pendwire
Definition: ahci_top.v:292
ahci_top.13933was_hba_rst
13933was_hba_rstwire
Definition: ahci_top.v:401
ahci_top.13772afi_rid
[ 5:0] 13772afi_rid
Definition: ahci_top.v:132
ahci_top.13948sirq_OF
13948sirq_OFwire
Definition: ahci_top.v:442
ahci_ctrl_stat.12718sirq_DS
12718sirq_DS
Definition: ahci_ctrl_stat.v:94
ahci_top.13938pcmd_cr_set
13938pcmd_cr_setwire
Definition: ahci_top.v:426
datascope_timing.14004soft_write_en
14004soft_write_en
Definition: ahci_top.v:1229
ahci_fsm.13456dma_prd_irq_pend
13456dma_prd_irq_pend
Definition: ahci_fsm.v:150
ahci_fis_receive.13199decr_dwcr
13199decr_dwcr
Definition: ahci_fis_receive.v:79
ahci_top.13771afi_rready
13771afi_rready
Definition: ahci_top.v:131
ahci_fis_receive.13208dma_a
reg 13208dma_a
Definition: ahci_fis_receive.v:97
ahci_top.13923fsnd_clearCmdToIssue
13923fsnd_clearCmdToIssuewire
Definition: ahci_top.v:387
ahci_fsm.13401aclk
13401aclk
Definition: ahci_fsm.v:42
ahci_fsm.13410cominit_got
13410cominit_got
Definition: ahci_fsm.v:54
ahci_ctrl_stat.12689update_busy
12689update_busy
Definition: ahci_ctrl_stat.v:53
ahci_top.13705awvalid
13705awvalid
Definition: ahci_top.v:52
ahci_fsm.13511ch_a
13511ch_a
Definition: ahci_fsm.v:243
axi_ahci_regs.14095drp_we
reg 14095drp_we
Definition: axi_ahci_regs.v:129
ahci_top.13738afi_awlock
[ 1:0] 13738afi_awlock
Definition: ahci_top.v:92
ahci_ctrl_stat.12712sirq_OF
12712sirq_OF
Definition: ahci_ctrl_stat.v:88
ahci_fis_receive.13200decr_dwcw
13200decr_dwcw
Definition: ahci_fis_receive.v:80
ahci_top.13826xclk_period
[FREQ_METER_WIDTH - 1:0] 13826xclk_period
Definition: ahci_top.v:211
ahci_fsm.13494dma_a
13494dma_a
Definition: ahci_fsm.v:209
ahci_top.13859fsm_pgm_wd
13859fsm_pgm_wdwire
Definition: ahci_top.v:280
axi_ahci_regs.14103datascope_di
[31:0] 14103datascope_di
Definition: axi_ahci_regs.v:140