30 // parameter PREFETCH_ALWAYS = 0, 31 parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen 32 // parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen 33 parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle) 37 input mclk,
// for command/status 38 input was_hba_rst,
// last reset was hba reset (not counting system reset) 41 // Writing FSM program memory 44 input [
17:
0]
pgm_ad,
// @aclk, address/data to program the AHCI FSM 45 input pgm_wa,
// @aclk, address strobe to program the AHCI FSM 46 input pgm_wd,
// @aclk, data strobe to program the AHCI FSM 49 // direct communication with transposrt, link and phy layers 50 input [
1:
0]
phy_ready,
// goes up after comreset,cominit, align, ..., showing speed 56 // input x_rdy_collision, // X_RDY/X_RDY collision on interface 57 output send_R_OK,
// Should it be originated in this layer SM? 62 // Communication with ahci_ctrl_stat (some are not needed) 63 // update register inputs (will write to register memory current value of the corresponding register) 64 output pfsm_started,
// H: FSM done, P: FSM started (enable sensing pcmd_st_cleared) 65 // update register inputs (will write to register memory current value of the corresponding register) 66 // Removing - such updates are always done when startimng new state 67 /// input update_pending, 70 // output update_gis, // these following individual may be unneeded - just use universal update_all 72 // output update_ssts, 73 // output update_serr, 74 // output update_pcmd, 76 /// input st01_pending, // software turned PxCMD.ST from 0 to 1 - detected in the loop 77 /// input st10_pending, // software turned PxCMD.ST from 1 to 0 - generates port reset 78 /// output st_pending_reset,// reset both st01_pending and st10_pending 81 /// output pcmd_clear_icc, // clear PxCMD.ICC field 82 /// output pcmd_esp, // external SATA port (just forward value) 83 /// input pcmd_cr, // command list run - current 86 // output pcmd_fr, // ahci_fis_receive:get_fis_busy 87 /// output pcmd_clear_bsy_drq, // == ahci_fis_receive:clear_bsy_drq 89 // Command List override, not yet implemented (optional), keeping @SuppressWarnings VEditor 90 input pcmd_clo,
//RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit 91 /// output pcmd_clear_st, // RW clear ST (start) bit Seems it is software controlled only 97 output sirq_TFE,
// RWC: Task File Error Status 98 output sirq_IF,
// RWC: Interface Fatal Error Status (sect. 6.1.2) 99 output sirq_INF,
// RWC: Interface Non-Fatal Error Status (sect. 6.1.2) 102 output sirq_PC,
// RO: Port Connect Change Status 103 output sirq_DP,
// RWC: Descriptor Processed with "I" bit on 105 output sirq_SDB,
// RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set 106 output sirq_DS,
// RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set 107 output sirq_PS,
// RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set 108 output sirq_DHR,
// RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set 109 // SCR1:SError (only inputs that are not available in sirq_* ones 112 // 5.3.2.3 P:NotRunning.8 - can not be implemented now, keeping @SuppressWarnings VEditor 118 output ssts_ipm_dnp,
// device not present or communication not established 124 output ssts_spd_dnp,
// device not present or communication not established 129 output ssts_det_ndnp,
// no device detected, phy communication not established 130 output ssts_det_dnp,
// device detected, but phy communication not established 131 output ssts_det_dp,
// device detected, phy communication established 133 input [
3:
0]
ssts_det,
// current value of PxSSTS.DET 135 // SCR2:SControl (written by software only) 136 /// input [3:0] sctl_ipm, // Interface power management transitions allowed 137 /// input [3:0] sctl_spd, // Interface maximal speed 138 input [
3:
0]
sctl_det,
// Device detection initialization requested 147 // inputs from the DMA engine 148 /// input dma_prd_done, // output (finished next prd) 150 input dma_prd_irq_pend,
// prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK 152 /// input dma_cmd_done, // output (last PRD is over) 154 input dma_abort_done,
// if abort is not needed, will generate dma_abort_done just next cycle 156 // Communication with ahci_fis_receive (some are unused) 161 input fis_first_vld,
// fis_first contains valid FIS header, reset by 'get_*' 162 input [
7:
0]
fis_type,
// FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld' 163 input [
7:
0]
bist_bits,
// bits that define built-in self test 172 output get_ignore,
// ignore whatever FIS (use for DMA activate too?) 173 // input get_fis_busy, // busy processing FIS 174 input get_fis_done,
// done processing FIS (see fis_ok, fis_err, fis_ferr) 175 input fis_ok,
// FIS done, checksum OK reset by starting a new get FIS 176 input fis_err,
// FIS done, checksum ERROR reset by starting a new get FIS 177 input fis_ferr,
// FIS done, fatal error - FIS too long 178 input fis_extra,
// more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency 181 /// input pUpdateSig, // state variable 182 /// input sig_available, // device signature available 186 // next commands use register address/data/we for 1 clock cycle - after next to command (commnd - t0, we - t2) 187 output update_err_sts,
// update PxTFD.STS and PxTFD.ERR from the last received regs d2h 188 output update_pio,
// update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update) 196 output set_sts_80,
// set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update 199 output decr_dwcr,
// decrement DMA Xfer counter after read // need pulse to 'update_prdbc' to write to registers 200 output decr_dwcw,
// decrement DMA Xfer counter after write // need pulse to 'update_prdbc' to write to registers 201 // output [11:0] decr_DXC_dw, // decrement value (in DWORDs) 202 input pxcmd_fre,
// control bit enables saving FIS to memory 204 input [
7:
0]
tfd_sts,
// Current PxTFD status field (updated after regFIS and SDB - certain fields) 205 // tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR 206 /// input [7:0] tfd_err, // Current PxTFD error field (updated after regFIS and SDB) 207 input fis_i,
// value of "I" field in received regsD2H or SDB FIS 208 /// input sdb_n, // value of "N" field in received SDB FIS 209 input dma_a,
// value of "A" field in received DMA Setup FIS 210 /// input dma_d, // value of "D" field in received DMA Setup FIS 211 input pio_i,
// value of "I" field in received PIO Setup FIS 212 input pio_d,
// value of "D" field in received PIO Setup FIS 213 /// input [7:0] pio_es, // value of PIO E_Status 214 /// input sactive0, // bit 0 of sActive DWORD received in SDB FIS 215 // Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed 216 /// input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc 219 // Communication with ahci_fis_transmit 220 // Command pulses to execute states 221 output fetch_cmd,
// Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS) 222 // wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd 223 output cfis_xmit,
// transmit command (wait for dma_ct_busy == 0) 224 output dx_xmit,
// send FIS header DWORD, (just 0x46), then forward DMA data 225 // transmit until error, 2048DWords or pDmaXferCnt 232 // output dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output 233 // input syncesc_recv, // These two inputs interrupt transmit 234 // input xmit_err, // 235 input [
2:
0]
dx_err,
// bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command) 237 /// input [15:0] ch_prdtl, // Physical region descriptor table length (in entries, 0 is 0) 238 input ch_c,
// Clear busy upon R_OK for this FIS 239 input ch_b,
// Built-in self test command 240 input ch_r,
// reset - may need to send SYNC escape before this command 241 input ch_p,
// prefetchable - only used with non-zero PRDTL or ATAPI bit set 242 input ch_w,
// Write: system memory -> device 243 input ch_a,
// ATAPI: 1 means device should send PIO setup FIS for ATAPI command 244 input unsolicited_en,
// enable processing of cominit_got and PxERR.DIAG.W interrupts from 245 // this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4 248 /// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal, 249 // maximal is 16 (0x10) 250 /// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048) 253 localparam PCI_Header__ID__DID__ADDR =
'h60;
254 localparam PCI_Header__ID__DID__MASK =
'hffff0000;
255 localparam PCI_Header__ID__DID__DFLT =
'h10000;
257 localparam PCI_Header__ID__VID__ADDR =
'h60;
258 localparam PCI_Header__ID__VID__MASK =
'hffff;
259 localparam PCI_Header__ID__VID__DFLT =
'hfffe;
260 // RW: HBA Interrupt Disable 261 localparam PCI_Header__CMD__ID__ADDR =
'h61;
262 localparam PCI_Header__CMD__ID__MASK =
'h400;
263 localparam PCI_Header__CMD__ID__DFLT =
'h0;
264 // RO: Fast Back-to-Back Enable 265 localparam PCI_Header__CMD__FBE__ADDR =
'h61;
266 localparam PCI_Header__CMD__FBE__MASK =
'h200;
267 localparam PCI_Header__CMD__FBE__DFLT =
'h0;
269 localparam PCI_Header__CMD__SEE__ADDR =
'h61;
270 localparam PCI_Header__CMD__SEE__MASK =
'h100;
271 localparam PCI_Header__CMD__SEE__DFLT =
'h0;
273 localparam PCI_Header__CMD__WCC__ADDR =
'h61;
274 localparam PCI_Header__CMD__WCC__MASK =
'h80;
275 localparam PCI_Header__CMD__WCC__DFLT =
'h0;
276 // RO: Parity Error Response Enable 277 localparam PCI_Header__CMD__PEE__ADDR =
'h61;
278 localparam PCI_Header__CMD__PEE__MASK =
'h40;
279 localparam PCI_Header__CMD__PEE__DFLT =
'h0;
281 localparam PCI_Header__CMD__VGA__ADDR =
'h61;
282 localparam PCI_Header__CMD__VGA__MASK =
'h20;
283 localparam PCI_Header__CMD__VGA__DFLT =
'h0;
285 localparam PCI_Header__CMD__MWIE__ADDR =
'h61;
286 localparam PCI_Header__CMD__MWIE__MASK =
'h10;
287 localparam PCI_Header__CMD__MWIE__DFLT =
'h0;
289 localparam PCI_Header__CMD__SCE__ADDR =
'h61;
290 localparam PCI_Header__CMD__SCE__MASK =
'h8;
291 localparam PCI_Header__CMD__SCE__DFLT =
'h0;
292 // RW: Bus Master Enable (0 - stops any DMA) 293 localparam PCI_Header__CMD__BME__ADDR =
'h61;
294 localparam PCI_Header__CMD__BME__MASK =
'h4;
295 localparam PCI_Header__CMD__BME__DFLT =
'h0;
296 // RW: Memory Space enable (here - always?) 297 localparam PCI_Header__CMD__MSE__ADDR =
'h61;
298 localparam PCI_Header__CMD__MSE__MASK =
'h2;
299 localparam PCI_Header__CMD__MSE__DFLT =
'h0;
300 // RO: Enable IO space access (only for legacy IDE) 301 localparam PCI_Header__CMD__IOSE__ADDR =
'h61;
302 localparam PCI_Header__CMD__IOSE__MASK =
'h1;
303 localparam PCI_Header__CMD__IOSE__DFLT =
'h0;
304 // RWC: Detected Parity Error 305 localparam PCI_Header__STS__DPE__ADDR =
'h61;
306 localparam PCI_Header__STS__DPE__MASK =
'h80000000;
307 localparam PCI_Header__STS__DPE__DFLT =
'h0;
308 // RWC: Signaled System Error (HBA SERR) 309 localparam PCI_Header__STS__SSE__ADDR =
'h61;
310 localparam PCI_Header__STS__SSE__MASK =
'h40000000;
311 localparam PCI_Header__STS__SSE__DFLT =
'h0;
312 // RWC: Received Master Abort 313 localparam PCI_Header__STS__RMA__ADDR =
'h61;
314 localparam PCI_Header__STS__RMA__MASK =
'h20000000;
315 localparam PCI_Header__STS__RMA__DFLT =
'h0;
316 // RWC: Received Target Abort 317 localparam PCI_Header__STS__RTA__ADDR =
'h61;
318 localparam PCI_Header__STS__RTA__MASK =
'h10000000;
319 localparam PCI_Header__STS__RTA__DFLT =
'h0;
320 // RWC: Signaled Target Abort 321 localparam PCI_Header__STS__STA__ADDR =
'h61;
322 localparam PCI_Header__STS__STA__MASK =
'h8000000;
323 localparam PCI_Header__STS__STA__DFLT =
'h0;
324 // RO: PCI DEVSEL Timing 325 localparam PCI_Header__STS__DEVT__ADDR =
'h61;
326 localparam PCI_Header__STS__DEVT__MASK =
'h6000000;
327 localparam PCI_Header__STS__DEVT__DFLT =
'h0;
328 // RWC: Master Data Parity Error Detected 329 localparam PCI_Header__STS__DPD__ADDR =
'h61;
330 localparam PCI_Header__STS__DPD__MASK =
'h1000000;
331 localparam PCI_Header__STS__DPD__DFLT =
'h0;
332 // RO: Fast Back-To-Back Capable 333 localparam PCI_Header__STS__FBC__ADDR =
'h61;
334 localparam PCI_Header__STS__FBC__MASK =
'h800000;
335 localparam PCI_Header__STS__FBC__DFLT =
'h0;
336 // RO: 66 MHz Capable 337 localparam PCI_Header__STS__C66__ADDR =
'h61;
338 localparam PCI_Header__STS__C66__MASK =
'h200000;
339 localparam PCI_Header__STS__C66__DFLT =
'h0;
340 // RO: Capabilities List (PCI power management mandatory) 341 localparam PCI_Header__STS__CL__ADDR =
'h61;
342 localparam PCI_Header__STS__CL__MASK =
'h100000;
343 localparam PCI_Header__STS__CL__DFLT =
'h100000;
344 // RO: Interrupt Status (1 - asserted) 345 localparam PCI_Header__STS__IS__ADDR =
'h61;
346 localparam PCI_Header__STS__IS__MASK =
'h80000;
347 localparam PCI_Header__STS__IS__DFLT =
'h0;
348 // RO: HBA Revision ID 349 localparam PCI_Header__RID__RID__ADDR =
'h62;
350 localparam PCI_Header__RID__RID__MASK =
'hff;
351 localparam PCI_Header__RID__RID__DFLT =
'h2;
352 // RO: Base Class Code: 1 - Mass Storage Device 353 localparam PCI_Header__CC__BCC__ADDR =
'h62;
354 localparam PCI_Header__CC__BCC__MASK =
'hff000000;
355 localparam PCI_Header__CC__BCC__DFLT =
'h1000000;
356 // RO: Sub Class Code: 0x06 - SATA Device 357 localparam PCI_Header__CC__SCC__ADDR =
'h62;
358 localparam PCI_Header__CC__SCC__MASK =
'hff0000;
359 localparam PCI_Header__CC__SCC__DFLT =
'h60000;
360 // RO: Programming Interface: 1 - AHCI HBA major rev 1 361 localparam PCI_Header__CC__PI__ADDR =
'h62;
362 localparam PCI_Header__CC__PI__MASK =
'hff0000;
363 localparam PCI_Header__CC__PI__DFLT =
'h10000;
364 // RW: Cache Line Size 365 localparam PCI_Header__CLS__CLS__ADDR =
'h63;
366 localparam PCI_Header__CLS__CLS__MASK =
'hff;
367 localparam PCI_Header__CLS__CLS__DFLT =
'h0;
368 // RW: Master Latency Timer 369 localparam PCI_Header__MLT__MLT__ADDR =
'h63;
370 localparam PCI_Header__MLT__MLT__MASK =
'hff00;
371 localparam PCI_Header__MLT__MLT__DFLT =
'h0;
372 // RO: Multi-Function Device 373 localparam PCI_Header__HTYPE__MFDT__ADDR =
'h63;
374 localparam PCI_Header__HTYPE__MFDT__MASK =
'h8000;
375 localparam PCI_Header__HTYPE__MFDT__DFLT =
'h0;
376 // RO: Header Layout 0 - HBA uses a target device layout 377 localparam PCI_Header__HTYPE__HL__ADDR =
'h63;
378 localparam PCI_Header__HTYPE__HL__MASK =
'h7f00;
379 localparam PCI_Header__HTYPE__HL__DFLT =
'h0;
380 // RO: AHCI Base Address high bits, normally RW, but here RO to get to MAXIGP1 space 381 localparam PCI_Header__ABAR__BA__ADDR =
'h69;
382 localparam PCI_Header__ABAR__BA__MASK =
'hfffffff0;
383 localparam PCI_Header__ABAR__BA__DFLT =
'h80000000;
384 // RO: Prefetchable (this is not) 385 localparam PCI_Header__ABAR__PF__ADDR =
'h69;
386 localparam PCI_Header__ABAR__PF__MASK =
'h8;
387 localparam PCI_Header__ABAR__PF__DFLT =
'h0;
388 // RO: Type (0 - any 32-bit address, here it is hard-mapped 389 localparam PCI_Header__ABAR__TP__ADDR =
'h69;
390 localparam PCI_Header__ABAR__TP__MASK =
'h6;
391 localparam PCI_Header__ABAR__TP__DFLT =
'h0;
392 // RO: Resource Type Indicator: 0 - memory address 393 localparam PCI_Header__ABAR__RTE__ADDR =
'h69;
394 localparam PCI_Header__ABAR__RTE__MASK =
'h1;
395 localparam PCI_Header__ABAR__RTE__DFLT =
'h0;
397 localparam PCI_Header__SS__SSID__ADDR =
'h6b;
398 localparam PCI_Header__SS__SSID__MASK =
'hffff0000;
399 localparam PCI_Header__SS__SSID__DFLT =
'h10000;
400 // RO: SubSystem Vendor ID 401 localparam PCI_Header__SS__SSVID__ADDR =
'h6b;
402 localparam PCI_Header__SS__SSVID__MASK =
'hffff;
403 localparam PCI_Header__SS__SSVID__DFLT =
'hfffe;
404 // RO: ROM Base Address 405 localparam PCI_Header__EROM__RBA__ADDR =
'h6c;
406 localparam PCI_Header__EROM__RBA__MASK =
'hffffffff;
407 localparam PCI_Header__EROM__RBA__DFLT =
'h0;
408 // RO: Capabilities pointer 409 localparam PCI_Header__CAP__CAP__ADDR =
'h6d;
410 localparam PCI_Header__CAP__CAP__MASK =
'hff;
411 localparam PCI_Header__CAP__CAP__DFLT =
'h40;
413 localparam PCI_Header__INTR__IPIN__ADDR =
'h6f;
414 localparam PCI_Header__INTR__IPIN__MASK =
'hff00;
415 localparam PCI_Header__INTR__IPIN__DFLT =
'h100;
416 // RW: Interrupt Line 417 localparam PCI_Header__INTR__ILINE__ADDR =
'h6f;
418 localparam PCI_Header__INTR__ILINE__MASK =
'hff;
419 localparam PCI_Header__INTR__ILINE__DFLT =
'h0;
421 localparam PCI_Header__MGNT__MGNT__ADDR =
'h6f;
422 localparam PCI_Header__MGNT__MGNT__MASK =
'hff0000;
423 localparam PCI_Header__MGNT__MGNT__DFLT =
'h0;
424 // RO: Maximal Latency 425 localparam PCI_Header__MLAT__MLAT__ADDR =
'h6f;
426 localparam PCI_Header__MLAT__MLAT__MASK =
'hff000000;
427 localparam PCI_Header__MLAT__MLAT__DFLT =
'h0;
428 // RO: Next Capability pointer 429 localparam PMCAP__PID__NEXT__ADDR =
'h70;
430 localparam PMCAP__PID__NEXT__MASK =
'hff00;
431 localparam PMCAP__PID__NEXT__DFLT =
'h0;
432 // RO: This is PCI Power Management Capability 433 localparam PMCAP__PID__CID__ADDR =
'h70;
434 localparam PMCAP__PID__CID__MASK =
'hff;
435 localparam PMCAP__PID__CID__DFLT =
'h1;
436 // RO: PME_SUPPORT bits:'b01000 437 localparam PMCAP__PC__PSUP__ADDR =
'h70;
438 localparam PMCAP__PC__PSUP__MASK =
'hf8000000;
439 localparam PMCAP__PC__PSUP__DFLT =
'h40000000;
440 // RO: D2 Support - no 441 localparam PMCAP__PC__D2S__ADDR =
'h70;
442 localparam PMCAP__PC__D2S__MASK =
'h4000000;
443 localparam PMCAP__PC__D2S__DFLT =
'h0;
444 // RO: D1 Support - no 445 localparam PMCAP__PC__D1S__ADDR =
'h70;
446 localparam PMCAP__PC__D1S__MASK =
'h2000000;
447 localparam PMCAP__PC__D1S__DFLT =
'h0;
448 // RO: Maximal D3cold current 449 localparam PMCAP__PC__AUXC__ADDR =
'h70;
450 localparam PMCAP__PC__AUXC__MASK =
'h1c00000;
451 localparam PMCAP__PC__AUXC__DFLT =
'h0;
452 // RO: Device-specific initialization required 453 localparam PMCAP__PC__DSI__ADDR =
'h70;
454 localparam PMCAP__PC__DSI__MASK =
'h200000;
455 localparam PMCAP__PC__DSI__DFLT =
'h0;
456 // RO: PCI clock required to generate PME 457 localparam PMCAP__PC__PMEC__ADDR =
'h70;
458 localparam PMCAP__PC__PMEC__MASK =
'h80000;
459 localparam PMCAP__PC__PMEC__DFLT =
'h0;
460 // RO: Revision of Power Management Specification support version 461 localparam PMCAP__PC__VS__ADDR =
'h70;
462 localparam PMCAP__PC__VS__MASK =
'h70000;
463 localparam PMCAP__PC__VS__DFLT =
'h0;
464 // RWC: PME Status, set by hardware when HBA generates PME 465 localparam PMCAP__PMCS__PMES__ADDR =
'h71;
466 localparam PMCAP__PMCS__PMES__MASK =
'h8000;
467 localparam PMCAP__PMCS__PMES__DFLT =
'h0;
469 localparam PMCAP__PMCS__PMEE__ADDR =
'h71;
470 localparam PMCAP__PMCS__PMEE__MASK =
'h100;
471 localparam PMCAP__PMCS__PMEE__DFLT =
'h0;
473 localparam PMCAP__PMCS__PS__ADDR =
'h71;
474 localparam PMCAP__PMCS__PS__MASK =
'h3;
475 localparam PMCAP__PMCS__PS__DFLT =
'h0;
476 // RO: Supports 64-bit Addressing - no 477 localparam GHC__CAP__S64A__ADDR =
'h0;
478 localparam GHC__CAP__S64A__MASK =
'h80000000;
479 localparam GHC__CAP__S64A__DFLT =
'h0;
480 // RO: Supports Native Command Queuing - no 481 localparam GHC__CAP__SNCQ__ADDR =
'h0;
482 localparam GHC__CAP__SNCQ__MASK =
'h40000000;
483 localparam GHC__CAP__SNCQ__DFLT =
'h0;
484 // RO: Supports SNotification Register - no 485 localparam GHC__CAP__SSNTF__ADDR =
'h0;
486 localparam GHC__CAP__SSNTF__MASK =
'h20000000;
487 localparam GHC__CAP__SSNTF__DFLT =
'h0;
488 // RO: Supports Mechanical Presence Switch - no 489 localparam GHC__CAP__SMPS__ADDR =
'h0;
490 localparam GHC__CAP__SMPS__MASK =
'h10000000;
491 localparam GHC__CAP__SMPS__DFLT =
'h0;
492 // RO: Supports Staggered Spin-up - no 493 localparam GHC__CAP__SSS__ADDR =
'h0;
494 localparam GHC__CAP__SSS__MASK =
'h8000000;
495 localparam GHC__CAP__SSS__DFLT =
'h0;
496 // RO: Supports Aggressive Link Power Management - no 497 localparam GHC__CAP__SALP__ADDR =
'h0;
498 localparam GHC__CAP__SALP__MASK =
'h4000000;
499 localparam GHC__CAP__SALP__DFLT =
'h0;
500 // RO: Supports Activity LED - no 501 localparam GHC__CAP__SAL__ADDR =
'h0;
502 localparam GHC__CAP__SAL__MASK =
'h2000000;
503 localparam GHC__CAP__SAL__DFLT =
'h0;
504 // RO: Supports Command List Override - no (not capable of clearing BSY and DRQ bits, needs soft reset 505 localparam GHC__CAP__SCLO__ADDR =
'h0;
506 localparam GHC__CAP__SCLO__MASK =
'h1000000;
507 localparam GHC__CAP__SCLO__DFLT =
'h0;
508 // RO: Interface Maximal speed: 2 - Gen2, 3 - Gen3 509 localparam GHC__CAP__ISS__ADDR =
'h0;
510 localparam GHC__CAP__ISS__MASK =
'hf00000;
511 localparam GHC__CAP__ISS__DFLT =
'h200000;
512 // RO: AHCI only (0 - legacy too) 513 localparam GHC__CAP__SAM__ADDR =
'h0;
514 localparam GHC__CAP__SAM__MASK =
'h40000;
515 localparam GHC__CAP__SAM__DFLT =
'h40000;
516 // RO: Supports Port Multiplier - no 517 localparam GHC__CAP__SPM__ADDR =
'h0;
518 localparam GHC__CAP__SPM__MASK =
'h20000;
519 localparam GHC__CAP__SPM__DFLT =
'h0;
520 // RO: Supports FIS-based switching of the Port Multiplier - no 521 localparam GHC__CAP__FBSS__ADDR =
'h0;
522 localparam GHC__CAP__FBSS__MASK =
'h10000;
523 localparam GHC__CAP__FBSS__DFLT =
'h0;
524 // RO: PIO Multiple DRQ block - no 525 localparam GHC__CAP__PMD__ADDR =
'h0;
526 localparam GHC__CAP__PMD__MASK =
'h8000;
527 localparam GHC__CAP__PMD__DFLT =
'h0;
528 // RO: Slumber State Capable - no 529 localparam GHC__CAP__SSC__ADDR =
'h0;
530 localparam GHC__CAP__SSC__MASK =
'h4000;
531 localparam GHC__CAP__SSC__DFLT =
'h0;
532 // RO: Partial State Capable - no 533 localparam GHC__CAP__PSC__ADDR =
'h0;
534 localparam GHC__CAP__PSC__MASK =
'h2000;
535 localparam GHC__CAP__PSC__DFLT =
'h0;
536 // RO: Number of Command Slots, 0-based (0 means 1?) 537 localparam GHC__CAP__NSC__ADDR =
'h0;
538 localparam GHC__CAP__NSC__MASK =
'h1f00;
539 localparam GHC__CAP__NSC__DFLT =
'h0;
540 // RO: Command Completion Coalescing - no 541 localparam GHC__CAP__CCCS__ADDR =
'h0;
542 localparam GHC__CAP__CCCS__MASK =
'h80;
543 localparam GHC__CAP__CCCS__DFLT =
'h0;
544 // RO: Enclosure Management - no 545 localparam GHC__CAP__EMS__ADDR =
'h0;
546 localparam GHC__CAP__EMS__MASK =
'h40;
547 localparam GHC__CAP__EMS__DFLT =
'h0;
548 // RO: External SATA connector - yes 549 localparam GHC__CAP__SXS__ADDR =
'h0;
550 localparam GHC__CAP__SXS__MASK =
'h20;
551 localparam GHC__CAP__SXS__DFLT =
'h20;
552 // RO: Number of Ports, 0-based (0 means 1?) 553 localparam GHC__CAP__NP__ADDR =
'h0;
554 localparam GHC__CAP__NP__MASK =
'h1f;
555 localparam GHC__CAP__NP__DFLT =
'h0;
556 // RO: AHCI enable (0 - legacy) 557 localparam GHC__GHC__AE__ADDR =
'h1;
558 localparam GHC__GHC__AE__MASK =
'h80000000;
559 localparam GHC__GHC__AE__DFLT =
'h80000000;
560 // RO: MSI Revert to Single Message 561 localparam GHC__GHC__MRSM__ADDR =
'h1;
562 localparam GHC__GHC__MRSM__MASK =
'h4;
563 localparam GHC__GHC__MRSM__DFLT =
'h0;
564 // RW: Interrupt Enable (all ports) 565 localparam GHC__GHC__IE__ADDR =
'h1;
566 localparam GHC__GHC__IE__MASK =
'h2;
567 localparam GHC__GHC__IE__DFLT =
'h0;
568 // RW1: HBA reset (COMINIT, ...). Set by software, cleared by hardware, section 10.4.3 569 localparam GHC__GHC__HR__ADDR =
'h1;
570 localparam GHC__GHC__HR__MASK =
'h1;
571 localparam GHC__GHC__HR__DFLT =
'h0;
572 // RWC: Interrupt Pending Status (per port) 573 localparam GHC__IS__IPS__ADDR =
'h2;
574 localparam GHC__IS__IPS__MASK =
'hffffffff;
575 localparam GHC__IS__IPS__DFLT =
'h0;
576 // RO: Ports Implemented 577 localparam GHC__PI__PI__ADDR =
'h3;
578 localparam GHC__PI__PI__MASK =
'hffffffff;
579 localparam GHC__PI__PI__DFLT =
'h1;
580 // RO: AHCI Major Version 1. 581 localparam GHC__VS__MJR__ADDR =
'h4;
582 localparam GHC__VS__MJR__MASK =
'hffff0000;
583 localparam GHC__VS__MJR__DFLT =
'h10000;
584 // RO: AHCI Minor Version 3.1 585 localparam GHC__VS__MNR__ADDR =
'h4;
586 localparam GHC__VS__MNR__MASK =
'hffff;
587 localparam GHC__VS__MNR__DFLT =
'h301;
588 // RO: DevSleep Entrance from Slumber Only 589 localparam GHC__CAP2__DESO__ADDR =
'h9;
590 localparam GHC__CAP2__DESO__MASK =
'h20;
591 localparam GHC__CAP2__DESO__DFLT =
'h0;
592 // RO: Supports Aggressive Device Sleep Management 593 localparam GHC__CAP2__SADM__ADDR =
'h9;
594 localparam GHC__CAP2__SADM__MASK =
'h10;
595 localparam GHC__CAP2__SADM__DFLT =
'h0;
596 // RO: Supports Device Sleep 597 localparam GHC__CAP2__SDS__ADDR =
'h9;
598 localparam GHC__CAP2__SDS__MASK =
'h8;
599 localparam GHC__CAP2__SDS__DFLT =
'h0;
600 // RO: Automatic Partial to Slumber Transitions 601 localparam GHC__CAP2__APST__ADDR =
'h9;
602 localparam GHC__CAP2__APST__MASK =
'h4;
603 localparam GHC__CAP2__APST__DFLT =
'h0;
604 // RO: NVMHCI Present (section 10.15) 605 localparam GHC__CAP2__NVMP__ADDR =
'h9;
606 localparam GHC__CAP2__NVMP__MASK =
'h2;
607 localparam GHC__CAP2__NVMP__DFLT =
'h0;
608 // RO: BIOS/OS Handoff - not supported 609 localparam GHC__CAP2__BOH__ADDR =
'h9;
610 localparam GHC__CAP2__BOH__MASK =
'h1;
611 localparam GHC__CAP2__BOH__DFLT =
'h0;
612 // RW: Command List Base Address (1KB aligned) 613 localparam HBA_PORT__PxCLB__CLB__ADDR =
'h40;
614 localparam HBA_PORT__PxCLB__CLB__MASK =
'hfffffc00;
615 localparam HBA_PORT__PxCLB__CLB__DFLT =
'h80000800;
616 // RW: Command List Base Address (1KB aligned) 617 localparam HBA_PORT__PxFB__CLB__ADDR =
'h42;
618 localparam HBA_PORT__PxFB__CLB__MASK =
'hffffff00;
619 localparam HBA_PORT__PxFB__CLB__DFLT =
'h80000c00;
620 // RWC: Cold Port Detect Status 621 localparam HBA_PORT__PxIS__CPDS__ADDR =
'h44;
622 localparam HBA_PORT__PxIS__CPDS__MASK =
'h80000000;
623 localparam HBA_PORT__PxIS__CPDS__DFLT =
'h0;
624 // RWC: Task File Error Status 625 localparam HBA_PORT__PxIS__TFES__ADDR =
'h44;
626 localparam HBA_PORT__PxIS__TFES__MASK =
'h40000000;
627 localparam HBA_PORT__PxIS__TFES__DFLT =
'h0;
628 // RWC: Host Bus (PCI) Fatal error 629 localparam HBA_PORT__PxIS__HBFS__ADDR =
'h44;
630 localparam HBA_PORT__PxIS__HBFS__MASK =
'h20000000;
631 localparam HBA_PORT__PxIS__HBFS__DFLT =
'h0;
632 // RWC: ECC error R/W system memory 633 localparam HBA_PORT__PxIS__HBDS__ADDR =
'h44;
634 localparam HBA_PORT__PxIS__HBDS__MASK =
'h10000000;
635 localparam HBA_PORT__PxIS__HBDS__DFLT =
'h0;
636 // RWC: Interface Fatal Error Status (sect. 6.1.2) 637 localparam HBA_PORT__PxIS__IFS__ADDR =
'h44;
638 localparam HBA_PORT__PxIS__IFS__MASK =
'h8000000;
639 localparam HBA_PORT__PxIS__IFS__DFLT =
'h0;
640 // RWC: Interface Non-Fatal Error Status (sect. 6.1.2) 641 localparam HBA_PORT__PxIS__INFS__ADDR =
'h44;
642 localparam HBA_PORT__PxIS__INFS__MASK =
'h4000000;
643 localparam HBA_PORT__PxIS__INFS__DFLT =
'h0;
644 // RWC: Overflow Status 645 localparam HBA_PORT__PxIS__OFS__ADDR =
'h44;
646 localparam HBA_PORT__PxIS__OFS__MASK =
'h1000000;
647 localparam HBA_PORT__PxIS__OFS__DFLT =
'h0;
648 // RWC: Incorrect Port Multiplier Status 649 localparam HBA_PORT__PxIS__IPMS__ADDR =
'h44;
650 localparam HBA_PORT__PxIS__IPMS__MASK =
'h800000;
651 localparam HBA_PORT__PxIS__IPMS__DFLT =
'h0;
652 // RO: PhyRdy changed Status 653 localparam HBA_PORT__PxIS__PRCS__ADDR =
'h44;
654 localparam HBA_PORT__PxIS__PRCS__MASK =
'h400000;
655 localparam HBA_PORT__PxIS__PRCS__DFLT =
'h0;
656 // RWC: Device Mechanical Presence Status 657 localparam HBA_PORT__PxIS__DMPS__ADDR =
'h44;
658 localparam HBA_PORT__PxIS__DMPS__MASK =
'h80;
659 localparam HBA_PORT__PxIS__DMPS__DFLT =
'h0;
660 // RO: Port Connect Change Status 661 localparam HBA_PORT__PxIS__PCS__ADDR =
'h44;
662 localparam HBA_PORT__PxIS__PCS__MASK =
'h40;
663 localparam HBA_PORT__PxIS__PCS__DFLT =
'h0;
664 // RWC: Descriptor Processed 665 localparam HBA_PORT__PxIS__DPS__ADDR =
'h44;
666 localparam HBA_PORT__PxIS__DPS__MASK =
'h20;
667 localparam HBA_PORT__PxIS__DPS__DFLT =
'h0;
669 localparam HBA_PORT__PxIS__UFS__ADDR =
'h44;
670 localparam HBA_PORT__PxIS__UFS__MASK =
'h10;
671 localparam HBA_PORT__PxIS__UFS__DFLT =
'h0;
672 // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set 673 localparam HBA_PORT__PxIS__SDBS__ADDR =
'h44;
674 localparam HBA_PORT__PxIS__SDBS__MASK =
'h8;
675 localparam HBA_PORT__PxIS__SDBS__DFLT =
'h0;
676 // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set 677 localparam HBA_PORT__PxIS__DSS__ADDR =
'h44;
678 localparam HBA_PORT__PxIS__DSS__MASK =
'h4;
679 localparam HBA_PORT__PxIS__DSS__DFLT =
'h0;
680 // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set 681 localparam HBA_PORT__PxIS__PSS__ADDR =
'h44;
682 localparam HBA_PORT__PxIS__PSS__MASK =
'h2;
683 localparam HBA_PORT__PxIS__PSS__DFLT =
'h0;
684 // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set 685 localparam HBA_PORT__PxIS__DHRS__ADDR =
'h44;
686 localparam HBA_PORT__PxIS__DHRS__MASK =
'h1;
687 localparam HBA_PORT__PxIS__DHRS__DFLT =
'h0;
688 // RW: Cold Port Detect Enable 689 localparam HBA_PORT__PxIE__CPDE__ADDR =
'h45;
690 localparam HBA_PORT__PxIE__CPDE__MASK =
'h80000000;
691 localparam HBA_PORT__PxIE__CPDE__DFLT =
'h0;
692 // RW: Task File Error Enable 693 localparam HBA_PORT__PxIE__TFEE__ADDR =
'h45;
694 localparam HBA_PORT__PxIE__TFEE__MASK =
'h40000000;
695 localparam HBA_PORT__PxIE__TFEE__DFLT =
'h0;
696 // RW: Host Bus (PCI) Fatal Error Enable 697 localparam HBA_PORT__PxIE__HBFE__ADDR =
'h45;
698 localparam HBA_PORT__PxIE__HBFE__MASK =
'h20000000;
699 localparam HBA_PORT__PxIE__HBFE__DFLT =
'h0;
700 // RW: ECC Error R/W System Memory Enable 701 localparam HBA_PORT__PxIE__HBDE__ADDR =
'h45;
702 localparam HBA_PORT__PxIE__HBDE__MASK =
'h10000000;
703 localparam HBA_PORT__PxIE__HBDE__DFLT =
'h0;
704 // RW: Interface Fatal Error Enable (sect. 6.1.2) 705 localparam HBA_PORT__PxIE__IFE__ADDR =
'h45;
706 localparam HBA_PORT__PxIE__IFE__MASK =
'h8000000;
707 localparam HBA_PORT__PxIE__IFE__DFLT =
'h0;
708 // RW: Interface Non-Fatal Error Enable (sect. 6.1.2) 709 localparam HBA_PORT__PxIE__INFE__ADDR =
'h45;
710 localparam HBA_PORT__PxIE__INFE__MASK =
'h4000000;
711 localparam HBA_PORT__PxIE__INFE__DFLT =
'h0;
712 // RW: Overflow Enable 713 localparam HBA_PORT__PxIE__OFE__ADDR =
'h45;
714 localparam HBA_PORT__PxIE__OFE__MASK =
'h1000000;
715 localparam HBA_PORT__PxIE__OFE__DFLT =
'h0;
716 // RW: Incorrect Port Multiplier Enable 717 localparam HBA_PORT__PxIE__IPME__ADDR =
'h45;
718 localparam HBA_PORT__PxIE__IPME__MASK =
'h800000;
719 localparam HBA_PORT__PxIE__IPME__DFLT =
'h0;
720 // RW: PhyRdy changed Enable 721 localparam HBA_PORT__PxIE__PRCE__ADDR =
'h45;
722 localparam HBA_PORT__PxIE__PRCE__MASK =
'h400000;
723 localparam HBA_PORT__PxIE__PRCE__DFLT =
'h0;
724 // RO: Device Mechanical Presence Interrupt Enable 725 localparam HBA_PORT__PxIE__DMPE__ADDR =
'h45;
726 localparam HBA_PORT__PxIE__DMPE__MASK =
'h80;
727 localparam HBA_PORT__PxIE__DMPE__DFLT =
'h0;
728 // RW: Port Connect Change Interrupt Enable 729 localparam HBA_PORT__PxIE__PCE__ADDR =
'h45;
730 localparam HBA_PORT__PxIE__PCE__MASK =
'h40;
731 localparam HBA_PORT__PxIE__PCE__DFLT =
'h0;
732 // RW: Descriptor Processed Interrupt Enable 733 localparam HBA_PORT__PxIE__DPE__ADDR =
'h45;
734 localparam HBA_PORT__PxIE__DPE__MASK =
'h20;
735 localparam HBA_PORT__PxIE__DPE__DFLT =
'h0;
737 localparam HBA_PORT__PxIE__UFE__ADDR =
'h45;
738 localparam HBA_PORT__PxIE__UFE__MASK =
'h10;
739 localparam HBA_PORT__PxIE__UFE__DFLT =
'h0;
740 // RW: Device Bits Interrupt Enable 741 localparam HBA_PORT__PxIE__SDBE__ADDR =
'h45;
742 localparam HBA_PORT__PxIE__SDBE__MASK =
'h8;
743 localparam HBA_PORT__PxIE__SDBE__DFLT =
'h0;
744 // RW: DMA Setup FIS Interrupt Enable 745 localparam HBA_PORT__PxIE__DSE__ADDR =
'h45;
746 localparam HBA_PORT__PxIE__DSE__MASK =
'h4;
747 localparam HBA_PORT__PxIE__DSE__DFLT =
'h0;
748 // RW: PIO Setup FIS Interrupt Enable 749 localparam HBA_PORT__PxIE__PSE__ADDR =
'h45;
750 localparam HBA_PORT__PxIE__PSE__MASK =
'h2;
751 localparam HBA_PORT__PxIE__PSE__DFLT =
'h0;
752 // RW: D2H Register FIS Interrupt Enable 753 localparam HBA_PORT__PxIE__DHRE__ADDR =
'h45;
754 localparam HBA_PORT__PxIE__DHRE__MASK =
'h1;
755 localparam HBA_PORT__PxIE__DHRE__DFLT =
'h0;
756 // RW: Interface Communication Control 757 localparam HBA_PORT__PxCMD__ICC__ADDR =
'h46;
758 localparam HBA_PORT__PxCMD__ICC__MASK =
'hf0000000;
759 localparam HBA_PORT__PxCMD__ICC__DFLT =
'h0;
760 // RO: Aggressive Slumber/Partial - not implemented 761 localparam HBA_PORT__PxCMD__ASP__ADDR =
'h46;
762 localparam HBA_PORT__PxCMD__ASP__MASK =
'h8000000;
763 localparam HBA_PORT__PxCMD__ASP__DFLT =
'h0;
764 // RO: Aggressive Link Power Management Enable - not implemented 765 localparam HBA_PORT__PxCMD__ALPE__ADDR =
'h46;
766 localparam HBA_PORT__PxCMD__ALPE__MASK =
'h4000000;
767 localparam HBA_PORT__PxCMD__ALPE__DFLT =
'h0;
768 // RW: Drive LED on ATAPI enable 769 localparam HBA_PORT__PxCMD__DLAE__ADDR =
'h46;
770 localparam HBA_PORT__PxCMD__DLAE__MASK =
'h2000000;
771 localparam HBA_PORT__PxCMD__DLAE__DFLT =
'h0;
772 // RW: Device is ATAPI (for activity LED) 773 localparam HBA_PORT__PxCMD__ATAPI__ADDR =
'h46;
774 localparam HBA_PORT__PxCMD__ATAPI__MASK =
'h1000000;
775 localparam HBA_PORT__PxCMD__ATAPI__DFLT =
'h0;
776 // RW: Automatic Partial to Slumber Transitions Enabled 777 localparam HBA_PORT__PxCMD__APSTE__ADDR =
'h46;
778 localparam HBA_PORT__PxCMD__APSTE__MASK =
'h800000;
779 localparam HBA_PORT__PxCMD__APSTE__DFLT =
'h0;
780 // RO: FIS-Based Switching Capable Port - not implemented 781 localparam HBA_PORT__PxCMD__FBSCP__ADDR =
'h46;
782 localparam HBA_PORT__PxCMD__FBSCP__MASK =
'h400000;
783 localparam HBA_PORT__PxCMD__FBSCP__DFLT =
'h0;
784 // RO: External SATA port 785 localparam HBA_PORT__PxCMD__ESP__ADDR =
'h46;
786 localparam HBA_PORT__PxCMD__ESP__MASK =
'h200000;
787 localparam HBA_PORT__PxCMD__ESP__DFLT =
'h200000;
788 // RO: Cold Presence Detection 789 localparam HBA_PORT__PxCMD__CPD__ADDR =
'h46;
790 localparam HBA_PORT__PxCMD__CPD__MASK =
'h100000;
791 localparam HBA_PORT__PxCMD__CPD__DFLT =
'h0;
792 // RO: Mechanical Presence Switch Attached to Port 793 localparam HBA_PORT__PxCMD__MPSP__ADDR =
'h46;
794 localparam HBA_PORT__PxCMD__MPSP__MASK =
'h80000;
795 localparam HBA_PORT__PxCMD__MPSP__DFLT =
'h0;
796 // RO: Hot Plug Capable Port 797 localparam HBA_PORT__PxCMD__HPCP__ADDR =
'h46;
798 localparam HBA_PORT__PxCMD__HPCP__MASK =
'h40000;
799 localparam HBA_PORT__PxCMD__HPCP__DFLT =
'h40000;
800 // RW: Port Multiplier Attached - not implemented (software should write this bit) 801 localparam HBA_PORT__PxCMD__PMA__ADDR =
'h46;
802 localparam HBA_PORT__PxCMD__PMA__MASK =
'h20000;
803 localparam HBA_PORT__PxCMD__PMA__DFLT =
'h0;
804 // RO: Cold Presence State 805 localparam HBA_PORT__PxCMD__CPS__ADDR =
'h46;
806 localparam HBA_PORT__PxCMD__CPS__MASK =
'h10000;
807 localparam HBA_PORT__PxCMD__CPS__DFLT =
'h0;
808 // RO: Command List Running (section 5.3.2) 809 localparam HBA_PORT__PxCMD__CR__ADDR =
'h46;
810 localparam HBA_PORT__PxCMD__CR__MASK =
'h8000;
811 localparam HBA_PORT__PxCMD__CR__DFLT =
'h0;
812 // RO: FIS Receive Running (section 10.3.2) 813 localparam HBA_PORT__PxCMD__FR__ADDR =
'h46;
814 localparam HBA_PORT__PxCMD__FR__MASK =
'h4000;
815 localparam HBA_PORT__PxCMD__FR__DFLT =
'h0;
816 // RO: Mechanical Presence Switch State 817 localparam HBA_PORT__PxCMD__MPSS__ADDR =
'h46;
818 localparam HBA_PORT__PxCMD__MPSS__MASK =
'h2000;
819 localparam HBA_PORT__PxCMD__MPSS__DFLT =
'h0;
820 // RO: Current Command Slot (when PxCMD.ST 1-> ) should be reset to 0, when 0->1 - highest priority is 0 821 localparam HBA_PORT__PxCMD__CCS__ADDR =
'h46;
822 localparam HBA_PORT__PxCMD__CCS__MASK =
'h1f00;
823 localparam HBA_PORT__PxCMD__CCS__DFLT =
'h0;
824 // RW: FIS Receive Enable (enable after FIS memory is set) 825 localparam HBA_PORT__PxCMD__FRE__ADDR =
'h46;
826 localparam HBA_PORT__PxCMD__FRE__MASK =
'h10;
827 localparam HBA_PORT__PxCMD__FRE__DFLT =
'h0;
828 // RW1: Command List Override 829 localparam HBA_PORT__PxCMD__CLO__ADDR =
'h46;
830 localparam HBA_PORT__PxCMD__CLO__MASK =
'h8;
831 localparam HBA_PORT__PxCMD__CLO__DFLT =
'h0;
832 // RO: Power On Device (RW with Cold Presence Detection) 833 localparam HBA_PORT__PxCMD__POD__ADDR =
'h46;
834 localparam HBA_PORT__PxCMD__POD__MASK =
'h4;
835 localparam HBA_PORT__PxCMD__POD__DFLT =
'h4;
836 // RO: Spin-Up Device (RW with Staggered Spin-Up Support) 837 localparam HBA_PORT__PxCMD__SUD__ADDR =
'h46;
838 localparam HBA_PORT__PxCMD__SUD__MASK =
'h2;
839 localparam HBA_PORT__PxCMD__SUD__DFLT =
'h2;
840 // RW: Start (HBA may process commands). See section 10.3.1 841 localparam HBA_PORT__PxCMD__ST__ADDR =
'h46;
842 localparam HBA_PORT__PxCMD__ST__MASK =
'h1;
843 localparam HBA_PORT__PxCMD__ST__DFLT =
'h0;
844 // RO: Latest Copy of Task File Error Register 845 localparam HBA_PORT__PxTFD__ERR__ADDR =
'h48;
846 localparam HBA_PORT__PxTFD__ERR__MASK =
'hff00;
847 localparam HBA_PORT__PxTFD__ERR__DFLT =
'h0;
848 // RO: Latest Copy of Task File Status Register: BSY 849 localparam HBA_PORT__PxTFD__STS__BSY__ADDR =
'h48;
850 localparam HBA_PORT__PxTFD__STS__BSY__MASK =
'h80;
851 localparam HBA_PORT__PxTFD__STS__BSY__DFLT =
'h0;
852 // RO: Latest Copy of Task File Status Register: command-specific bits 4..6 853 localparam HBA_PORT__PxTFD__STS__64__ADDR =
'h48;
854 localparam HBA_PORT__PxTFD__STS__64__MASK =
'h70;
855 localparam HBA_PORT__PxTFD__STS__64__DFLT =
'h0;
856 // RO: Latest Copy of Task File Status Register: DRQ 857 localparam HBA_PORT__PxTFD__STS__DRQ__ADDR =
'h48;
858 localparam HBA_PORT__PxTFD__STS__DRQ__MASK =
'h8;
859 localparam HBA_PORT__PxTFD__STS__DRQ__DFLT =
'h0;
860 // RO: Latest Copy of Task File Status Register: command-specific bits 1..2 861 localparam HBA_PORT__PxTFD__STS__12__ADDR =
'h48;
862 localparam HBA_PORT__PxTFD__STS__12__MASK =
'h6;
863 localparam HBA_PORT__PxTFD__STS__12__DFLT =
'h0;
864 // RO: Latest Copy of Task File Status Register: ERR 865 localparam HBA_PORT__PxTFD__STS__ERR__ADDR =
'h48;
866 localparam HBA_PORT__PxTFD__STS__ERR__MASK =
'h1;
867 localparam HBA_PORT__PxTFD__STS__ERR__DFLT =
'h0;
868 // RO: Data in the first D2H Register FIS 869 localparam HBA_PORT__PxSIG__SIG__ADDR =
'h49;
870 localparam HBA_PORT__PxSIG__SIG__MASK =
'hffffffff;
871 localparam HBA_PORT__PxSIG__SIG__DFLT =
'hffffffff;
872 // RO: Interface Power Management 873 localparam HBA_PORT__PxSSTS__IPM__ADDR =
'h4a;
874 localparam HBA_PORT__PxSSTS__IPM__MASK =
'hf00;
875 localparam HBA_PORT__PxSSTS__IPM__DFLT =
'h0;
876 // RO: Interface Speed 877 localparam HBA_PORT__PxSSTS__SPD__ADDR =
'h4a;
878 localparam HBA_PORT__PxSSTS__SPD__MASK =
'hf0;
879 localparam HBA_PORT__PxSSTS__SPD__DFLT =
'h0;
880 // RO: Device Detection (should be detected if COMINIT is received) 881 localparam HBA_PORT__PxSSTS__DET__ADDR =
'h4a;
882 localparam HBA_PORT__PxSSTS__DET__MASK =
'hf;
883 localparam HBA_PORT__PxSSTS__DET__DFLT =
'h0;
884 // RO: Port Multiplier Port - not used by AHCI 885 localparam HBA_PORT__PxSCTL__PMP__ADDR =
'h4b;
886 localparam HBA_PORT__PxSCTL__PMP__MASK =
'hf0000;
887 localparam HBA_PORT__PxSCTL__PMP__DFLT =
'h0;
888 // RO: Select Power Management - not used by AHCI 889 localparam HBA_PORT__PxSCTL__SPM__ADDR =
'h4b;
890 localparam HBA_PORT__PxSCTL__SPM__MASK =
'hf000;
891 localparam HBA_PORT__PxSCTL__SPM__DFLT =
'h0;
892 // RW: Interface Power Management Transitions Allowed 893 localparam HBA_PORT__PxSCTL__IPM__ADDR =
'h4b;
894 localparam HBA_PORT__PxSCTL__IPM__MASK =
'hf00;
895 localparam HBA_PORT__PxSCTL__IPM__DFLT =
'h0;
896 // RW: Interface Highest Speed 897 localparam HBA_PORT__PxSCTL__SPD__ADDR =
'h4b;
898 localparam HBA_PORT__PxSCTL__SPD__MASK =
'hf0;
899 localparam HBA_PORT__PxSCTL__SPD__DFLT =
'h0;
900 // RW: Device Detection Initialization 901 localparam HBA_PORT__PxSCTL__DET__ADDR =
'h4b;
902 localparam HBA_PORT__PxSCTL__DET__MASK =
'hf;
903 localparam HBA_PORT__PxSCTL__DET__DFLT =
'h0;
904 // RWC: Exchanged (set on COMINIT), reflected in PxIS.PCS 905 localparam HBA_PORT__PxSERR__DIAG__X__ADDR =
'h4c;
906 localparam HBA_PORT__PxSERR__DIAG__X__MASK =
'h4000000;
907 localparam HBA_PORT__PxSERR__DIAG__X__DFLT =
'h0;
909 localparam HBA_PORT__PxSERR__DIAG__F__ADDR =
'h4c;
910 localparam HBA_PORT__PxSERR__DIAG__F__MASK =
'h2000000;
911 localparam HBA_PORT__PxSERR__DIAG__F__DFLT =
'h0;
912 // RWC: Transport state transition error 913 localparam HBA_PORT__PxSERR__DIAG__T__ADDR =
'h4c;
914 localparam HBA_PORT__PxSERR__DIAG__T__MASK =
'h1000000;
915 localparam HBA_PORT__PxSERR__DIAG__T__DFLT =
'h0;
916 // RWC: Link sequence error 917 localparam HBA_PORT__PxSERR__DIAG__S__ADDR =
'h4c;
918 localparam HBA_PORT__PxSERR__DIAG__S__MASK =
'h800000;
919 localparam HBA_PORT__PxSERR__DIAG__S__DFLT =
'h0;
920 // RWC: Handshake Error (i.e. Device got CRC error) 921 localparam HBA_PORT__PxSERR__DIAG__H__ADDR =
'h4c;
922 localparam HBA_PORT__PxSERR__DIAG__H__MASK =
'h400000;
923 localparam HBA_PORT__PxSERR__DIAG__H__DFLT =
'h0;
924 // RWC: CRC error in Link layer 925 localparam HBA_PORT__PxSERR__DIAG__C__ADDR =
'h4c;
926 localparam HBA_PORT__PxSERR__DIAG__C__MASK =
'h200000;
927 localparam HBA_PORT__PxSERR__DIAG__C__DFLT =
'h0;
928 // RWC: Disparity Error - not used by AHCI 929 localparam HBA_PORT__PxSERR__DIAG__D__ADDR =
'h4c;
930 localparam HBA_PORT__PxSERR__DIAG__D__MASK =
'h100000;
931 localparam HBA_PORT__PxSERR__DIAG__D__DFLT =
'h0;
932 // RWC: 10B to 8B decode error 933 localparam HBA_PORT__PxSERR__DIAG__B__ADDR =
'h4c;
934 localparam HBA_PORT__PxSERR__DIAG__B__MASK =
'h80000;
935 localparam HBA_PORT__PxSERR__DIAG__B__DFLT =
'h0;
936 // RWC: COMMWAKE signal was detected 937 localparam HBA_PORT__PxSERR__DIAG__W__ADDR =
'h4c;
938 localparam HBA_PORT__PxSERR__DIAG__W__MASK =
'h40000;
939 localparam HBA_PORT__PxSERR__DIAG__W__DFLT =
'h0;
940 // RWC: PHY Internal Error 941 localparam HBA_PORT__PxSERR__DIAG__I__ADDR =
'h4c;
942 localparam HBA_PORT__PxSERR__DIAG__I__MASK =
'h20000;
943 localparam HBA_PORT__PxSERR__DIAG__I__DFLT =
'h0;
944 // RWC: PhyRdy changed. Reflected in PxIS.PRCS bit. 945 localparam HBA_PORT__PxSERR__DIAG__N__ADDR =
'h4c;
946 localparam HBA_PORT__PxSERR__DIAG__N__MASK =
'h10000;
947 localparam HBA_PORT__PxSERR__DIAG__N__DFLT =
'h0;
948 // RWC: Internal Error 949 localparam HBA_PORT__PxSERR__ERR__E__ADDR =
'h4c;
950 localparam HBA_PORT__PxSERR__ERR__E__MASK =
'h800;
951 localparam HBA_PORT__PxSERR__ERR__E__DFLT =
'h0;
952 // RWC: Protocol Error - a violation of SATA protocol detected 953 localparam HBA_PORT__PxSERR__ERR__P__ADDR =
'h4c;
954 localparam HBA_PORT__PxSERR__ERR__P__MASK =
'h400;
955 localparam HBA_PORT__PxSERR__ERR__P__DFLT =
'h0;
956 // RWC: Persistent Communication or Data Integrity Error 957 localparam HBA_PORT__PxSERR__ERR__C__ADDR =
'h4c;
958 localparam HBA_PORT__PxSERR__ERR__C__MASK =
'h200;
959 localparam HBA_PORT__PxSERR__ERR__C__DFLT =
'h0;
960 // RWC: Transient Data Integrity Error (error not recovered by the interface) 961 localparam HBA_PORT__PxSERR__ERR__T__ADDR =
'h4c;
962 localparam HBA_PORT__PxSERR__ERR__T__MASK =
'h100;
963 localparam HBA_PORT__PxSERR__ERR__T__DFLT =
'h0;
964 // RWC: Communication between the device and host was lost but re-established 965 localparam HBA_PORT__PxSERR__ERR__M__ADDR =
'h4c;
966 localparam HBA_PORT__PxSERR__ERR__M__MASK =
'h2;
967 localparam HBA_PORT__PxSERR__ERR__M__DFLT =
'h0;
968 // RWC: Recovered Data integrity Error 969 localparam HBA_PORT__PxSERR__ERR__I__ADDR =
'h4c;
970 localparam HBA_PORT__PxSERR__ERR__I__MASK =
'h1;
971 localparam HBA_PORT__PxSERR__ERR__I__DFLT =
'h0;
972 // RW1: Device Status: bit per Port, for TAG in native queued command 973 localparam HBA_PORT__PxSACT__DS__ADDR =
'h4d;
974 localparam HBA_PORT__PxSACT__DS__MASK =
'hffffffff;
975 localparam HBA_PORT__PxSACT__DS__DFLT =
'h0;
976 // RW1: Command Issued: bit per Port, only set when PxCMD.ST==1, also cleared by PxCMD.ST: 1->0 by soft 977 localparam HBA_PORT__PxCI__CI__ADDR =
'h4e;
978 localparam HBA_PORT__PxCI__CI__MASK =
'hffffffff;
979 localparam HBA_PORT__PxCI__CI__DFLT =
'h0;
980 // RWC: PM Notify (bit per PM port) 981 localparam HBA_PORT__PxSNTF__PMN__ADDR =
'h4f;
982 localparam HBA_PORT__PxSNTF__PMN__MASK =
'hffff;
983 localparam HBA_PORT__PxSNTF__PMN__DFLT =
'h0;
984 // RO: Device with Error 985 localparam HBA_PORT__PxFBS__DWE__ADDR =
'h50;
986 localparam HBA_PORT__PxFBS__DWE__MASK =
'hf0000;
987 localparam HBA_PORT__PxFBS__DWE__DFLT =
'h0;
988 // RO: Active Device Optimization 989 localparam HBA_PORT__PxFBS__ADO__ADDR =
'h50;
990 localparam HBA_PORT__PxFBS__ADO__MASK =
'hf000;
991 localparam HBA_PORT__PxFBS__ADO__DFLT =
'h0;
992 // RW: Device To Issue 993 localparam HBA_PORT__PxFBS__DEV__ADDR =
'h50;
994 localparam HBA_PORT__PxFBS__DEV__MASK =
'hf00;
995 localparam HBA_PORT__PxFBS__DEV__DFLT =
'h0;
996 // RO: Single Device Error 997 localparam HBA_PORT__PxFBS__SDE__ADDR =
'h50;
998 localparam HBA_PORT__PxFBS__SDE__MASK =
'h4;
999 localparam HBA_PORT__PxFBS__SDE__DFLT =
'h0;
1000 // RW1: Device Error Clear 1001 localparam HBA_PORT__PxFBS__DEC__ADDR =
'h50;
1002 localparam HBA_PORT__PxFBS__DEC__MASK =
'h2;
1003 localparam HBA_PORT__PxFBS__DEC__DFLT =
'h0;
1005 localparam HBA_PORT__PxFBS__EN__ADDR =
'h50;
1006 localparam HBA_PORT__PxFBS__EN__MASK =
'h1;
1007 localparam HBA_PORT__PxFBS__EN__DFLT =
'h0;
1008 // RO: DITO Multiplier 1009 localparam HBA_PORT__PxDEVSLP__DM__ADDR =
'h51;
1010 localparam HBA_PORT__PxDEVSLP__DM__MASK =
'h1e000000;
1011 localparam HBA_PORT__PxDEVSLP__DM__DFLT =
'h0;
1012 // RW: Device Sleep Idle Timeout (section 8.5.1.1.1) 1013 localparam HBA_PORT__PxDEVSLP__DITO__ADDR =
'h51;
1014 localparam HBA_PORT__PxDEVSLP__DITO__MASK =
'h1ff8000;
1015 localparam HBA_PORT__PxDEVSLP__DITO__DFLT =
'h0;
1016 // RW: Minimum Device Sleep Assertion Time 1017 localparam HBA_PORT__PxDEVSLP__MDAT__ADDR =
'h51;
1018 localparam HBA_PORT__PxDEVSLP__MDAT__MASK =
'h7c00;
1019 localparam HBA_PORT__PxDEVSLP__MDAT__DFLT =
'h0;
1020 // RW: Device Sleep Exit Timeout 1021 localparam HBA_PORT__PxDEVSLP__DETO__ADDR =
'h51;
1022 localparam HBA_PORT__PxDEVSLP__DETO__MASK =
'h3fc;
1023 localparam HBA_PORT__PxDEVSLP__DETO__DFLT =
'h0;
1024 // RO: Device Sleep Present 1025 localparam HBA_PORT__PxDEVSLP__DSP__ADDR =
'h51;
1026 localparam HBA_PORT__PxDEVSLP__DSP__MASK =
'h2;
1027 localparam HBA_PORT__PxDEVSLP__DSP__DFLT =
'h0;
1028 // RO: Aggressive Device Sleep Enable 1029 localparam HBA_PORT__PxDEVSLP__ADSE__ADDR =
'h51;
1030 localparam HBA_PORT__PxDEVSLP__ADSE__MASK =
'h1;
1031 localparam HBA_PORT__PxDEVSLP__ADSE__DFLT =
'h0;
1032 // RW: SAXIHP write channel cache mode 1033 localparam HBA_PORT__AFI_CACHE__WR_CM__ADDR =
'h5c;
1034 localparam HBA_PORT__AFI_CACHE__WR_CM__MASK =
'hf0;
1035 localparam HBA_PORT__AFI_CACHE__WR_CM__DFLT =
'h30;
1036 // RW: SAXIHP read channel cache mode 1037 localparam HBA_PORT__AFI_CACHE__RD_CM__ADDR =
'h5c;
1038 localparam HBA_PORT__AFI_CACHE__RD_CM__MASK =
'hf;
1039 localparam HBA_PORT__AFI_CACHE__RD_CM__DFLT =
'h3;
1040 // RW: Address/not data for programming AHCI state machine 1041 localparam HBA_PORT__PGM_AHCI_SM__AnD__ADDR =
'h5d;
1042 localparam HBA_PORT__PGM_AHCI_SM__AnD__MASK =
'h1000000;
1043 localparam HBA_PORT__PGM_AHCI_SM__AnD__DFLT =
'h0;
1044 // RW: Program address/data for programming AHCI state machine 1045 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR =
'h5d;
1046 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK =
'h3ffff;
1047 localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT =
'h0;
1048 // RW: 3-bit tag to add to the recorded timestamp 1049 localparam HBA_PORT__PunchTime__TAG__ADDR =
'h5e;
1050 localparam HBA_PORT__PunchTime__TAG__MASK =
'h7;
1051 localparam HBA_PORT__PunchTime__TAG__DFLT =
'h0;
1054 localparam FIS_H2DR =
'h27;
1055 localparam FIS_D2HR =
'h34;
1056 localparam FIS_DMAA =
'h39;
1057 localparam FIS_DMAS =
'h41;
1058 localparam FIS_DATA =
'h46;
1059 localparam FIS_BIST =
'h58;
1060 localparam FIS_PIOS =
'h5f;
1061 localparam FIS_SDB =
'ha1;
1063 // Reset addresses - later use generated 1077 wire cond_met_w;
// calculated from signals and program conditions decoder 1087 reg dis_actions;
// disable actions during async jump 1090 reg fsm_preload;
// read first sequence data (2 cycles for regen) 1091 // wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions 1092 // reg [7:0] conditions; 1093 // wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]); 1099 asynq_rq;
// cominit_got || pcmd_st_cleared 1100 reg fsm_act_done;
// made later by 1 cycle so the new conditions are latched // TODO:check is enough ? Adding 1 extra 1107 reg [
1:
0]
async_pend_r;
// waiting to process cominit_got 1108 reg async_from_st;
// change to multi-bit if there will be more sources for async transitions 1109 // wire asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared; 1111 // OK to wait for some time fsm_act_busy is supposed to never hang up 1113 // reg x_rdy_collision_pend; 1114 reg syncesc_send_pend;
// waiting for 'syncesc_send' confiramtion 'syncesc_send_done' 1124 wire conditions_ce =
// copy all conditions to the register so they will not change while iterating through them 1126 // reg unsolicited_cominit_en; // allow unsolicited COMINITs 1127 // wire en_cominit; // en_cominit 1130 reg pisn32;
// pIssueSlot != 32 1131 wire clear_pisn32;
// additional clear when in P:NotRunning state 1148 // assign ssts_det_dnp = 0; // device detected, but phy communication not established 1151 assign sirq_OF =
0;
// RWC: Overflow Status (buffer overrun - should not happen, add?) 1156 // Writing to the FSM program memory 1157 always @ (
posedge aclk)
begin 1163 always @ (
posedge mclk)
begin 1169 always @ (
posedge mclk)
begin 1170 /// if (hba_rst) unsolicited_cominit_en <= !was_port_rst; 1171 // else if (en_cominit || comreset_send) unsolicited_cominit_en <= en_cominit; 1175 // else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT; 1181 /// fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle 1191 // if (hba_rst) conditions <= 0; 1192 // if (fsm_transitions[0]) conditions <= precond_w; 1207 // else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) || 1208 // (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1; 1223 /// else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)}; 1227 // if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0; 1228 // else if (x_rdy_collision) x_rdy_collision_pend <= 1; 1243 .
LOG2WIDTH_RD(
4), .
INIT_00 (
256'h00100000000E0000000C02020035000000220000000C0000000A0000000C0000)
1244 , .
INIT_01 (
256'h1C3C9449543244190060001B0108001B00500402040401040022000600120000)
1245 , .
INIT_02 (
256'h001BC8300014000C0210002B2507250E0180001B0003004200180000001B4455)
1246 , .
INIT_03 (
256'h4C6B2C45141B0012003C01080028000A040800220410001B01020110001B0005)
1247 , .
INIT_04 (
256'h0210001B14490102005004020404003CB080707D00A0003C8C6E845584C7443A)
1248 , .
INIT_05 (
256'h000000512507250E0240004F2507250E0240005F0000003C0000001B0210003C)
1249 , .
INIT_06 (
256'h02200204006E0402009000EEA89968FC18F518D498B058E0388564570C27045B)
1250 , .
INIT_07 (
256'h003CB0800000005300840022003CB080707D307A30FC02080074D10E5104903C)
1251 , .
INIT_08 (
256'h2891290A0000000000000014021000892507250E018000A2D1070120003C0000)
1252 , .
INIT_09 (
256'h0CB6290A0210009D2507250E04400053000C009700050097C895002200440097)
1253 , .
INIT_0A (
256'h00530081005348AE00220044003C48AE28AA290A0000000000000024003C4882)
1254 , .
INIT_0B (
256'h0044008800BED1075104042000BA883C08A2003000B6021000B42507250E0240)
1255 , .
INIT_0C (
256'h0048021000CEC50E2507250700C000C90030003C88A200300009003C88A250C3)
1256 , .
INIT_0D (
256'h003C34DB000000DD001100DDC8DB021000D82507250E0140003C88A250C30044)
1257 , .
INIT_0E (
256'h250E0480005301010053C8EC290A0000000000000014021000E42507250E0280)
1258 , .
INIT_0F (
256'h01002507250E024001020082021000F92507250E0240003C0401021000F22507)
1259 , .
INIT_10 (
256'h00410410010C0000010C0201010C00210410010C002100840102000001020210)
1260 , .
INIT_11 (
256'h000000000000000000000000000000000000000000000000000000000000003C)
1261 , .
INITP_00 (
256'h08802605C240900789C9C8888A000C25062040820809C8020188800222222222)
1262 , .
INITP_01 (
256'h27209C82720A00270882271A009C86068072E22721816802A89C882068009C32)
1263 , .
INITP_02 (
256'h0000000000000000000000000000000000000000000000000000000082220822)
1274 .
web (
4'hf),
// input[7:0] 1321 // SATA TRANSPORT/LINK/PHY 1327 // .EN_COMINIT (en_cominit), // output reg 1329 // FIS TRANSMIT/WAIT DONE 1334 //FIS RECEIVE/WAIT DONE 1344 // Condition inputs may be registered if needed 1352 // .PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd 1356 .
NST_D2HR (!
pcmd_st && (
fis_type ==
FIS_D2HR)),
// input !ST && (FIS == FIS_D2HR) TODO: does it mean either BSY or DRQ are 1? 1364 .
NPCMD_FRE (!
pxcmd_fre),
// input !pcmd_fre (docs: goto P:NotRunning, but we need to clear FIFO) 1375 .
D2HR (
fis_type ==
FIS_D2HR),
// input FIS == FIS_D2HR 1380 .
BIST_ACT ((
fis_type ==
FIS_BIST)),
// input FIS == FIS_BIST# && !(|bist_bits) 1386 .
NPD (!
pio_d),
// input pio_d = 0 , "ch_a == 1" is not needed 1395 .
TX_ERR (
dx_err[
1]),
// input dx_err[1] (reset by new command) 1399 // SATA TRANSPORT/LINK/PHY 1407 input update_busy, // valid same cycle as update_all 1411 Implement sync esc request/ackn in TL (available in LL)
13533fsm_transitionsreg[1:0]
13524pgm_jump_addrreg[9:0]
14567PXCI0_NOT_CMDTOISSUE
14574SCTL_DET_CHANGED_TO_1
13542async_pend_rreg[1:0]
reg 14534CLEAR_BSY_SET_DRQ
13551fsm_transitions_wwire
13550was_last_action_rreg
[9 << LOG2WIDTH_WR-3-1:0] 11679data_in
14573SCTL_DET_CHANGED_TO_4
reg 14542CLEAR_CMD_TO_ISSUE
13517LABEL_COMINIT11'h006
fsm_pgm_mem_i ram18p_var_w_var_r
condition_mux_i condition_mux
13547phy_ready_prevreg[1:0]
[9 << LOG2WIDTH_RD-3-1:0] 11674data_out
13546syncesc_send_pendreg
reg 14544DMA_PRD_IRQ_CLEAR
13516LABEL_PORT_RST11'h004
reg 14525SSTS_DET_OFFLINE
action_decoder_i action_decoder
13515LABEL_HBA_RST11'h002
reg [ 9:0] 13513last_jump_addr
[13-LOG2WIDTH_RD:0] 11671raddr
13549phy_ready_chng_wwire
[13-LOG2WIDTH_WR:0] 11676waddr
13518LABEL_ST_CLEARED11'h008