x393  1.0
FPGAcodeforElphelNC393camera
ahci_fis_transmit Module Reference
Inheritance diagram for ahci_fis_transmit:

Static Public Member Functions

Always Constructs

ALWAYS_584  ( mclk )

Public Attributes

Inputs

hba_rst  
mclk  
pcmd_st_cleared  
fetch_cmd  
cfis_xmit  
dx_xmit  
atapi_xmit  
clearCmdToIssue  
xmit_ok  
xmit_err  
syncesc_recv  
xrdy_collision  
reg_rdata   [ 31 : 0 ]
xfer_cntr   [ 31 : 2 ]
xfer_cntr_zero  
dma_ct_busy  
ct_data   [ 31 : 0 ]
dma_out   [ 31 : 0 ]
dma_dav  
last_h2d_data  
todev_ready  

Outputs

done   reg
busy   reg
pCmdToIssue  
dx_err   [ 2 : 0 ]
ch_prdtl   [ 15 : 0 ]
ch_c  
ch_b  
ch_r  
ch_p  
ch_w  
ch_a  
ch_cfl   [ 4 : 0 ]
dwords_sent   reg [ 11 : 0 ]
reg_addr   reg [ADDRESS_BITS - 1 : 0 ]
reg_re   [ 1 : 0 ]
dma_ctba_ld  
dma_start  
dma_dev_wr  
dma_prd_start   reg
dma_cmd_abort   reg
ct_addr   reg [ 4 : 0 ]
ct_re   [ 1 : 0 ]
dma_re  
todev_data   reg [ 31 : 0 ]
todev_type   reg [ 1 : 0 ]
todev_valid  
debug_01   [ 9 : 0 ]

Parameters

PREFETCH_ALWAYS   0
READ_REG_LATENCY   2
READ_CT_LATENCY   2
ADDRESS_BITS   10
CLB_OFFS32  'h200
DATA_FIS   32 'h46

Signals

reg  todev_full_r
reg  dma_en_r
wire  fis_data_valid
wire[ 1 : 0 ]  fis_data_type
wire[ 31 : 0 ]  fis_data_out
wire  write_or_w
wire  dma_re_w
reg[ 15 : 0 ]  ch_prdtl_r
reg  ch_c_r
reg  ch_b_r
reg  ch_r_r
reg  ch_p_r
reg  ch_w_r
reg  ch_a_r
reg[ 4 : 0 ]  ch_cmd_len_r
reg[ 4 : 0 ]  cfis_acmd_left_r
reg[ 4 : 0 ]  cfis_acmd_left_out_r
reg[READ_REG_LATENCY : 0 ]  reg_re_r
wire  reg_re_w
wire  pre_reg_stb
reg[ 3 : 0 ]  fetch_chead_r
reg[ 3 : 0 ]  fetch_chead_stb_r
wire  chead_done_w
reg  chead_bsy
reg  chead_bsy_re
reg  pCmdToIssue_r
reg  acfis_xmit_pend_r
reg  acfis_xmit_start_r
reg  acfis_xmit_busy_r
wire  acfis_xmit_start_w
wire  acfis_xmit_end
wire  ct_re_w
reg[READ_CT_LATENCY : 0 ]  ct_re_r
wire  ct_stb
reg  fis_dw_first
wire  fis_dw_last
reg[ 11 : 0 ]  dx_dwords_left
reg  dx_fis_pend_r
wire  dx_dma_last_w
reg  dx_busy_r
reg[ 2 : 0 ]  dx_err_r
reg  xmit_ok_r
wire  any_cmd_start
wire  done_w
reg  fetch_cmd_busy_r
reg[ 3 : 0 ]  dbg_was_ct_re_r
reg[ 4 : 0 ]  dbg_was_cfis_acmd_left_r

Detailed Description

Definition at line 28 of file ahci_fis_transmit.v.

Member Function Documentation

ALWAYS_584 (   mclk  
)
Always Construct

Definition at line 238 of file ahci_fis_transmit.v.

Member Data Documentation

PREFETCH_ALWAYS 0
Parameter

Definition at line 29 of file ahci_fis_transmit.v.

READ_REG_LATENCY 2
Parameter

Definition at line 30 of file ahci_fis_transmit.v.

READ_CT_LATENCY 2
Parameter

Definition at line 32 of file ahci_fis_transmit.v.

ADDRESS_BITS 10
Parameter

Definition at line 33 of file ahci_fis_transmit.v.

hba_rst
Input

Definition at line 36 of file ahci_fis_transmit.v.

mclk
Input

Definition at line 37 of file ahci_fis_transmit.v.

Definition at line 38 of file ahci_fis_transmit.v.

fetch_cmd
Input

Definition at line 40 of file ahci_fis_transmit.v.

cfis_xmit
Input

Definition at line 42 of file ahci_fis_transmit.v.

dx_xmit
Input

Definition at line 43 of file ahci_fis_transmit.v.

atapi_xmit
Input

Definition at line 45 of file ahci_fis_transmit.v.

done reg
Output

Definition at line 48 of file ahci_fis_transmit.v.

busy reg
Output

Definition at line 49 of file ahci_fis_transmit.v.

Definition at line 51 of file ahci_fis_transmit.v.

pCmdToIssue
Output

Definition at line 52 of file ahci_fis_transmit.v.

xmit_ok
Input

Definition at line 57 of file ahci_fis_transmit.v.

xmit_err
Input

Definition at line 58 of file ahci_fis_transmit.v.

syncesc_recv
Input

Definition at line 59 of file ahci_fis_transmit.v.

Definition at line 60 of file ahci_fis_transmit.v.

dx_err [ 2 : 0 ]
Output

Definition at line 61 of file ahci_fis_transmit.v.

ch_prdtl [ 15 : 0 ]
Output

Definition at line 63 of file ahci_fis_transmit.v.

ch_c
Output

Definition at line 64 of file ahci_fis_transmit.v.

ch_b
Output

Definition at line 65 of file ahci_fis_transmit.v.

ch_r
Output

Definition at line 66 of file ahci_fis_transmit.v.

ch_p
Output

Definition at line 67 of file ahci_fis_transmit.v.

ch_w
Output

Definition at line 68 of file ahci_fis_transmit.v.

ch_a
Output

Definition at line 69 of file ahci_fis_transmit.v.

ch_cfl [ 4 : 0 ]
Output

Definition at line 70 of file ahci_fis_transmit.v.

dwords_sent reg [ 11 : 0 ]
Output

Definition at line 72 of file ahci_fis_transmit.v.

reg_addr reg [ADDRESS_BITS - 1 : 0 ]
Output

Definition at line 75 of file ahci_fis_transmit.v.

reg_re [ 1 : 0 ]
Output

Definition at line 76 of file ahci_fis_transmit.v.

reg_rdata [ 31 : 0 ]
Input

Definition at line 77 of file ahci_fis_transmit.v.

xfer_cntr [ 31 : 2 ]
Input

Definition at line 80 of file ahci_fis_transmit.v.

Definition at line 81 of file ahci_fis_transmit.v.

dma_ctba_ld
Output

Definition at line 84 of file ahci_fis_transmit.v.

dma_start
Output

Definition at line 85 of file ahci_fis_transmit.v.

dma_dev_wr
Output

Definition at line 86 of file ahci_fis_transmit.v.

dma_ct_busy
Input

Definition at line 87 of file ahci_fis_transmit.v.

dma_prd_start reg
Output

Definition at line 89 of file ahci_fis_transmit.v.

dma_cmd_abort reg
Output

Definition at line 90 of file ahci_fis_transmit.v.

ct_addr reg [ 4 : 0 ]
Output

Definition at line 93 of file ahci_fis_transmit.v.

ct_re [ 1 : 0 ]
Output

Definition at line 94 of file ahci_fis_transmit.v.

ct_data [ 31 : 0 ]
Input

Definition at line 95 of file ahci_fis_transmit.v.

dma_out [ 31 : 0 ]
Input

Definition at line 98 of file ahci_fis_transmit.v.

dma_dav
Input

Definition at line 99 of file ahci_fis_transmit.v.

dma_re
Output

Definition at line 100 of file ahci_fis_transmit.v.

Definition at line 101 of file ahci_fis_transmit.v.

todev_data reg [ 31 : 0 ]
Output

Definition at line 104 of file ahci_fis_transmit.v.

todev_type reg [ 1 : 0 ]
Output

Definition at line 105 of file ahci_fis_transmit.v.

todev_valid
Output

Definition at line 106 of file ahci_fis_transmit.v.

todev_ready
Input

Definition at line 107 of file ahci_fis_transmit.v.

debug_01 [ 9 : 0 ]
Output

Definition at line 109 of file ahci_fis_transmit.v.

CLB_OFFS32 'h200
Parameter

Definition at line 113 of file ahci_fis_transmit.v.

DATA_FIS 32 'h46
Parameter

Definition at line 114 of file ahci_fis_transmit.v.

todev_full_r
Signal

Definition at line 115 of file ahci_fis_transmit.v.

dma_en_r
Signal

Definition at line 116 of file ahci_fis_transmit.v.

Definition at line 117 of file ahci_fis_transmit.v.

fis_data_type
Signal

Definition at line 118 of file ahci_fis_transmit.v.

fis_data_out
Signal

Definition at line 119 of file ahci_fis_transmit.v.

write_or_w
Signal

Definition at line 121 of file ahci_fis_transmit.v.

dma_re_w
Signal

Definition at line 124 of file ahci_fis_transmit.v.

ch_prdtl_r
Signal

Definition at line 127 of file ahci_fis_transmit.v.

ch_c_r
Signal

Definition at line 128 of file ahci_fis_transmit.v.

ch_b_r
Signal

Definition at line 129 of file ahci_fis_transmit.v.

ch_r_r
Signal

Definition at line 130 of file ahci_fis_transmit.v.

ch_p_r
Signal

Definition at line 131 of file ahci_fis_transmit.v.

ch_w_r
Signal

Definition at line 132 of file ahci_fis_transmit.v.

ch_a_r
Signal

Definition at line 133 of file ahci_fis_transmit.v.

ch_cmd_len_r
Signal

Definition at line 134 of file ahci_fis_transmit.v.

Definition at line 135 of file ahci_fis_transmit.v.

Definition at line 138 of file ahci_fis_transmit.v.

reg_re_r
Signal

Definition at line 141 of file ahci_fis_transmit.v.

reg_re_w
Signal

Definition at line 142 of file ahci_fis_transmit.v.

pre_reg_stb
Signal

Definition at line 145 of file ahci_fis_transmit.v.

fetch_chead_r
Signal

Definition at line 146 of file ahci_fis_transmit.v.

Definition at line 147 of file ahci_fis_transmit.v.

chead_done_w
Signal

Definition at line 148 of file ahci_fis_transmit.v.

chead_bsy
Signal

Definition at line 149 of file ahci_fis_transmit.v.

chead_bsy_re
Signal

Definition at line 150 of file ahci_fis_transmit.v.

pCmdToIssue_r
Signal

Definition at line 151 of file ahci_fis_transmit.v.

Definition at line 153 of file ahci_fis_transmit.v.

Definition at line 154 of file ahci_fis_transmit.v.

Definition at line 155 of file ahci_fis_transmit.v.

Definition at line 158 of file ahci_fis_transmit.v.

Definition at line 159 of file ahci_fis_transmit.v.

ct_re_w
Signal

Definition at line 161 of file ahci_fis_transmit.v.

ct_re_r
Signal

Definition at line 162 of file ahci_fis_transmit.v.

ct_stb
Signal

Definition at line 164 of file ahci_fis_transmit.v.

fis_dw_first
Signal

Definition at line 166 of file ahci_fis_transmit.v.

fis_dw_last
Signal

Definition at line 167 of file ahci_fis_transmit.v.

Definition at line 169 of file ahci_fis_transmit.v.

dx_fis_pend_r
Signal

Definition at line 170 of file ahci_fis_transmit.v.

dx_dma_last_w
Signal

Definition at line 171 of file ahci_fis_transmit.v.

dx_busy_r
Signal

Definition at line 172 of file ahci_fis_transmit.v.

dx_err_r
Signal

Definition at line 173 of file ahci_fis_transmit.v.

xmit_ok_r
Signal

Definition at line 174 of file ahci_fis_transmit.v.

any_cmd_start
Signal

Definition at line 175 of file ahci_fis_transmit.v.

done_w
Signal

Definition at line 178 of file ahci_fis_transmit.v.

Definition at line 180 of file ahci_fis_transmit.v.

Definition at line 233 of file ahci_fis_transmit.v.

Definition at line 234 of file ahci_fis_transmit.v.


The documentation for this Module was generated from the following files: