axi_ahci_regs Module Reference

Inheritance diagram for axi_ahci_regs:

Collaboration diagram for axi_ahci_regs:

Static Public Member Functions

Always Constructs
ALWAYS_594	( aclk )
ALWAYS_595	( aclk )
ALWAYS_596	( aclk )
ALWAYS_597	( aclk )
ALWAYS_598	( hba_clk )
ALWAYS_599	( aclk )
ALWAYS_600	( aclk )

Public Attributes

Inputs
aclk
arst
awaddr	[ 31 : 0 ]
awvalid
awid	[ 11 : 0 ]
awlen	[ 3 : 0 ]
awsize	[ 1 : 0 ]
awburst	[ 1 : 0 ]
wdata	[ 31 : 0 ]
wvalid
wid	[ 11 : 0 ]
wlast
wstb	[ 3 : 0 ]
bready
araddr	[ 31 : 0 ]
arvalid
arid	[ 11 : 0 ]
arlen	[ 3 : 0 ]
arsize	[ 1 : 0 ]
arburst	[ 1 : 0 ]
rready
hba_clk
hba_rst
hba_addr	[ADDRESS_BITS - 1 : 0 ]
hba_we
hba_re	[ 1 : 0 ]
hba_din	[ 31 : 0 ]
debug_in0	[ 31 : 0 ]
debug_in1	[ 31 : 0 ]
debug_in2	[ 31 : 0 ]
debug_in3	[ 31 : 0 ]
drp_rdy
drp_do	[ 15 : 0 ]
datascope_clk
datascope_waddr	[ADDRESS_BITS - 1 : 0 ]
datascope_we
datascope_di	[ 31 : 0 ]
datascope1_clk
datascope1_waddr	[ADDRESS_BITS - 1 : 0 ]
datascope1_we
datascope1_di	[ 31 : 0 ]

Outputs
awready
wready
bvalid
bid	[ 11 : 0 ]
bresp	[ 1 : 0 ]
arready
rdata	[ 31 : 0 ]
rvalid
rid	[ 11 : 0 ]
rlast
rresp	[ 1 : 0 ]
soft_write_addr	[ADDRESS_BITS - 1 : 0 ]
soft_write_data	[ 31 : 0 ]
soft_write_en
hba_arst
port_arst
port_arst_any
hba_dout	[ 31 : 0 ]
pgm_ad	reg [ 17 : 0 ]
pgm_wa	reg
pgm_wd	reg
afi_wcache	reg [ 3 : 0 ]
afi_rcache	reg [ 3 : 0 ]
afi_cache_set
was_hba_rst
was_port_rst
drp_en	reg
drp_we	reg
drp_addr	reg [ 14 : 0 ]
drp_di	reg [ 15 : 0 ]

Parameters
ADDRESS_BITS	10
HBA_RESET_BITS	9
RESET_TO_FIRST_ACCESS	1
DRP_ADDR	'h3fb
AXIBRAM_BITS	ADDRESS_BITS + 2
HBA_PORT__PxSCTL__DET__MASK01	HBA_PORT__PxSCTL__DET__MASK & ~1

GENERATE
GENERATE [284]

Includes

ahci_localparams.vh

ahci_defaults.vh

ahci_types.vh

Signals
reg[ 15 : 0 ]	drp_read_data
reg	drp_read_r
reg	drp_ready_r
wire[ 31 : 0 ]	datascope_rdata
reg[ 1 : 0 ]	datascope_sel
wire[ 31 : 0 ]	datascope1_rdata
reg[ 1 : 0 ]	datascope1_sel
wire[AXIBRAM_BITS - 1 : 0 ]	bram_waddr
wire[AXIBRAM_BITS - 1 : 0 ]	bram_raddr
wire[ 31 : 0 ]	bram_rdata
wire	pre_bram_wen
wire	bram_wen
wire[ 3 : 0 ]	bram_wstb
wire[ 31 : 0 ]	bram_wdata
wire[ADDRESS_BITS - 1 : 0 ]	bram_addr
wire[ 1 : 0 ]	bram_ren
reg	write_busy_r
wire	write_start_burst
wire	write_busy_w
reg[ 31 : 0 ]	bram_wdata_r
reg[ 31 : 0 ]	bram_rdata_r
wire[ 63 : 0 ]	regbit_type
wire[ 31 : 0 ]	ahci_regs_di
reg[ 3 : 0 ]	bram_wstb_r
reg	bram_wen_r
wire[ 31 : 0 ]	wmask
reg[ADDRESS_BITS - 1 : 0 ]	bram_waddr_r
reg[HBA_RESET_BITS - 1 : 0 ]	hba_reset_cntr
reg	hba_rst_r
reg	port_rst_r
reg	port_arst_any_r
wire	high_sel
wire	afi_cache_set_w
wire	pgm_fsm_set_w
wire	pgm_fsm_and_w
wire	set_hba_rst
wire	set_port_rst
wire	port_rst_on
reg	was_hba_rst_aclk
reg	was_port_rst_aclk
reg[ 2 : 0 ]	was_hba_rst_r
reg[ 2 : 0 ]	was_port_rst_r
reg[ 2 : 0 ]	arst_r
reg	wait_first_access
wire	any_access
reg	debug_rd_r
reg[ 31 : 0 ]	debug_r

Module Instances
axibram_write::axibram_write_i	Module axibram_write
axibram_read::axibram_read_i	Module axibram_read
ramt_var_wb_var_r::ahci_regs_i	Module ramt_var_wb_var_r
ram_var_w_var_r::ahci_regs_type_i	Module ram_var_w_var_r
ram_var_w_var_r::datascope_mem_i	Module ram_var_w_var_r
ram_var_w_var_r::datascope1_mem_i	Module ram_var_w_var_r
fifo_cross_clocks::ahci_regs_set_i	Module fifo_cross_clocks
pulse_cross_clock::afi_cache_set_i	Module pulse_cross_clock

Detailed Description

Definition at line 45 of file axi_ahci_regs.v.

Member Function Documentation

ALWAYS_594 (   aclk   )

Always Construct

Definition at line 161 of file axi_ahci_regs.v.

ALWAYS_595 (   aclk   )

Always Construct

Definition at line 233 of file axi_ahci_regs.v.

ALWAYS_596 (   aclk   )

Always Construct

Definition at line 298 of file axi_ahci_regs.v.

ALWAYS_597 (   aclk   )

Always Construct

Definition at line 308 of file axi_ahci_regs.v.

ALWAYS_598 (   hba_clk   )

Always Construct

Definition at line 329 of file axi_ahci_regs.v.

ALWAYS_599 (   aclk   )

Always Construct

Definition at line 336 of file axi_ahci_regs.v.

ALWAYS_600 (   aclk   )

Always Construct

Definition at line 341 of file axi_ahci_regs.v.

Member Data Documentation

ADDRESS_BITS 10

Parameter

Definition at line 47 of file axi_ahci_regs.v.

HBA_RESET_BITS 9

Parameter

Definition at line 48 of file axi_ahci_regs.v.

RESET_TO_FIRST_ACCESS 1

Parameter

Definition at line 49 of file axi_ahci_regs.v.

aclk

Input

Definition at line 51 of file axi_ahci_regs.v.

arst

Input

Definition at line 52 of file axi_ahci_regs.v.

awaddr [ 31 : 0 ]

Input

Definition at line 55 of file axi_ahci_regs.v.

awvalid

Input

Definition at line 56 of file axi_ahci_regs.v.

awready

Output

Definition at line 57 of file axi_ahci_regs.v.

awid [ 11 : 0 ]

Input

Definition at line 58 of file axi_ahci_regs.v.

awlen [ 3 : 0 ]

Input

Definition at line 59 of file axi_ahci_regs.v.

awsize [ 1 : 0 ]

Input

Definition at line 60 of file axi_ahci_regs.v.

awburst [ 1 : 0 ]

Input

Definition at line 61 of file axi_ahci_regs.v.

wdata [ 31 : 0 ]

Input

Definition at line 63 of file axi_ahci_regs.v.

wvalid

Input

Definition at line 64 of file axi_ahci_regs.v.

wready

Output

Definition at line 65 of file axi_ahci_regs.v.

wid [ 11 : 0 ]

Input

Definition at line 66 of file axi_ahci_regs.v.

wlast

Input

Definition at line 67 of file axi_ahci_regs.v.

wstb [ 3 : 0 ]

Input

Definition at line 68 of file axi_ahci_regs.v.

bvalid

Output

Definition at line 70 of file axi_ahci_regs.v.

bready

Input

Definition at line 71 of file axi_ahci_regs.v.

bid [ 11 : 0 ]

Output

Definition at line 72 of file axi_ahci_regs.v.

bresp [ 1 : 0 ]

Output

Definition at line 73 of file axi_ahci_regs.v.

araddr [ 31 : 0 ]

Input

Definition at line 75 of file axi_ahci_regs.v.

arvalid

Input

Definition at line 76 of file axi_ahci_regs.v.

arready

Output

Definition at line 77 of file axi_ahci_regs.v.

arid [ 11 : 0 ]

Input

Definition at line 78 of file axi_ahci_regs.v.

arlen [ 3 : 0 ]

Input

Definition at line 79 of file axi_ahci_regs.v.

arsize [ 1 : 0 ]

Input

Definition at line 80 of file axi_ahci_regs.v.

arburst [ 1 : 0 ]

Input

Definition at line 81 of file axi_ahci_regs.v.

rdata [ 31 : 0 ]

Output

Definition at line 83 of file axi_ahci_regs.v.

rvalid

Output

Definition at line 84 of file axi_ahci_regs.v.

rready

Input

Definition at line 85 of file axi_ahci_regs.v.

rid [ 11 : 0 ]

Output

Definition at line 86 of file axi_ahci_regs.v.

rlast

Output

Definition at line 87 of file axi_ahci_regs.v.

rresp [ 1 : 0 ]

Output

Definition at line 88 of file axi_ahci_regs.v.

soft_write_addr [ADDRESS_BITS - 1 : 0 ]

Output

Definition at line 92 of file axi_ahci_regs.v.

soft_write_data [ 31 : 0 ]

Output

Definition at line 93 of file axi_ahci_regs.v.

soft_write_en

Output

Definition at line 94 of file axi_ahci_regs.v.

hba_arst

Output

Definition at line 96 of file axi_ahci_regs.v.

port_arst

Output

Definition at line 97 of file axi_ahci_regs.v.

port_arst_any

Output

Definition at line 98 of file axi_ahci_regs.v.

hba_clk

Input

Definition at line 101 of file axi_ahci_regs.v.

hba_rst

Input

Definition at line 102 of file axi_ahci_regs.v.

hba_addr [ADDRESS_BITS - 1 : 0 ]

Input

Definition at line 103 of file axi_ahci_regs.v.

hba_we

Input

Definition at line 104 of file axi_ahci_regs.v.

hba_re [ 1 : 0 ]

Input

Definition at line 106 of file axi_ahci_regs.v.

hba_din [ 31 : 0 ]

Input

Definition at line 107 of file axi_ahci_regs.v.

hba_dout [ 31 : 0 ]

Output

Definition at line 108 of file axi_ahci_regs.v.

pgm_ad reg [ 17 : 0 ]

Output

Definition at line 111 of file axi_ahci_regs.v.

pgm_wa reg

Output

Definition at line 112 of file axi_ahci_regs.v.

pgm_wd reg

Output

Definition at line 113 of file axi_ahci_regs.v.

afi_wcache reg [ 3 : 0 ]

Output

Definition at line 118 of file axi_ahci_regs.v.

afi_rcache reg [ 3 : 0 ]

Output

Definition at line 119 of file axi_ahci_regs.v.

afi_cache_set

Output

Definition at line 120 of file axi_ahci_regs.v.

was_hba_rst

Output

Definition at line 121 of file axi_ahci_regs.v.

was_port_rst

Output

Definition at line 122 of file axi_ahci_regs.v.

debug_in0 [ 31 : 0 ]

Input

Definition at line 123 of file axi_ahci_regs.v.

debug_in1 [ 31 : 0 ]

Input

Definition at line 124 of file axi_ahci_regs.v.

debug_in2 [ 31 : 0 ]

Input

Definition at line 125 of file axi_ahci_regs.v.

debug_in3 [ 31 : 0 ]

Input

Definition at line 126 of file axi_ahci_regs.v.

drp_en reg

Output

Definition at line 128 of file axi_ahci_regs.v.

drp_we reg

Output

Definition at line 129 of file axi_ahci_regs.v.

drp_addr reg [ 14 : 0 ]

Output

Definition at line 130 of file axi_ahci_regs.v.

drp_di reg [ 15 : 0 ]

Output

Definition at line 131 of file axi_ahci_regs.v.

drp_rdy

Input

Definition at line 132 of file axi_ahci_regs.v.

drp_do [ 15 : 0 ]

Input

Definition at line 133 of file axi_ahci_regs.v.

datascope_clk

Input

Definition at line 137 of file axi_ahci_regs.v.

datascope_waddr [ADDRESS_BITS - 1 : 0 ]

Input

Definition at line 138 of file axi_ahci_regs.v.

datascope_we

Input

Definition at line 139 of file axi_ahci_regs.v.

datascope_di [ 31 : 0 ]

Input

Definition at line 140 of file axi_ahci_regs.v.

datascope1_clk

Input

Definition at line 142 of file axi_ahci_regs.v.

datascope1_waddr [ADDRESS_BITS - 1 : 0 ]

Input

Definition at line 143 of file axi_ahci_regs.v.

datascope1_we

Input

Definition at line 144 of file axi_ahci_regs.v.

datascope1_di [ 31 : 0 ]

Input

Definition at line 145 of file axi_ahci_regs.v.

DRP_ADDR 'h3fb

Parameter

Definition at line 149 of file axi_ahci_regs.v.

drp_read_data

Signal

Definition at line 150 of file axi_ahci_regs.v.

drp_read_r

Signal

Definition at line 151 of file axi_ahci_regs.v.

drp_ready_r

Signal

Definition at line 152 of file axi_ahci_regs.v.

AXIBRAM_BITS ADDRESS_BITS + 2

Parameter

Definition at line 156 of file axi_ahci_regs.v.

datascope_rdata

Signal

Definition at line 157 of file axi_ahci_regs.v.

datascope_sel

Signal

Definition at line 158 of file axi_ahci_regs.v.

datascope1_rdata

Signal

Definition at line 159 of file axi_ahci_regs.v.

datascope1_sel

Signal

Definition at line 160 of file axi_ahci_regs.v.

bram_waddr

Signal

Definition at line 168 of file axi_ahci_regs.v.

bram_raddr

Signal

Definition at line 170 of file axi_ahci_regs.v.

bram_rdata

Signal

Definition at line 171 of file axi_ahci_regs.v.

pre_bram_wen

Signal

Definition at line 172 of file axi_ahci_regs.v.

bram_wen

Signal

Definition at line 173 of file axi_ahci_regs.v.

bram_wstb

Signal

Definition at line 174 of file axi_ahci_regs.v.

bram_wdata

Signal

Definition at line 175 of file axi_ahci_regs.v.

bram_addr

Signal

Definition at line 176 of file axi_ahci_regs.v.

bram_ren

Signal

Definition at line 179 of file axi_ahci_regs.v.

write_busy_r

Signal

Definition at line 180 of file axi_ahci_regs.v.

write_start_burst

Signal

Definition at line 181 of file axi_ahci_regs.v.

write_busy_w

Signal

Definition at line 184 of file axi_ahci_regs.v.

bram_wdata_r

Signal

Definition at line 185 of file axi_ahci_regs.v.

bram_rdata_r

Signal

Definition at line 186 of file axi_ahci_regs.v.

regbit_type

Signal

Definition at line 188 of file axi_ahci_regs.v.

ahci_regs_di

Signal

Definition at line 189 of file axi_ahci_regs.v.

bram_wstb_r

Signal

Definition at line 190 of file axi_ahci_regs.v.

bram_wen_r

Signal

Definition at line 191 of file axi_ahci_regs.v.

wmask

Signal

Definition at line 193 of file axi_ahci_regs.v.

bram_waddr_r

Signal

Definition at line 194 of file axi_ahci_regs.v.

hba_reset_cntr

Signal

Definition at line 196 of file axi_ahci_regs.v.

hba_rst_r

Signal

Definition at line 197 of file axi_ahci_regs.v.

port_rst_r

Signal

Definition at line 198 of file axi_ahci_regs.v.

port_arst_any_r

Signal

Definition at line 199 of file axi_ahci_regs.v.

high_sel

Signal

Definition at line 201 of file axi_ahci_regs.v.

afi_cache_set_w

Signal

Definition at line 202 of file axi_ahci_regs.v.

pgm_fsm_set_w

Signal

Definition at line 203 of file axi_ahci_regs.v.

pgm_fsm_and_w

Signal

Definition at line 204 of file axi_ahci_regs.v.

set_hba_rst

Signal

Definition at line 206 of file axi_ahci_regs.v.

HBA_PORT__PxSCTL__DET__MASK01 HBA_PORT__PxSCTL__DET__MASK & ~1

Parameter

Definition at line 207 of file axi_ahci_regs.v.

set_port_rst

Signal

Definition at line 208 of file axi_ahci_regs.v.

port_rst_on

Signal

Definition at line 212 of file axi_ahci_regs.v.

was_hba_rst_aclk

Signal

Definition at line 213 of file axi_ahci_regs.v.

was_port_rst_aclk

Signal

Definition at line 214 of file axi_ahci_regs.v.

was_hba_rst_r

Signal

Definition at line 215 of file axi_ahci_regs.v.

was_port_rst_r

Signal

Definition at line 216 of file axi_ahci_regs.v.

arst_r

Signal

Definition at line 217 of file axi_ahci_regs.v.

wait_first_access

Signal

Definition at line 218 of file axi_ahci_regs.v.

any_access

Signal

Definition at line 219 of file axi_ahci_regs.v.

debug_rd_r

Signal

Definition at line 220 of file axi_ahci_regs.v.

debug_r

Signal

Definition at line 221 of file axi_ahci_regs.v.

ahci_defaults.vh include

Include

Definition at line 466 of file axi_ahci_regs.v.

ahci_localparams.vh include

Include

Definition at line 167 of file axi_ahci_regs.v.

ahci_types.vh include

Include

Definition at line 490 of file axi_ahci_regs.v.

axibram_read axibram_read_i

Module Instance

Definition at line 419 of file axi_ahci_regs.v.

axibram_write axibram_write_i

Module Instance

Definition at line 385 of file axi_ahci_regs.v.

fifo_cross_clocks ahci_regs_set_i

Module Instance

Definition at line 542 of file axi_ahci_regs.v.

GENERATE [284]

GENERATE

Definition at line 284 of file axi_ahci_regs.v.

pulse_cross_clock afi_cache_set_i

Module Instance

Definition at line 559 of file axi_ahci_regs.v.

ram_var_w_var_r ahci_regs_type_i

Module Instance

Definition at line 485 of file axi_ahci_regs.v.

ram_var_w_var_r datascope_mem_i

Module Instance

Definition at line 505 of file axi_ahci_regs.v.

ram_var_w_var_r datascope1_mem_i

Module Instance

Definition at line 523 of file axi_ahci_regs.v.

ramt_var_wb_var_r ahci_regs_i

Module Instance

Definition at line 459 of file axi_ahci_regs.v.

---

The documentation for this Module was generated from the following files:

• x393_sata/ahci/axi_ahci_regs.v