592
15550RXPMARESET_TIME5'h11
15583debug_cntr5reg[15:0]
15589error_countreg[11:0]
15497rxdata_outwire[DATA_BYTE_WIDTH*8-1:0]
15429debug_detected_alignp
15504rxnotintablewire[DATA_BYTE_WIDTH-1:0]
wire [DATA_BYTE_WIDTH * 8 - 1:0] 15465ll_data_out
15500rxchariskwire[DATA_BYTE_WIDTH-1:0]
15503rxdisperrwire[DATA_BYTE_WIDTH-1:0]
wire 15404rxcominitdet_in
15496rxdatawire[DATA_BYTE_WIDTH*8-1:0]
wire [DATA_BYTE_WIDTH*8 - 1:0] 15422rxdata_out
15555RXEYERESET_TIME7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME
wire [DATA_BYTE_WIDTH - 1:0] 15469ll_charisk_in
15588dbg_clk_align_waitreg
15587dbg_clk_align_cntrreg[15:0]
wire [DATA_BYTE_WIDTH*8 - 1:0] 15416txdata_in
15585debug_rxbyteisaligned_rreg[1:0]
15522clk_phase_align_ackwire
15448DATASCOPE_POST_MEAS16
15447DATASCOPE_START_BIT14
15552RXCDRFREQRESET_TIME5'h1
wire 15405rxcomwakedet_in
15569TXPCSRESET_CYCLES100
wire [DATA_BYTE_WIDTH - 1:0] 15421rxcharisk_in
15501txcharisk_inwire[DATA_BYTE_WIDTH-1:0]
ext_clock_buf IBUFDS_GTE2
wire 15414clk_phase_align_req
15584debug_cntr6reg[15:0]
15566sata_reset_done_rreg[2:0]
15495txdatawire[DATA_BYTE_WIDTH*8-1:0]
[7:0] 15558RST_TIMER_LIMIT8'b1000
wire [DATA_BYTE_WIDTH - 1:0] 15423rxcharisk_out
15574rxreset_oob_stopwire
15527dbg_rxdlysresetdonewire
15549txpmareset_cntreg[2:0]
[ADDRESS_BITS-1:0] 15481datascope_waddr
wire [DATA_BYTE_WIDTH*8 - 1:0] 15418txdata_out
[1:0] 15578CLKSWING_CFG2'b11
wire [DATA_BYTE_WIDTH * 8 - 1:0] 15468ll_data_in
wire [DATA_BYTE_WIDTH - 1:0] 15467ll_err_out
15556rxeyereset_cntreg[6:0]
15499txchariskwire[DATA_BYTE_WIDTH-1:0]
wire [DATA_BYTE_WIDTH - 1:0] 15419txcharisk_out
15553RXDFELPMRESET_TIME7'hf
15525dbg_rx_clocks_alignedwire
wire [DATA_BYTE_WIDTH - 1:0] 15417txcharisk_in
wire 15415clk_phase_align_ack
15524dbg_rxphaligndonewire
wire [DATA_BYTE_WIDTH - 1:0] 15466ll_charisk_out
15502rxcharisk_outwire[DATA_BYTE_WIDTH-1:0]
15494debug_detected_alignp
15498txdata_inwire[DATA_BYTE_WIDTH*8-1:0]
15554RXISCANRESET_TIME5'h1
15505txbufstatuswire[1:0]
15573rxreset_oob_cntreg[3:0]
15551RXCDRPHRESET_TIME5'h1
15521clk_phase_align_reqwire
15571txpcsreset_cntrreg[7:0]
wire [DATA_BYTE_WIDTH*8 - 1:0] 15420rxdata_in
wire 15424rxbyteisaligned
wire [11:0] 15458debug_cnt