Static Public Member Functions

Always Constructs
ALWAYS_691	( gtrefclk )
ALWAYS_692	( gtrefclk )
ALWAYS_693	( clk or sata_areset )
ALWAYS_694	( gtrefclk )
ALWAYS_695	( clk or extrst )
ALWAYS_696	( clk )
ALWAYS_697	( clk or extrst )
ALWAYS_698	( txoutclk )
ALWAYS_699	( gtrefclk )
ALWAYS_700	( clk )
ALWAYS_701	( reliable_clk )
ALWAYS_702	( txoutclk )
ALWAYS_703	( clk )
ALWAYS_704	( clk )

Public Attributes

Inputs
extrst	wire
reliable_clk	wire
extclk_p	wire
extclk_n	wire
rxp_in	wire
rxn_in	wire
ll_data_in	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
ll_charisk_in	wire [DATA_BYTE_WIDTH - 1 : 0 ]
set_offline
comreset_send
datascope_trig
drp_rst
drp_clk
drp_en
drp_we
drp_addr	[ 14 : 0 ]
drp_di	[ 15 : 0 ]

Outputs
clk	wire
rst	wire
phy_ready	wire
gtx_ready	wire
debug_cnt	wire [ 11 : 0 ]
txp_out	wire
txn_out	wire
ll_data_out	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
ll_charisk_out	wire [DATA_BYTE_WIDTH - 1 : 0 ]
ll_err_out	wire [DATA_BYTE_WIDTH - 1 : 0 ]
cominit_got	wire
comwake_got	wire
rxelsfull	wire
rxelsempty	wire
cplllock_debug
usrpll_locked_debug
re_aligned
xclk
datascope_clk
datascope_waddr	[ADDRESS_BITS - 1 : 0 ]
datascope_we
datascope_di	[ 31 : 0 ]
drp_rdy
drp_do	[ 15 : 0 ]
debug_sata	[ 31 : 0 ]
debug_detected_alignp

Parameters
ADDRESS_BITS	10
DATASCOPE_START_BIT	14
DATASCOPE_POST_MEAS	16
DATA_BYTE_WIDTH	4
ELASTIC_DEPTH	4
ELASTIC_OFFSET	7
TXPMARESET_TIME	5 'h1
RXPMARESET_TIME	5 'h11
RXCDRPHRESET_TIME	5 'h1
RXCDRFREQRESET_TIME	5 'h1
RXDFELPMRESET_TIME	7 'hf
RXISCANRESET_TIME	5 'h1
RXEYERESET_TIME	7 'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME
RST_TIMER_LIMIT	[ 7 : 0 ] 8 'b1000
TXPCSRESET_CYCLES	100
CLKSWING_CFG	[ 1 : 0 ] 2 'b11

Signals
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	txdata
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	rxdata
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	rxdata_out
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	txdata_in
wire[DATA_BYTE_WIDTH - 1 : 0 ]	txcharisk
wire[DATA_BYTE_WIDTH - 1 : 0 ]	rxcharisk
wire[DATA_BYTE_WIDTH - 1 : 0 ]	txcharisk_in
wire[DATA_BYTE_WIDTH - 1 : 0 ]	rxcharisk_out
wire[DATA_BYTE_WIDTH - 1 : 0 ]	rxdisperr
wire[DATA_BYTE_WIDTH - 1 : 0 ]	rxnotintable
wire[ 1 : 0 ]	txbufstatus
reg	gtx_configured
wire	sata_reset_done
wire	rxcomwakedet
wire	rxcominitdet
wire	cplllock
wire	txcominit
wire	txcomwake
wire	rxreset
wire	rxelecidle
wire	txelecidle
wire	rxbyteisaligned
wire	txpcsreset_req
wire	recal_tx_done
wire	rxreset_req
wire	rxreset_ack
wire	clk_phase_align_req
wire	clk_phase_align_ack
wire	rxreset_oob
wire	dbg_rxphaligndone
wire	dbg_rx_clocks_aligned
wire	dbg_rxcdrlock
wire	dbg_rxdlysresetdone
wire	dummy
wire	cplllockdetclk
wire	cpllreset
wire	gtrefclk
wire	rxresetdone
wire	txresetdone
wire	txpcsreset
wire	txreset
wire	txuserrdy
wire	rxuserrdy
wire	txusrclk
wire	txusrclk2
wire	rxusrclk2
wire	txp
wire	txn
wire	rxp
wire	rxn
wire	txoutclk
wire	txpmareset_done
wire	rxeyereset_done
reg[ 2 : 0 ]	txpmareset_cnt
reg[ 6 : 0 ]	rxeyereset_cnt
wire	usrpll_locked
reg	rxreset_f
reg	txreset_f
reg	rxreset_f_r
reg	txreset_f_r
reg	rxreset_f_rr
reg	txreset_f_rr
reg	sata_areset
reg[ 2 : 0 ]	sata_reset_done_r
reg[ 7 : 0 ]	rst_timer
reg	cplllock_r
reg	txpcsreset_r
reg[ 7 : 0 ]	txpcsreset_cntr
reg	recal_tx_done_r
reg[ 3 : 0 ]	rxreset_oob_cnt
wire	rxreset_oob_stop
wire	usrclk_global
wire	usrclk2
reg	usrclk2_r
reg[ 3 : 0 ]	debug_cntr1
reg[ 3 : 0 ]	debug_cntr2
reg[ 3 : 0 ]	debug_cntr3
reg[ 3 : 0 ]	debug_cntr4
reg[ 15 : 0 ]	debug_cntr5
reg[ 15 : 0 ]	debug_cntr6
reg[ 1 : 0 ]	debug_rxbyteisaligned_r
reg	debug_error_r
reg[ 15 : 0 ]	dbg_clk_align_cntr
reg	dbg_clk_align_wait
reg[ 11 : 0 ]	error_count

Module Instances
oob_ctrl::oob_ctrl	Module oob_ctrl
select_clk_buf::bufg_sclk	Module select_clk_buf
IBUFDS_GTE2::ext_clock_buf	Module IBUFDS_GTE2
gtx_wrap::gtx_wrap	Module gtx_wrap