Static Public Member Functions

Always Constructs
ALWAYS_650	( rxusrclk2 )
ALWAYS_651	( txusrclk2 )
ALWAYS_652	( drp_clk )
ALWAYS_653	( xclk )
ALWAYS_654	( xclk )
ALWAYS_655	( xclk )
ALWAYS_656	( rxusrclk2 )
ALWAYS_657	( txusrclk2 )
ALWAYS_658	( gtrefclk )

Public Attributes

Outputs
debug	reg

Parameters
ADDRESS_BITS	10
DATASCOPE_START_BIT	14
DATASCOPE_POST_MEAS	16
DATA_BYTE_WIDTH	4
TXPMARESET_TIME	5 'h1
RXPMARESET_TIME	5 'h11
RXCDRPHRESET_TIME	5 'h1
RXCDRFREQRESET_TIME	5 'h1
RXDFELPMRESET_TIME	7 'hf
RXISCANRESET_TIME	5 'h1
ELASTIC_DEPTH	4
ELASTIC_OFFSET	7

GENERATE
GENERATE [201]

Signals
wire	rxresetdone_gtx
wire	txresetdone_gtx
reg	wrap_rxreset_
reg	wrap_txreset_
wire[ 63 : 0 ]	rxdata_gtx
wire[ 7 : 0 ]	rxcharisk_gtx
wire[ 7 : 0 ]	rxdisperr_gtx
wire[ 63 : 0 ]	txdata_gtx
wire[ 7 : 0 ]	txcharisk_gtx
wire[ 7 : 0 ]	txchardispval_gtx
wire[ 7 : 0 ]	txchardispmode_gtx
wire[ 19 : 0 ]	txdata_enc_out
wire[ 15 : 0 ]	txdata_enc_in
wire[ 1 : 0 ]	txcharisk_enc_in
wire	txcominit_gtx
wire	txcomwake_gtx
wire	txelecidle_gtx
wire[ 1 : 0 ]	drp_en_w
wire[ 1 : 0 ]	drp_we_w
reg[ 1 : 0 ]	drp_sel
wire[ 15 : 0 ]	drp_do_gtx
wire[ 15 : 0 ]	drp_do_meas
wire	drp_rdy_gtx
wire	drp_rdy_meas
wire[ 15 : 0 ]	other_control
wire	rxdlysreset
reg	rxphaligndone1_r
reg	rxphaligndone2_r
reg	rx_clocks_aligned
reg	rxdlysresetdone_r
wire	rxphaligndone
wire	rxdlysresetdone
wire	rxcdrlock
wire	bypass_aligned
wire	first_confirm
wire[ 19 : 0 ]	rxdata_comma_out
wire[ 19 : 0 ]	gtx_rx_data20
wire[ 19 : 0 ]	rxdata_comma_in
wire	RXPHDLYRESET
wire	RXPHALIGN
wire	RXPHALIGNEN
wire	RXPHDLYPD
wire	RXPHOVRDEN
wire	RXDLYSRESET
wire	RXDLYBYPASS
wire	RXDLYEN
wire	RXDLYOVRDEN
wire	RXDDIEN
wire	RXLPMEN
reg[ 19 : 0 ]	rxdata_comma_in_r
wire	comma
wire	realign
wire	state_nonaligned
reg	state_aligned
reg	state_triggered
wire	set_aligned
wire	set_triggered
wire	clr_aligned
wire	clr_triggered
wire[ 15 : 0 ]	rxdata_dec_out
wire[ 1 : 0 ]	rxcharisk_dec_out
wire[ 1 : 0 ]	rxnotintable_dec_out
wire[ 1 : 0 ]	rxdisperr_dec_out
wire	rxcomwakedet_gtx
wire	rxcominitdet_gtx
reg	rxresetdone_r
reg	txresetdone_r
wire	txoutclk_gtx
wire	xclk_gtx

Module Instances
resync_data::txdata_resynchro	Module resync_data [generate]
gtx_8x10enc::gtx_8x10enc	Module gtx_8x10enc
drp_other_registers::drp_other_registers_i	Module drp_other_registers
gtx_comma_align::gtx_comma_align	Module gtx_comma_align
gtx_10x8dec::gtx_10x8dec	Module gtx_10x8dec
elastic1632::elastic1632_i	Module elastic1632
pulse_cross_clock::pulse_cross_clock_rxcominitdet_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_rxcomwakedet_i	Module pulse_cross_clock
select_clk_buf::bufg_txoutclk	Module select_clk_buf
select_clk_buf::bug_xclk	Module select_clk_buf
gtxe2_channel_wrapper::gtxe2_channel_wrapper	Module gtxe2_channel_wrapper
datascope_incoming::datascope_incoming_i	Module datascope_incoming