45 input wire clk,
// input wire // sata clk = usrclk2 46 input wire rst,
// input wire // reset oob 47 input wire gtx_ready,
// input wire // gtx is ready = all resets are done 48 output wire [
11:
0]
debug,
// output[11:0] wire 57 output wire rxreset_req,
// output wire // rx reset (after rxelecidle -> 0) 59 // Andrey: adding new signal and state - after RX is operational try re-align clock 60 output wire clk_phase_align_req,
// Request GTX to align SIPO parallel clock and user- provided RXUSRCLK 61 input wire clk_phase_align_ack,
// GTX aligned clock phase (DEBUG - not always clear when it works or not) 63 input wire [
DATA_BYTE_WIDTH*
8 -
1:
0]
txdata_in,
// output[31:0] wire // input data stream (if any data during OOB setting => ignored) 72 output wire phy_ready,
// output wire // shows if channel is ready 79 // oob sequence needs to be issued 81 // connection established, all further data is valid 84 // doc p265, link is established after 3back-to-back non-ALIGNp 88 // the device itself sends cominit 90 // allow to respond to cominit 93 // status information to handle by a control block if any exists 94 // incompatible host-device speed grades (host cannot lock to alignp) 96 // timeout in an unexpected place 98 // noone responds to our cominits 103 // 1 - link is up and running, 0 - probably not 105 // 1 - connection is being established OR already established, 0 - is not 108 // Andrey: Force offline from AHCI 110 always @ (
posedge clk)
begin 116 // Andrey: Make phy ready not go inactive during re-aligning 117 ///assign phy_ready = link_state & gtx_ready & rxbyteisaligned; 120 always @ (
posedge clk)
begin 136 // decide when to issue oob: always when gtx is ready 137 //assign oob_start = gtx_ready & ~oob_state & ~oob_busy; 140 // set line to idle state before if we're waiting for a device to answer AND while oob sequence 142 //assign txelecidle = /*~oob_state |*/ txelecidle_inner ; 145 // let devices always begin oob sequence, if only it's not a glitch 155 .
clk (
clk),
// input wire // sata clk = usrclk2 156 .
rst (
rst),
// input wire // reset oob 169 .
txdata_in (
txdata_in),
// input [31:0] wire // input data stream (if any data during OOB setting => ignored) 178 .
oob_done (
oob_done),
// output wire // connection established, all further data is valid 180 .
link_up (
link_up),
// output wire // doc p265, link is established after 3back-to-back non-ALIGNp 184 // status information to handle by a control block if any exists wire 15320oob_incompatible
15429debug_detected_alignp
wire 15404rxcominitdet_in
wire [DATA_BYTE_WIDTH*8 - 1:0] 15422rxdata_out
wire [DATA_BYTE_WIDTH*8 - 1:0] 15307txdata_out
wire [DATA_BYTE_WIDTH*8 - 1:0] 15416txdata_in
wire [DATA_BYTE_WIDTH - 1:0] 15312rxcharisk_out
wire [DATA_BYTE_WIDTH*8 - 1:0] 15305txdata_in
wire 15405rxcomwakedet_in
wire [DATA_BYTE_WIDTH - 1:0] 15310rxcharisk_in
wire [DATA_BYTE_WIDTH - 1:0] 15421rxcharisk_in
wire 15414clk_phase_align_req
wire 15293rxcominitdet_in
wire [DATA_BYTE_WIDTH - 1:0] 15423rxcharisk_out
wire [DATA_BYTE_WIDTH*8 - 1:0] 15309rxdata_in
wire [DATA_BYTE_WIDTH*8 - 1:0] 15418txdata_out
wire 15304clk_phase_align_ack
15436oob_incompatiblewire
wire 15294rxcomwakedet_in
wire 15303clk_phase_align_req
15445txelecidle_innerwire
wire [DATA_BYTE_WIDTH - 1:0] 15419txcharisk_out
wire [DATA_BYTE_WIDTH - 1:0] 15417txcharisk_in
15323debug_detected_alignp
wire 15415clk_phase_align_ack
wire [DATA_BYTE_WIDTH*8 - 1:0] 15311rxdata_out
wire [DATA_BYTE_WIDTH - 1:0] 15308txcharisk_out
wire [DATA_BYTE_WIDTH*8 - 1:0] 15420rxdata_in
wire 15424rxbyteisaligned
wire [DATA_BYTE_WIDTH - 1:0] 15306txcharisk_in