x393  1.0
FPGAcodeforElphelNC393camera
ram18p_var_w_var_r.v
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1 
63  // This file may be used to define same pre-processor macros to be included into each parsed file
64 `ifndef SYSTEM_DEFINES
65  `define SYSTEM_DEFINES
66  // TODO: Later compare instantiate/infer
67  `define INSTANTIATE_DSP48E1
68  `define DEBUG_DCT1D// undefine after debugging is over // `define USE_OLD_DCT
69 
70 // Parameters from x393_sata project
71  `define USE_DRP
72  `define ALIGN_CLOCKS
73 // `define STRAIGHT_XCLK
74  `define USE_DATASCOPE
75 // `define DATASCOPE_INCOMING_RAW
76  `define PRELOAD_BRAMS
77 // `define AHCI_SATA 1
78 // `define DEBUG_ELASTIC
79 // End of parameters from x393_sata project
80 
81  `define PRELOAD_BRAMS
82  `define DISPLAY_COMPRESSED_DATA // if HISPI is not defined, parallel sensor interface is used for all channels
83  `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/// `define USE_OLD_XDCT393
84 // `define USE_PCLK2X
85 // `define USE_XCLK2X
86  `define REVERSE_LANES 1 `define DEBUG_RING 1 `define USE_HARD_CURPARAMS// Adjustment of actual hardware may break simulation // `define DEBUG_SENS_MEM_PAGES 1
87 // `define MCLK_VCO_MULT 16
88 // DDR3 memory speed grade and density
89  `define sg25 1// `define sg15E 1
90 // `define sg187E 1
91  `define den4096Mb 1
92  `define MCLK_VCO_MULT 16// `define MCLK_VCO_MULT 18
93 // `define MCLK_VCO_MULT 20
94 
95  `define MEMBRIDGE_DEBUG_WRITE 1// Enviroment-dependent options
96  `ifdef IVERILOG
97  `define SIMULATION
98  `define OPEN_SOURCE_ONLY
99  `endif
100 
101  `ifdef COCOTB
102  `define SIMULATION
103  `define OPEN_SOURCE_ONLY
104  `endif
105 
106  `ifdef CVC
107  `define SIMULATION
108  `define OPEN_SOURCE_ONLY
109  `endif // CVC
110 
111 // will not use simultaneous reset in shift registers, just and input data with ~rst
112  `define SHREG_SEQUENTIAL_RESET 1// synthesis does to recognize global clock as G input of the primitive latch
113  `undef INFER_LATCHES
114  // define when using CDC - it does not support them
115  `undef IGNORE_ATTR
116 //`define MEMBRIDGE_DEBUG_READ 1
117  `define use200Mhz 1 `define USE_CMD_ENCOD_TILED_32_RD 1 // chn 0 is read from memory and write to memory
118  `define def_enable_mem_chn0
119  `define def_read_mem_chn0
120  `define def_write_mem_chn0
121  `undef def_scanline_chn0
122  `undef def_tiled_chn0
123 
124  // chn 1 is scanline r+w
125  `define def_enable_mem_chn1
126  `define def_read_mem_chn1
127  `define def_write_mem_chn1
128  `define def_scanline_chn1
129  `undef def_tiled_chn1
130 
131  // chn 2 is tiled r+w
132  `define def_enable_mem_chn2
133  `define def_read_mem_chn2
134  `define def_write_mem_chn2
135  `undef def_scanline_chn2
136  `define def_tiled_chn2
137 
138  // chn 3 is scanline r+w (reuse later)
139  `define def_enable_mem_chn3
140  `define def_read_mem_chn3
141  `define def_write_mem_chn3
142  `define def_scanline_chn3
143  `undef def_tiled_chn3
144 
145  // chn 4 is tiled r+w (reuse later)
146  `define def_enable_mem_chn4
147  `define def_read_mem_chn4
148  `define def_write_mem_chn4
149  `undef def_scanline_chn4
150  `define def_tiled_chn4
151 
152  // chn 5 is disabled
153  `undef def_enable_mem_chn5
154 
155  // chn 6 is disabled
156  `undef def_enable_mem_chn6
157 
158  // chn 7 is disabled
159  `undef def_enable_mem_chn7
160 
161  // chn 8 is scanline w (sensor channel 0)
162  `define def_enable_mem_chn8
163  `undef def_read_mem_chn8
164  `define def_write_mem_chn8
165  `define def_scanline_chn8
166  `undef def_tiled_chn8
167 
168  // chn 9 is scanline w (sensor channel 1)
169  `define def_enable_mem_chn9
170  `undef def_read_mem_chn9
171  `define def_write_mem_chn9
172  `define def_scanline_chn9
173  `undef def_tiled_chn9
174 
175  // chn 10 is scanline w (sensor channel 2)
176  `define def_enable_mem_chn10
177  `undef def_read_mem_chn10
178  `define def_write_mem_chn10
179  `define def_scanline_chn10
180  `undef def_tiled_chn10
181 
182  // chn 11 is scanline w (sensor channel 3)
183  `define def_enable_mem_chn11
184  `undef def_read_mem_chn11
185  `define def_write_mem_chn11
186  `define def_scanline_chn11
187  `undef def_tiled_chn11
188 
189  // chn 12 is tiled read (compressor channel 0)
190  `define def_enable_mem_chn12
191  `define def_read_mem_chn12
192  `undef def_write_mem_chn12
193  `undef def_scanline_chn12
194  `define def_tiled_chn12
195 
196  // chn 12 is tiled read (compressor channel 1)
197  `define def_enable_mem_chn13
198  `define def_read_mem_chn13
199  `undef def_write_mem_chn13
200  `undef def_scanline_chn13
201  `define def_tiled_chn13
202 
203  // chn 12 is tiled read (compressor channel 2)
204  `define def_enable_mem_chn14
205  `define def_read_mem_chn14
206  `undef def_write_mem_chn14
207  `undef def_scanline_chn14
208  `define def_tiled_chn14
209 
210  // chn 12 is tiled read (compressor channel 3)
211  `define def_enable_mem_chn15
212  `define def_read_mem_chn15
213  `undef def_write_mem_chn15
214  `undef def_scanline_chn15
215  `define def_tiled_chn15
216 `endif
217 
218 /*
219  Address/data widths
220  Connect unused data to 1b0, unused addresses - to 1'b1
221 
222  RAMB18E1 in True Dual Port (TDP) Mode - each port individually
223  +-----------+---------+---------+---------+
224  |Data Width | Address | Data | Parity |
225  +-----------+---------+---------+---------+
226  | 1 | A[13:0] | D[0] | --- |
227  | 2 | A[13:1] | D[1:0] | --- |
228  | 4 | A[13:2] | D[3:0[ | --- |
229  | 9 | A[13:3] | D[7:0] | DP[0] |
230  | 18 | A[13:4] | D[15:0] | DP[1:0] |
231  +-----------+---------+---------+---------+
232 
233  RAMB18E1 in Simple Dual Port (SDP) Mode
234  one of the ports (r or w) - 32/36 bits, other - variable
235  +------------+---------+---------+---------+
236  |Data Widths | Address | Data | Parity |
237  +------------+---------+---------+---------+
238  | 32/ 1 | A[13:0] | D[0] | --- |
239  | 32/ 2 | A[13:1] | D[1:0] | --- |
240  | 32/ 4 | A[13:2] | D[3:0[ | --- |
241  | 36/ 9 | A[13:3] | D[7:0] | DP[0] |
242  | 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
243  | 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
244  +------------+---------+---------+---------+
245 
246  RAMB36E1 in True Dual Port (TDP) Mode - each port individually
247  +-----------+---------+---------+---------+
248  |Data Width | Address | Data | Parity |
249  +-----------+---------+---------+---------+
250  | 1 | A[14:0] | D[0] | --- |
251  | 2 | A[14:1] | D[1:0] | --- |
252  | 4 | A[14:2] | D[3:0[ | --- |
253  | 9 | A[14:3] | D[7:0] | DP[0] |
254  | 18 | A[14:4] | D[15:0] | DP[1:0] |
255  | 36 | A[14:5] | D[31:0] | DP[3:0] |
256  |1(Cascade) | A[15:0] | D[0] | --- |
257  +-----------+---------+---------+---------+
258 
259  RAMB36E1 in Simple Dual Port (SDP) Mode
260  one of the ports (r or w) - 64/72 bits, other - variable
261  +------------+---------+---------+---------+
262  |Data Widths | Address | Data | Parity |
263  +------------+---------+---------+---------+
264  | 64/ 1 | A[14:0] | D[0] | --- |
265  | 64/ 2 | A[14:1] | D[1:0] | --- |
266  | 64/ 4 | A[14:2] | D[3:0[ | --- |
267  | 64/ 9 | A[14:3] | D[7:0] | DP[0] |
268  | 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
269  | 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
270  | 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
271  +------------+---------+---------+---------+
272 */
273 module ram18p_var_w_var_r
274 #(
275  parameter integer REGISTERS = 0, // 1 - registered output
276  parameter integer LOG2WIDTH_WR = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
277  parameter integer LOG2WIDTH_RD = 5, // WIDTH= 9 << (LOG2WIDTH - 3)
278  parameter DUMMY = 0
279 `ifdef PRELOAD_BRAMS
280  , parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
281  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
282  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
283  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
284  parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
285  parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
286  parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
287  parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
288  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
289  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
290  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
291  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
292  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
293  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
294  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
295  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
296  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
297  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
298  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
299  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
300  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
301  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
302  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
303  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
304  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
305  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
306  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
307  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
308  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
309  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
310  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
311  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
312  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
313  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
314  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
315  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
316  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
317  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
318  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
319  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
320  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
321  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
322  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
323  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
324  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
325  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
326  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
327  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
328  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
329  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
330  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
331  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
332  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
333  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
334  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
335  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
336  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
337  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
338  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
339  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
340  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
341  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
342  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
343  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
344  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
345  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
346  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
347  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
348  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
349  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
350  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
351  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
352 
353 `endif
354  )
355  (
356  input rclk, // clock for read port
357 // input [ 9:0] raddr, // read address
358  input [13-LOG2WIDTH_RD:0] raddr, // read address
359  input ren, // read port enable
360  input regen, // output register enable
361  output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
362 
363  input wclk, // clock for read port
364  input [13-LOG2WIDTH_WR:0] waddr, // write address
365  input we, // write port enable
366  input [ 3:0] web, // write byte enable
367  input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
368  );
369  generate
370  if (DUMMY)
371  ram18p_dummy #(
372  .LOG2WIDTH_RD(LOG2WIDTH_RD)
373  ) ram18p_dummy_i (
374  .data_out(data_out)
375  );
376  else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD == 5))
377  ram18p_32w_32r #(
378  .REGISTERS (REGISTERS)
379 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
380 , .INITP_01 (INITP_01)
381 , .INITP_02 (INITP_02)
382 , .INITP_03 (INITP_03)
383 , .INITP_04 (INITP_04)
384 , .INITP_05 (INITP_05)
385 , .INITP_06 (INITP_06)
386 , .INITP_07 (INITP_07)
387 , .INIT_00 (INIT_00)
388 , .INIT_01 (INIT_01)
389 , .INIT_02 (INIT_02)
390 , .INIT_03 (INIT_03)
391 , .INIT_04 (INIT_04)
392 , .INIT_05 (INIT_05)
393 , .INIT_06 (INIT_06)
394 , .INIT_07 (INIT_07)
395 , .INIT_08 (INIT_08)
396 , .INIT_09 (INIT_09)
397 , .INIT_0A (INIT_0A)
398 , .INIT_0B (INIT_0B)
399 , .INIT_0C (INIT_0C)
400 , .INIT_0D (INIT_0D)
401 , .INIT_0E (INIT_0E)
402 , .INIT_0F (INIT_0F)
403 , .INIT_10 (INIT_10)
404 , .INIT_11 (INIT_11)
405 , .INIT_12 (INIT_12)
406 , .INIT_13 (INIT_13)
407 , .INIT_14 (INIT_14)
408 , .INIT_15 (INIT_15)
409 , .INIT_16 (INIT_16)
410 , .INIT_17 (INIT_17)
411 , .INIT_18 (INIT_18)
412 , .INIT_19 (INIT_19)
413 , .INIT_1A (INIT_1A)
414 , .INIT_1B (INIT_1B)
415 , .INIT_1C (INIT_1C)
416 , .INIT_1D (INIT_1D)
417 , .INIT_1E (INIT_1E)
418 , .INIT_1F (INIT_1F)
419 , .INIT_20 (INIT_20)
420 , .INIT_21 (INIT_21)
421 , .INIT_22 (INIT_22)
422 , .INIT_23 (INIT_23)
423 , .INIT_24 (INIT_24)
424 , .INIT_25 (INIT_25)
425 , .INIT_26 (INIT_26)
426 , .INIT_27 (INIT_27)
427 , .INIT_28 (INIT_28)
428 , .INIT_29 (INIT_29)
429 , .INIT_2A (INIT_2A)
430 , .INIT_2B (INIT_2B)
431 , .INIT_2C (INIT_2C)
432 , .INIT_2D (INIT_2D)
433 , .INIT_2E (INIT_2E)
434 , .INIT_2F (INIT_2F)
435 , .INIT_30 (INIT_30)
436 , .INIT_31 (INIT_31)
437 , .INIT_32 (INIT_32)
438 , .INIT_33 (INIT_33)
439 , .INIT_34 (INIT_34)
440 , .INIT_35 (INIT_35)
441 , .INIT_36 (INIT_36)
442 , .INIT_37 (INIT_37)
443 , .INIT_38 (INIT_38)
444 , .INIT_39 (INIT_39)
445 , .INIT_3A (INIT_3A)
446 , .INIT_3B (INIT_3B)
447 , .INIT_3C (INIT_3C)
448 , .INIT_3D (INIT_3D)
449 , .INIT_3E (INIT_3E)
450 , .INIT_3F (INIT_3F)
451 
452 `endif
453  ) ram_i (
454  .rclk (rclk), // input
455  .raddr (raddr), // input[8:0]
456  .ren (ren), // input
457  .regen (regen), // input
458  .data_out (data_out), // output[35:0]
459  .wclk (wclk), // input
460  .waddr (waddr), // input[8:0]
461  .we (we), // input
462  .web (web), // input[3:0]
463  .data_in (data_in) // input[35:0]
464  );
465  else if ((LOG2WIDTH_WR == 5) && (LOG2WIDTH_RD < 5))
466  ram18p_32w_lt32r #(
467  .REGISTERS (REGISTERS),
468  .LOG2WIDTH_RD (LOG2WIDTH_RD)
469 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
470 , .INITP_01 (INITP_01)
471 , .INITP_02 (INITP_02)
472 , .INITP_03 (INITP_03)
473 , .INITP_04 (INITP_04)
474 , .INITP_05 (INITP_05)
475 , .INITP_06 (INITP_06)
476 , .INITP_07 (INITP_07)
477 , .INIT_00 (INIT_00)
478 , .INIT_01 (INIT_01)
479 , .INIT_02 (INIT_02)
480 , .INIT_03 (INIT_03)
481 , .INIT_04 (INIT_04)
482 , .INIT_05 (INIT_05)
483 , .INIT_06 (INIT_06)
484 , .INIT_07 (INIT_07)
485 , .INIT_08 (INIT_08)
486 , .INIT_09 (INIT_09)
487 , .INIT_0A (INIT_0A)
488 , .INIT_0B (INIT_0B)
489 , .INIT_0C (INIT_0C)
490 , .INIT_0D (INIT_0D)
491 , .INIT_0E (INIT_0E)
492 , .INIT_0F (INIT_0F)
493 , .INIT_10 (INIT_10)
494 , .INIT_11 (INIT_11)
495 , .INIT_12 (INIT_12)
496 , .INIT_13 (INIT_13)
497 , .INIT_14 (INIT_14)
498 , .INIT_15 (INIT_15)
499 , .INIT_16 (INIT_16)
500 , .INIT_17 (INIT_17)
501 , .INIT_18 (INIT_18)
502 , .INIT_19 (INIT_19)
503 , .INIT_1A (INIT_1A)
504 , .INIT_1B (INIT_1B)
505 , .INIT_1C (INIT_1C)
506 , .INIT_1D (INIT_1D)
507 , .INIT_1E (INIT_1E)
508 , .INIT_1F (INIT_1F)
509 , .INIT_20 (INIT_20)
510 , .INIT_21 (INIT_21)
511 , .INIT_22 (INIT_22)
512 , .INIT_23 (INIT_23)
513 , .INIT_24 (INIT_24)
514 , .INIT_25 (INIT_25)
515 , .INIT_26 (INIT_26)
516 , .INIT_27 (INIT_27)
517 , .INIT_28 (INIT_28)
518 , .INIT_29 (INIT_29)
519 , .INIT_2A (INIT_2A)
520 , .INIT_2B (INIT_2B)
521 , .INIT_2C (INIT_2C)
522 , .INIT_2D (INIT_2D)
523 , .INIT_2E (INIT_2E)
524 , .INIT_2F (INIT_2F)
525 , .INIT_30 (INIT_30)
526 , .INIT_31 (INIT_31)
527 , .INIT_32 (INIT_32)
528 , .INIT_33 (INIT_33)
529 , .INIT_34 (INIT_34)
530 , .INIT_35 (INIT_35)
531 , .INIT_36 (INIT_36)
532 , .INIT_37 (INIT_37)
533 , .INIT_38 (INIT_38)
534 , .INIT_39 (INIT_39)
535 , .INIT_3A (INIT_3A)
536 , .INIT_3B (INIT_3B)
537 , .INIT_3C (INIT_3C)
538 , .INIT_3D (INIT_3D)
539 , .INIT_3E (INIT_3E)
540 , .INIT_3F (INIT_3F)
541 
542 `endif
543  ) ram_i (
544  .rclk (rclk), // input
545  .raddr (raddr), // input[(>8):0]
546  .ren (ren), // input
547  .regen (regen), // input
548  .data_out (data_out), // output[(<35):0]
549  .wclk (wclk), // input
550  .waddr (waddr), // input[8:0]
551  .we (we), // input
552  .web (web), // input[3:0]
553  .data_in (data_in) // input[35:0]
554  );
555  else if ((LOG2WIDTH_WR < 5) && (LOG2WIDTH_RD == 5))
556  ram18p_lt32w_32r #(
557  .REGISTERS (REGISTERS),
558  .LOG2WIDTH_WR (LOG2WIDTH_WR)
559 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
560 , .INITP_01 (INITP_01)
561 , .INITP_02 (INITP_02)
562 , .INITP_03 (INITP_03)
563 , .INITP_04 (INITP_04)
564 , .INITP_05 (INITP_05)
565 , .INITP_06 (INITP_06)
566 , .INITP_07 (INITP_07)
567 , .INIT_00 (INIT_00)
568 , .INIT_01 (INIT_01)
569 , .INIT_02 (INIT_02)
570 , .INIT_03 (INIT_03)
571 , .INIT_04 (INIT_04)
572 , .INIT_05 (INIT_05)
573 , .INIT_06 (INIT_06)
574 , .INIT_07 (INIT_07)
575 , .INIT_08 (INIT_08)
576 , .INIT_09 (INIT_09)
577 , .INIT_0A (INIT_0A)
578 , .INIT_0B (INIT_0B)
579 , .INIT_0C (INIT_0C)
580 , .INIT_0D (INIT_0D)
581 , .INIT_0E (INIT_0E)
582 , .INIT_0F (INIT_0F)
583 , .INIT_10 (INIT_10)
584 , .INIT_11 (INIT_11)
585 , .INIT_12 (INIT_12)
586 , .INIT_13 (INIT_13)
587 , .INIT_14 (INIT_14)
588 , .INIT_15 (INIT_15)
589 , .INIT_16 (INIT_16)
590 , .INIT_17 (INIT_17)
591 , .INIT_18 (INIT_18)
592 , .INIT_19 (INIT_19)
593 , .INIT_1A (INIT_1A)
594 , .INIT_1B (INIT_1B)
595 , .INIT_1C (INIT_1C)
596 , .INIT_1D (INIT_1D)
597 , .INIT_1E (INIT_1E)
598 , .INIT_1F (INIT_1F)
599 , .INIT_20 (INIT_20)
600 , .INIT_21 (INIT_21)
601 , .INIT_22 (INIT_22)
602 , .INIT_23 (INIT_23)
603 , .INIT_24 (INIT_24)
604 , .INIT_25 (INIT_25)
605 , .INIT_26 (INIT_26)
606 , .INIT_27 (INIT_27)
607 , .INIT_28 (INIT_28)
608 , .INIT_29 (INIT_29)
609 , .INIT_2A (INIT_2A)
610 , .INIT_2B (INIT_2B)
611 , .INIT_2C (INIT_2C)
612 , .INIT_2D (INIT_2D)
613 , .INIT_2E (INIT_2E)
614 , .INIT_2F (INIT_2F)
615 , .INIT_30 (INIT_30)
616 , .INIT_31 (INIT_31)
617 , .INIT_32 (INIT_32)
618 , .INIT_33 (INIT_33)
619 , .INIT_34 (INIT_34)
620 , .INIT_35 (INIT_35)
621 , .INIT_36 (INIT_36)
622 , .INIT_37 (INIT_37)
623 , .INIT_38 (INIT_38)
624 , .INIT_39 (INIT_39)
625 , .INIT_3A (INIT_3A)
626 , .INIT_3B (INIT_3B)
627 , .INIT_3C (INIT_3C)
628 , .INIT_3D (INIT_3D)
629 , .INIT_3E (INIT_3E)
630 , .INIT_3F (INIT_3F)
631 
632 `endif
633  ) ram_i (
634  .rclk (rclk), // input
635  .raddr (raddr), // input[8:0]
636  .ren (ren), // input
637  .regen (regen), // input
638  .data_out (data_out), // output[35:0]
639  .wclk (wclk), // input
640  .waddr (waddr), // input[(>8):0]
641  .we (we), // input
642  .web (web), // input[3:0]
643  .data_in (data_in) // input[(<35):0]
644  );
645  else if ((LOG2WIDTH_WR < 5) && (LOG2WIDTH_RD < 5))
646  ram18p_lt32w_lt32r #(
647  .REGISTERS (REGISTERS),
648  .LOG2WIDTH_WR (LOG2WIDTH_WR),
649  .LOG2WIDTH_RD (LOG2WIDTH_RD)
650 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
651 , .INITP_01 (INITP_01)
652 , .INITP_02 (INITP_02)
653 , .INITP_03 (INITP_03)
654 , .INITP_04 (INITP_04)
655 , .INITP_05 (INITP_05)
656 , .INITP_06 (INITP_06)
657 , .INITP_07 (INITP_07)
658 , .INIT_00 (INIT_00)
659 , .INIT_01 (INIT_01)
660 , .INIT_02 (INIT_02)
661 , .INIT_03 (INIT_03)
662 , .INIT_04 (INIT_04)
663 , .INIT_05 (INIT_05)
664 , .INIT_06 (INIT_06)
665 , .INIT_07 (INIT_07)
666 , .INIT_08 (INIT_08)
667 , .INIT_09 (INIT_09)
668 , .INIT_0A (INIT_0A)
669 , .INIT_0B (INIT_0B)
670 , .INIT_0C (INIT_0C)
671 , .INIT_0D (INIT_0D)
672 , .INIT_0E (INIT_0E)
673 , .INIT_0F (INIT_0F)
674 , .INIT_10 (INIT_10)
675 , .INIT_11 (INIT_11)
676 , .INIT_12 (INIT_12)
677 , .INIT_13 (INIT_13)
678 , .INIT_14 (INIT_14)
679 , .INIT_15 (INIT_15)
680 , .INIT_16 (INIT_16)
681 , .INIT_17 (INIT_17)
682 , .INIT_18 (INIT_18)
683 , .INIT_19 (INIT_19)
684 , .INIT_1A (INIT_1A)
685 , .INIT_1B (INIT_1B)
686 , .INIT_1C (INIT_1C)
687 , .INIT_1D (INIT_1D)
688 , .INIT_1E (INIT_1E)
689 , .INIT_1F (INIT_1F)
690 , .INIT_20 (INIT_20)
691 , .INIT_21 (INIT_21)
692 , .INIT_22 (INIT_22)
693 , .INIT_23 (INIT_23)
694 , .INIT_24 (INIT_24)
695 , .INIT_25 (INIT_25)
696 , .INIT_26 (INIT_26)
697 , .INIT_27 (INIT_27)
698 , .INIT_28 (INIT_28)
699 , .INIT_29 (INIT_29)
700 , .INIT_2A (INIT_2A)
701 , .INIT_2B (INIT_2B)
702 , .INIT_2C (INIT_2C)
703 , .INIT_2D (INIT_2D)
704 , .INIT_2E (INIT_2E)
705 , .INIT_2F (INIT_2F)
706 , .INIT_30 (INIT_30)
707 , .INIT_31 (INIT_31)
708 , .INIT_32 (INIT_32)
709 , .INIT_33 (INIT_33)
710 , .INIT_34 (INIT_34)
711 , .INIT_35 (INIT_35)
712 , .INIT_36 (INIT_36)
713 , .INIT_37 (INIT_37)
714 , .INIT_38 (INIT_38)
715 , .INIT_39 (INIT_39)
716 , .INIT_3A (INIT_3A)
717 , .INIT_3B (INIT_3B)
718 , .INIT_3C (INIT_3C)
719 , .INIT_3D (INIT_3D)
720 , .INIT_3E (INIT_3E)
721 , .INIT_3F (INIT_3F)
722 
723 `endif
724  ) ram_i (
725  .rclk (rclk), // input
726  .raddr (raddr), // input[(>8):0]
727  .ren (ren), // input
728  .regen (regen), // input
729  .data_out (data_out), // output[(<35):0]
730  .wclk (wclk), // input
731  .waddr (waddr), // input[(>8):0]
732  .we (we), // input
733  .web (web), // input[7:0]
734  .data_in (data_in) // input[(<35):0]
735  );
736  endgenerate
737 endmodule
738 
739 // Both ports with 32 bit widths
740 
741 module ram18p_32w_32r
742 #(
743  parameter integer REGISTERS = 0 // 1 - registered output
744 `ifdef PRELOAD_BRAMS
745  , parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
746  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
747  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
748  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
749  parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
750  parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
751  parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
752  parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
753  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
754  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
755  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
756  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
757  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
758  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
759  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
760  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
761  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
762  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
763  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
764  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
765  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
766  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
767  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
768  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
769  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
770  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
771  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
772  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
773  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
774  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
775  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
776  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
777  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
778  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
779  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
780  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
781  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
782  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
783  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
784  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
785  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
786  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
787  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
788  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
789  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
790  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
791  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
792  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
793  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
794  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
795  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
796  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
797  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
798  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
799  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
800  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
801  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
802  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
803  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
804  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
805  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
806  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
807  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
808  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
809  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
810  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
811  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
812  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
813  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
814  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
815  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
816  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
817 
818 `endif
819  )
820  (
821  input rclk, // clock for read port
822  input [8:0] raddr, // read address
823  input ren, // read port enable
824  input regen, // output register enable
825  output [35:0] data_out, // data out
826 
827  input wclk, // clock for read port
828  input [ 8:0] waddr, // write address
829  input we, // write port enable
830  input [ 3:0] web, // write byte enable
831  input [35:0] data_in // data out
832  );
833  localparam PWIDTH_WR=36;
834  localparam PWIDTH_RD=36;
835 
836  RAMB18E1
837  #(
838  .RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
839  .RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
840  .DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
841  .DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
842  .READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
843  .READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
844  .WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
845  .WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
846  .RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
847  .WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
848  .WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
849  .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
850  .SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
851  .INIT_FILE ("NONE"), // "NONE" or filename with initialization data
852  .SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
853 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
854 , .INITP_01 (INITP_01)
855 , .INITP_02 (INITP_02)
856 , .INITP_03 (INITP_03)
857 , .INITP_04 (INITP_04)
858 , .INITP_05 (INITP_05)
859 , .INITP_06 (INITP_06)
860 , .INITP_07 (INITP_07)
861 , .INIT_00 (INIT_00)
862 , .INIT_01 (INIT_01)
863 , .INIT_02 (INIT_02)
864 , .INIT_03 (INIT_03)
865 , .INIT_04 (INIT_04)
866 , .INIT_05 (INIT_05)
867 , .INIT_06 (INIT_06)
868 , .INIT_07 (INIT_07)
869 , .INIT_08 (INIT_08)
870 , .INIT_09 (INIT_09)
871 , .INIT_0A (INIT_0A)
872 , .INIT_0B (INIT_0B)
873 , .INIT_0C (INIT_0C)
874 , .INIT_0D (INIT_0D)
875 , .INIT_0E (INIT_0E)
876 , .INIT_0F (INIT_0F)
877 , .INIT_10 (INIT_10)
878 , .INIT_11 (INIT_11)
879 , .INIT_12 (INIT_12)
880 , .INIT_13 (INIT_13)
881 , .INIT_14 (INIT_14)
882 , .INIT_15 (INIT_15)
883 , .INIT_16 (INIT_16)
884 , .INIT_17 (INIT_17)
885 , .INIT_18 (INIT_18)
886 , .INIT_19 (INIT_19)
887 , .INIT_1A (INIT_1A)
888 , .INIT_1B (INIT_1B)
889 , .INIT_1C (INIT_1C)
890 , .INIT_1D (INIT_1D)
891 , .INIT_1E (INIT_1E)
892 , .INIT_1F (INIT_1F)
893 , .INIT_20 (INIT_20)
894 , .INIT_21 (INIT_21)
895 , .INIT_22 (INIT_22)
896 , .INIT_23 (INIT_23)
897 , .INIT_24 (INIT_24)
898 , .INIT_25 (INIT_25)
899 , .INIT_26 (INIT_26)
900 , .INIT_27 (INIT_27)
901 , .INIT_28 (INIT_28)
902 , .INIT_29 (INIT_29)
903 , .INIT_2A (INIT_2A)
904 , .INIT_2B (INIT_2B)
905 , .INIT_2C (INIT_2C)
906 , .INIT_2D (INIT_2D)
907 , .INIT_2E (INIT_2E)
908 , .INIT_2F (INIT_2F)
909 , .INIT_30 (INIT_30)
910 , .INIT_31 (INIT_31)
911 , .INIT_32 (INIT_32)
912 , .INIT_33 (INIT_33)
913 , .INIT_34 (INIT_34)
914 , .INIT_35 (INIT_35)
915 , .INIT_36 (INIT_36)
916 , .INIT_37 (INIT_37)
917 , .INIT_38 (INIT_38)
918 , .INIT_39 (INIT_39)
919 , .INIT_3A (INIT_3A)
920 , .INIT_3B (INIT_3B)
921 , .INIT_3C (INIT_3C)
922 , .INIT_3D (INIT_3D)
923 , .INIT_3E (INIT_3E)
924 , .INIT_3F (INIT_3F)
925 
926 `endif
927  ) RAMB36E1_i
928  (
929  // Port A (Read port in SDP mode):
930  .DOADO (data_out[15:0]), // Port A data/LSB data[15:0], output
931  .DOPADOP (data_out[17:16]),// Port A parity/LSB parity[2:0], output
932  .DIADI (data_in[15:0]), // Port A data/LSB data[15:0], input
933  .DIPADIP (data_in[17:16]), // Port A parity/LSB parity[2:0], input
934  .ADDRARDADDR ({raddr[8:0],5'b11111}), // Port A (read port in SDP) address [13:0], unused should be high, input
935  .CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
936  .ENARDEN (ren), // Port A (read port in SDP) Enable, input
937  .REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
938  .RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
939  .RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
940  .WEA (2'b0), // Port A (read port in SDP) Write Enable[2:0], input
941  // Port B
942  .DOBDO (data_out[33:18]),// Port B data/MSB data[15:0], output
943  .DOPBDOP (data_out[35:34]),// Port B parity/MSB parity[2:0], output
944  .DIBDI (data_in[33:18]), // Port B data/MSB data[31:0], input
945  .DIPBDIP (data_in[35:34]), // Port B parity/MSB parity[1:0], input
946  .ADDRBWRADDR ({waddr[8:0],5'b11111}), // Port B (write port in SDP) address [13:0], unused should be high, input
947  .CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
948  .ENBWREN (we), // Port B (write port in SDP) Enable, input
949  .REGCEB (1'b0), // Port B (write port in SDP) register enable, input
950  .RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
951  .RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
952  .WEBWE (web) // Port B (write port in SDP) Write Enable[7:0], input
953  );
954 
955 endmodule
956 
957 // Both ports with less than 32 bit widths
958 
959 module ram18p_lt32w_lt32r
960 #(
961  parameter integer REGISTERS = 0, // 1 - registered output
962  parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
963  parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
964 `ifdef PRELOAD_BRAMS
965  , parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
966  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
967  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
968  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
969  parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
970  parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
971  parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
972  parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
973  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
974  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
975  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
976  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
977  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
978  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
979  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
980  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
981  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
982  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
983  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
984  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
985  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
986  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
987  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
988  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
989  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
990  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
991  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
992  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
993  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
994  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
995  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
996  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
997  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
998  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
999  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1000  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1001  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1002  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1003  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1004  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1005  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1006  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1007  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1008  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1009  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1010  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1011  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1012  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1013  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1014  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1015  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1016  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1017  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1018  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1019  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1020  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1021  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1022  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1023  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1024  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1025  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1026  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1027  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1028  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1029  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1030  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1031  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1032  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1033  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1034  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1035  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1036  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
1037 
1038 `endif
1039  )
1040  (
1041  input rclk, // clock for read port
1042  input [13-LOG2WIDTH_RD:0] raddr, // read address
1043  input ren, // read port enable
1044  input regen, // output register enable
1045  output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
1046 
1047  input wclk, // clock for read port
1048  input [13-LOG2WIDTH_WR:0] waddr, // write address
1049  input we, // write port enable
1050  input [ 3:0] web, // write byte enable
1051  input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
1052  );
1053  localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
1054  localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
1055  localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
1056  localparam WIDTH_WRP = 1 << (LOG2WIDTH_WR-3);
1057  localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
1058  localparam WIDTH_RDP = 1 << (LOG2WIDTH_RD-3);
1059 
1060  wire [15:0] data_out16;
1061  wire [ 1:0] datap_out2;
1062  assign data_out={datap_out2[WIDTH_RDP-1:0], data_out16[WIDTH_RD-1:0]};
1063 
1064  wire [WIDTH_WR+15:0] data_in_ext = {16'b0,data_in[WIDTH_WR-1:0]};
1065  wire [15:0] data_in16=data_in_ext[15:0];
1066  wire [WIDTH_WRP+1:0] datap_in_ext = {2'b0,data_in[WIDTH_WR+:WIDTH_WRP]};
1067  wire [1:0] datap_in2= datap_in_ext[1:0];
1068 
1069  RAMB18E1
1070  #(
1071  .RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1072  .RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1073  .DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1074  .DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1075  .READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1076  .READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1077  .WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1078  .WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1079  .RAM_MODE ("TDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
1080  .WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1081  .WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1082  .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
1083  .SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
1084  .INIT_FILE ("NONE"), // "NONE" or filename with initialization data
1085  .SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
1086 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
1087 , .INITP_01 (INITP_01)
1088 , .INITP_02 (INITP_02)
1089 , .INITP_03 (INITP_03)
1090 , .INITP_04 (INITP_04)
1091 , .INITP_05 (INITP_05)
1092 , .INITP_06 (INITP_06)
1093 , .INITP_07 (INITP_07)
1094 , .INIT_00 (INIT_00)
1095 , .INIT_01 (INIT_01)
1096 , .INIT_02 (INIT_02)
1097 , .INIT_03 (INIT_03)
1098 , .INIT_04 (INIT_04)
1099 , .INIT_05 (INIT_05)
1100 , .INIT_06 (INIT_06)
1101 , .INIT_07 (INIT_07)
1102 , .INIT_08 (INIT_08)
1103 , .INIT_09 (INIT_09)
1104 , .INIT_0A (INIT_0A)
1105 , .INIT_0B (INIT_0B)
1106 , .INIT_0C (INIT_0C)
1107 , .INIT_0D (INIT_0D)
1108 , .INIT_0E (INIT_0E)
1109 , .INIT_0F (INIT_0F)
1110 , .INIT_10 (INIT_10)
1111 , .INIT_11 (INIT_11)
1112 , .INIT_12 (INIT_12)
1113 , .INIT_13 (INIT_13)
1114 , .INIT_14 (INIT_14)
1115 , .INIT_15 (INIT_15)
1116 , .INIT_16 (INIT_16)
1117 , .INIT_17 (INIT_17)
1118 , .INIT_18 (INIT_18)
1119 , .INIT_19 (INIT_19)
1120 , .INIT_1A (INIT_1A)
1121 , .INIT_1B (INIT_1B)
1122 , .INIT_1C (INIT_1C)
1123 , .INIT_1D (INIT_1D)
1124 , .INIT_1E (INIT_1E)
1125 , .INIT_1F (INIT_1F)
1126 , .INIT_20 (INIT_20)
1127 , .INIT_21 (INIT_21)
1128 , .INIT_22 (INIT_22)
1129 , .INIT_23 (INIT_23)
1130 , .INIT_24 (INIT_24)
1131 , .INIT_25 (INIT_25)
1132 , .INIT_26 (INIT_26)
1133 , .INIT_27 (INIT_27)
1134 , .INIT_28 (INIT_28)
1135 , .INIT_29 (INIT_29)
1136 , .INIT_2A (INIT_2A)
1137 , .INIT_2B (INIT_2B)
1138 , .INIT_2C (INIT_2C)
1139 , .INIT_2D (INIT_2D)
1140 , .INIT_2E (INIT_2E)
1141 , .INIT_2F (INIT_2F)
1142 , .INIT_30 (INIT_30)
1143 , .INIT_31 (INIT_31)
1144 , .INIT_32 (INIT_32)
1145 , .INIT_33 (INIT_33)
1146 , .INIT_34 (INIT_34)
1147 , .INIT_35 (INIT_35)
1148 , .INIT_36 (INIT_36)
1149 , .INIT_37 (INIT_37)
1150 , .INIT_38 (INIT_38)
1151 , .INIT_39 (INIT_39)
1152 , .INIT_3A (INIT_3A)
1153 , .INIT_3B (INIT_3B)
1154 , .INIT_3C (INIT_3C)
1155 , .INIT_3D (INIT_3D)
1156 , .INIT_3E (INIT_3E)
1157 , .INIT_3F (INIT_3F)
1158 
1159 `endif
1160  ) RAMB36E1_i
1161  (
1162  // Port A (Read port in SDP mode):
1163  .DOADO (data_out16), // Port A data/LSB data[15:0], output
1164  .DOPADOP (datap_out2), // Port A parity/LSB parity[1:0], output
1165  .DIADI (16'h0), // Port A data/LSB data[15:0], input
1166  .DIPADIP (2'h0), // Port A parity/LSB parity[1:0], input
1167  .ADDRARDADDR ({raddr,{LOG2WIDTH_RD{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
1168  .CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
1169  .ENARDEN (ren), // Port A (read port in SDP) Enable, input
1170  .REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
1171  .RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
1172  .RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
1173  .WEA (2'b0), // Port A (read port in SDP) Write Enable[3:0], input
1174  // Port B
1175  .DOBDO (), // Port B data/MSB data[31:0], output
1176  .DOPBDOP (), // Port B parity/MSB parity[3:0], output
1177  .DIBDI (data_in16), // Port B data/MSB data[31:0], input
1178  .DIPBDIP (datap_in2), // Port B parity/MSB parity[3:0], input
1179  .ADDRBWRADDR ({waddr,{LOG2WIDTH_WR{1'b1}}}), // Port B (write port in SDP) address [13:0], unused should be high, input
1180  .CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
1181  .ENBWREN (we), // Port B (write port in SDP) Enable, input
1182  .REGCEB (1'b0), // Port B (write port in SDP) register enable, input
1183  .RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
1184  .RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
1185  .WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[3:0], input
1186  );
1187 
1188 endmodule
1189 
1190 // Write port less than 32bits, read port 32 bit widths
1191 module ram18p_lt32w_32r
1192 #(
1193  parameter integer REGISTERS = 0, // 1 - registered output
1194  parameter integer LOG2WIDTH_WR = 4 // WIDTH= 1 << LOG2WIDTH
1195 `ifdef PRELOAD_BRAMS
1196  , parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1197  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1198  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1199  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1200  parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1201  parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1202  parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1203  parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1204  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1205  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1206  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1207  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1208  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1209  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1210  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1211  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1212  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1213  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1214  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1215  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1216  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1217  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1218  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1219  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1220  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1221  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1222  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1223  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1224  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1225  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1226  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1227  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1228  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1229  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1230  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1231  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1232  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1233  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1234  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1235  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1236  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1237  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1238  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1239  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1240  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1241  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1242  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1243  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1244  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1245  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1246  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1247  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1248  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1249  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1250  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1251  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1252  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1253  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1254  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1255  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1256  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1257  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1258  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1259  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1260  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1261  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1262  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1263  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1264  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1265  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1266  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1267  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
1268 
1269 `endif
1270  )
1271  (
1272  input rclk, // clock for read port
1273  input [8:0] raddr, // read address
1274  input ren, // read port enable
1275  input regen, // output register enable
1276  output [35:0] data_out, // data out
1277 
1278  input wclk, // clock for read port
1279  input [13-LOG2WIDTH_WR:0] waddr, // write address
1280  input we, // write port enable
1281  input [ 3:0] web, // write byte enable
1282  input [(9 << (LOG2WIDTH_WR-3))-1:0] data_in // data out
1283  );
1284 
1285  localparam PWIDTH_WR = (LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR);
1286  localparam PWIDTH_RD = 36;
1287  localparam WIDTH_WR = 1 << LOG2WIDTH_WR;
1288  localparam WIDTH_WRP = 1 << (LOG2WIDTH_WR-3);
1289 
1290  wire [WIDTH_WR+15:0] data_in_ext = {16'b0,data_in[WIDTH_WR-1:0]};
1291  wire [15:0] data_in16=data_in_ext[15:0];
1292 
1293  wire [WIDTH_WRP+1:0] datap_in_ext = {2'b0,data_in[WIDTH_WR+:WIDTH_WRP]};
1294  wire [1:0] datap_in2= datap_in_ext[1:0];
1295 
1296  RAMB18E1
1297  #(
1298  .RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1299  .RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1300  .DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1301  .DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1302  .READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1303  .READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1304  .WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1305  .WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1306  .RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
1307  .WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1308  .WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1309  .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
1310  .SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
1311  .INIT_FILE ("NONE"), // "NONE" or filename with initialization data
1312  .SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
1313 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
1314 , .INITP_01 (INITP_01)
1315 , .INITP_02 (INITP_02)
1316 , .INITP_03 (INITP_03)
1317 , .INITP_04 (INITP_04)
1318 , .INITP_05 (INITP_05)
1319 , .INITP_06 (INITP_06)
1320 , .INITP_07 (INITP_07)
1321 , .INIT_00 (INIT_00)
1322 , .INIT_01 (INIT_01)
1323 , .INIT_02 (INIT_02)
1324 , .INIT_03 (INIT_03)
1325 , .INIT_04 (INIT_04)
1326 , .INIT_05 (INIT_05)
1327 , .INIT_06 (INIT_06)
1328 , .INIT_07 (INIT_07)
1329 , .INIT_08 (INIT_08)
1330 , .INIT_09 (INIT_09)
1331 , .INIT_0A (INIT_0A)
1332 , .INIT_0B (INIT_0B)
1333 , .INIT_0C (INIT_0C)
1334 , .INIT_0D (INIT_0D)
1335 , .INIT_0E (INIT_0E)
1336 , .INIT_0F (INIT_0F)
1337 , .INIT_10 (INIT_10)
1338 , .INIT_11 (INIT_11)
1339 , .INIT_12 (INIT_12)
1340 , .INIT_13 (INIT_13)
1341 , .INIT_14 (INIT_14)
1342 , .INIT_15 (INIT_15)
1343 , .INIT_16 (INIT_16)
1344 , .INIT_17 (INIT_17)
1345 , .INIT_18 (INIT_18)
1346 , .INIT_19 (INIT_19)
1347 , .INIT_1A (INIT_1A)
1348 , .INIT_1B (INIT_1B)
1349 , .INIT_1C (INIT_1C)
1350 , .INIT_1D (INIT_1D)
1351 , .INIT_1E (INIT_1E)
1352 , .INIT_1F (INIT_1F)
1353 , .INIT_20 (INIT_20)
1354 , .INIT_21 (INIT_21)
1355 , .INIT_22 (INIT_22)
1356 , .INIT_23 (INIT_23)
1357 , .INIT_24 (INIT_24)
1358 , .INIT_25 (INIT_25)
1359 , .INIT_26 (INIT_26)
1360 , .INIT_27 (INIT_27)
1361 , .INIT_28 (INIT_28)
1362 , .INIT_29 (INIT_29)
1363 , .INIT_2A (INIT_2A)
1364 , .INIT_2B (INIT_2B)
1365 , .INIT_2C (INIT_2C)
1366 , .INIT_2D (INIT_2D)
1367 , .INIT_2E (INIT_2E)
1368 , .INIT_2F (INIT_2F)
1369 , .INIT_30 (INIT_30)
1370 , .INIT_31 (INIT_31)
1371 , .INIT_32 (INIT_32)
1372 , .INIT_33 (INIT_33)
1373 , .INIT_34 (INIT_34)
1374 , .INIT_35 (INIT_35)
1375 , .INIT_36 (INIT_36)
1376 , .INIT_37 (INIT_37)
1377 , .INIT_38 (INIT_38)
1378 , .INIT_39 (INIT_39)
1379 , .INIT_3A (INIT_3A)
1380 , .INIT_3B (INIT_3B)
1381 , .INIT_3C (INIT_3C)
1382 , .INIT_3D (INIT_3D)
1383 , .INIT_3E (INIT_3E)
1384 , .INIT_3F (INIT_3F)
1385 
1386 `endif
1387  ) RAMB36E1_i
1388  (
1389  // Port A (Read port in SDP mode):
1390  .DOADO (data_out[15:0]), // Port A data/LSB data[15:0], output
1391  .DOPADOP (data_out[17:16]),// Port A parity/LSB parity[3:0], output
1392  .DIADI (16'h0), // Port A data/LSB data[31:0], input
1393  .DIPADIP (2'h0), // Port A parity/LSB parity[3:0], input
1394  .ADDRARDADDR ({raddr[8:0],5'b11111}), // Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
1395  .CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
1396  .ENARDEN (ren), // Port A (read port in SDP) Enable, input
1397  .REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
1398  .RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
1399  .RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
1400  .WEA (2'b0), // Port A (read port in SDP) Write Enable[3:0], input
1401  // Port B
1402  .DOBDO (data_out[33:18]),// Port B data/MSB data[31:0], output
1403  .DOPBDOP (data_out[35:34]),// Port B parity/MSB parity[3:0], output
1404  .DIBDI (data_in16), // Port B data/MSB data[31:0], input
1405  .DIPBDIP (datap_in2), // Port B parity/MSB parity[3:0], input
1406  .ADDRBWRADDR ({waddr,{LOG2WIDTH_WR{1'b1}}}), // Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
1407  .CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
1408  .ENBWREN (we), // Port B (write port in SDP) Enable, input
1409  .REGCEB (1'b0), // Port B (write port in SDP) register enable, input
1410  .RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
1411  .RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
1412  .WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[7:0], input
1413  );
1414 
1415 endmodule
1416 
1417 // Write port 64 bita, read port - less than 64 bits
1418 module ram18p_32w_lt32r
1419 #(
1420  parameter integer REGISTERS = 0, // 1 - registered output
1421 // parameter integer LOG2WIDTH_WR = 4, // WIDTH= 1 << LOG2WIDTH
1422  parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
1423 `ifdef PRELOAD_BRAMS
1424  , parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1425  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1426  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1427  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1428  parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1429  parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1430  parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1431  parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1432  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1433  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1434  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1435  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1436  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1437  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1438  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1439  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1440  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1441  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1442  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1443  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1444  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1445  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1446  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1447  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1448  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1449  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1450  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1451  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1452  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1453  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1454  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1455  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1456  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1457  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1458  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1459  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1460  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1461  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1462  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1463  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1464  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1465  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1466  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1467  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1468  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1469  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1470  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1471  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1472  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1473  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1474  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1475  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1476  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1477  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1478  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1479  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1480  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1481  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1482  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1483  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1484  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1485  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1486  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1487  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1488  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1489  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1490  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1491  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1492  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1493  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1494  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000,
1495  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000
1496 
1497 `endif
1498  )
1499  (
1500  input rclk, // clock for read port
1501  input [13-LOG2WIDTH_RD:0] raddr, // read address
1502  input ren, // read port enable
1503  input regen, // output register enable
1504  output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out, // data out
1505 
1506  input wclk, // clock for read port
1507  input [8:0] waddr, // write address
1508  input we, // write port enable
1509  input [ 3:0] web, // write byte enable
1510  input [35:0] data_in // data out
1511  );
1512  localparam PWIDTH_WR = 36;
1513  localparam PWIDTH_RD = (LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD);
1514  localparam WIDTH_RD = 1 << LOG2WIDTH_RD;
1515  localparam WIDTH_RDP = 1 << (LOG2WIDTH_RD-3);
1516  wire [15:0] data_out16;
1517  wire [ 1:0] datap_out2;
1518  assign data_out={datap_out2[WIDTH_RDP-1:0], data_out16[WIDTH_RD-1:0]};
1519  RAMB18E1
1520  #(
1521  .RSTREG_PRIORITY_A ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1522  .RSTREG_PRIORITY_B ("RSTREG"), // Valid: "RSTREG" or "REGCE"
1523  .DOA_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1524  .DOB_REG (REGISTERS), // Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 18)
1525  .READ_WIDTH_A (PWIDTH_RD), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1526  .READ_WIDTH_B (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1527  .WRITE_WIDTH_A (0), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1528  .WRITE_WIDTH_B (PWIDTH_WR), // Valid: 0,1,2,4,9,18 and in SDP mode - 36 (should be 0 if port is not used)
1529  .RAM_MODE ("SDP"), // Valid "TDP" (true dual-port) and "SDP" - simple dual-port
1530  .WRITE_MODE_A ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1531  .WRITE_MODE_B ("WRITE_FIRST"), // Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
1532  .RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
1533  .SIM_COLLISION_CHECK ("ALL"), // Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
1534  .INIT_FILE ("NONE"), // "NONE" or filename with initialization data
1535  .SIM_DEVICE ("7SERIES") // Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
1536 `ifdef PRELOAD_BRAMS, .INITP_00 (INITP_00)
1537 , .INITP_01 (INITP_01)
1538 , .INITP_02 (INITP_02)
1539 , .INITP_03 (INITP_03)
1540 , .INITP_04 (INITP_04)
1541 , .INITP_05 (INITP_05)
1542 , .INITP_06 (INITP_06)
1543 , .INITP_07 (INITP_07)
1544 , .INIT_00 (INIT_00)
1545 , .INIT_01 (INIT_01)
1546 , .INIT_02 (INIT_02)
1547 , .INIT_03 (INIT_03)
1548 , .INIT_04 (INIT_04)
1549 , .INIT_05 (INIT_05)
1550 , .INIT_06 (INIT_06)
1551 , .INIT_07 (INIT_07)
1552 , .INIT_08 (INIT_08)
1553 , .INIT_09 (INIT_09)
1554 , .INIT_0A (INIT_0A)
1555 , .INIT_0B (INIT_0B)
1556 , .INIT_0C (INIT_0C)
1557 , .INIT_0D (INIT_0D)
1558 , .INIT_0E (INIT_0E)
1559 , .INIT_0F (INIT_0F)
1560 , .INIT_10 (INIT_10)
1561 , .INIT_11 (INIT_11)
1562 , .INIT_12 (INIT_12)
1563 , .INIT_13 (INIT_13)
1564 , .INIT_14 (INIT_14)
1565 , .INIT_15 (INIT_15)
1566 , .INIT_16 (INIT_16)
1567 , .INIT_17 (INIT_17)
1568 , .INIT_18 (INIT_18)
1569 , .INIT_19 (INIT_19)
1570 , .INIT_1A (INIT_1A)
1571 , .INIT_1B (INIT_1B)
1572 , .INIT_1C (INIT_1C)
1573 , .INIT_1D (INIT_1D)
1574 , .INIT_1E (INIT_1E)
1575 , .INIT_1F (INIT_1F)
1576 , .INIT_20 (INIT_20)
1577 , .INIT_21 (INIT_21)
1578 , .INIT_22 (INIT_22)
1579 , .INIT_23 (INIT_23)
1580 , .INIT_24 (INIT_24)
1581 , .INIT_25 (INIT_25)
1582 , .INIT_26 (INIT_26)
1583 , .INIT_27 (INIT_27)
1584 , .INIT_28 (INIT_28)
1585 , .INIT_29 (INIT_29)
1586 , .INIT_2A (INIT_2A)
1587 , .INIT_2B (INIT_2B)
1588 , .INIT_2C (INIT_2C)
1589 , .INIT_2D (INIT_2D)
1590 , .INIT_2E (INIT_2E)
1591 , .INIT_2F (INIT_2F)
1592 , .INIT_30 (INIT_30)
1593 , .INIT_31 (INIT_31)
1594 , .INIT_32 (INIT_32)
1595 , .INIT_33 (INIT_33)
1596 , .INIT_34 (INIT_34)
1597 , .INIT_35 (INIT_35)
1598 , .INIT_36 (INIT_36)
1599 , .INIT_37 (INIT_37)
1600 , .INIT_38 (INIT_38)
1601 , .INIT_39 (INIT_39)
1602 , .INIT_3A (INIT_3A)
1603 , .INIT_3B (INIT_3B)
1604 , .INIT_3C (INIT_3C)
1605 , .INIT_3D (INIT_3D)
1606 , .INIT_3E (INIT_3E)
1607 , .INIT_3F (INIT_3F)
1608 
1609 `endif
1610  ) RAMB36E1_i
1611  (
1612  // Port A (Read port in SDP mode):
1613  .DOADO (data_out16), // Port A data/LSB data[15:0], output
1614  .DOPADOP (datap_out2), // Port A parity/LSB parity[1:0], output
1615  .DIADI (data_in[15:0]), // Port A data/LSB data[15:0], input
1616  .DIPADIP (data_in[17:16]), // Port A parity/LSB parity[1:0], input
1617  .ADDRARDADDR ({raddr,{LOG2WIDTH_RD{1'b1}}}), // Port A (read port in SDP) address [13:0], unused should be high, input
1618  .CLKARDCLK (rclk), // Port A (read port in SDP) clock, input
1619  .ENARDEN (ren), // Port A (read port in SDP) Enable, input
1620  .REGCEAREGCE (regen), // Port A (read port in SDP) register enable, input
1621  .RSTRAMARSTRAM (1'b0), // Port A (read port in SDP) set/reset, input
1622  .RSTREGARSTREG (1'b0), // Port A (read port in SDP) register set/reset, input
1623  .WEA (2'b0), // Port A (read port in SDP) Write Enable[1:0], input
1624  // Port B
1625  .DOBDO (), // Port B data/MSB data[15:0], output
1626  .DOPBDOP (), // Port B parity/MSB parity[1:0], output
1627  .DIBDI (data_in[33:18]), // Port B data/MSB data[15:0], input
1628  .DIPBDIP (data_in[35:34]), // Port B parity/MSB parity[1:0], input
1629  .ADDRBWRADDR({waddr[8:0],5'b11111}), // Port B (write port in SDP) address [13:0], unused should be high, input
1630  .CLKBWRCLK (wclk), // Port B (write port in SDP) clock, input
1631  .ENBWREN (we), // Port B (write port in SDP) Enable, input
1632  .REGCEB (1'b0), // Port B (write port in SDP) register enable, input
1633  .RSTRAMB (1'b0), // Port B (write port in SDP) set/reset, input
1634  .RSTREGB (1'b0), // Port B (write port in SDP) register set/reset, input
1635  .WEBWE (web[3:0]) // Port B (write port in SDP) Write Enable[7:0], input
1636  );
1637 
1638 endmodule
1639 
1640 module ram18p_dummy
1641 #(
1642  parameter integer LOG2WIDTH_RD = 4 // WIDTH= 1 << LOG2WIDTH
1643  )
1644  (
1645  output [(9 << (LOG2WIDTH_RD-3))-1:0] data_out // data out
1646  );
1647  assign data_out=0;
1648 endmodule
1649 
ram18p_32w_lt32r.11738REGISTERS
integer 11738REGISTERS0
Definition: ram18p_var_w_var_r.v:447
ram18p_32w_32r.11691PWIDTH_WR
11691PWIDTH_WR36
Definition: ram18p_var_w_var_r.v:215
ram18p_lt32w_lt32r.11712data_out16
11712data_out16wire[15:0]
Definition: ram18p_var_w_var_r.v:300
ram18p_var_w_var_r.11666REGISTERS
integer 11666REGISTERS0
Definition: ram18p_var_w_var_r.v:83
ram18p_lt32w_32r.11718REGISTERS
integer 11718REGISTERS0
Definition: ram18p_var_w_var_r.v:362
ram18p_32w_32r.11685data_out
[35:0] 11685data_out
Definition: ram18p_var_w_var_r.v:207
ram18p_lt32w_lt32r.11699regen
11699regen
Definition: ram18p_var_w_var_r.v:284
ram18p_lt32w_lt32r.11707PWIDTH_RD
11707PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
Definition: ram18p_var_w_var_r.v:294
ram18p_var_w_var_r.11675wclk
11675wclk
Definition: ram18p_var_w_var_r.v:100
ram18p_lt32w_lt32r.11702waddr
[13-LOG2WIDTH_WR:0] 11702waddr
Definition: ram18p_var_w_var_r.v:288
ram18p_lt32w_lt32r.11693REGISTERS
integer 11693REGISTERS0
Definition: ram18p_var_w_var_r.v:272
ram18p_lt32w_lt32r.11698ren
11698ren
Definition: ram18p_var_w_var_r.v:283
ram18p_32w_lt32r.11752WIDTH_RD
11752WIDTH_RD1 << LOG2WIDTH_RD
Definition: ram18p_var_w_var_r.v:470
ram18p_lt32w_lt32r.11717datap_in2
11717datap_in2wire[1:0]
Definition: ram18p_var_w_var_r.v:307
ram18p_32w_lt32r.11750PWIDTH_WR
11750PWIDTH_WR36
Definition: ram18p_var_w_var_r.v:468
ram18p_lt32w_32r.11720rclk
11720rclk
Definition: ram18p_var_w_var_r.v:370
ram18p_lt32w_lt32r.11697raddr
[13-LOG2WIDTH_RD:0] 11697raddr
Definition: ram18p_var_w_var_r.v:282
ram18p_lt32w_32r.11726waddr
[13-LOG2WIDTH_WR:0] 11726waddr
Definition: ram18p_var_w_var_r.v:377
ram18p_lt32w_32r.11722ren
11722ren
Definition: ram18p_var_w_var_r.v:372
ram18p_32w_lt32r.11754data_out16
11754data_out16wire[15:0]
Definition: ram18p_var_w_var_r.v:472
ram18p_32w_32r.11681rclk
11681rclk
Definition: ram18p_var_w_var_r.v:203
ram18p_lt32w_32r.11731PWIDTH_RD
11731PWIDTH_RD36
Definition: ram18p_var_w_var_r.v:384
ram18p_32w_32r.11683ren
11683ren
Definition: ram18p_var_w_var_r.v:205
ram18p_var_w_var_r.ram18p_32w_lt32r
ram_i ram18p_32w_lt32r[generate]
Definition: ram18p_var_w_var_r.v:132
ram18p_var_w_var_r.11673regen
11673regen
Definition: ram18p_var_w_var_r.v:97
ram18p_dummy.11756LOG2WIDTH_RD
integer 11756LOG2WIDTH_RD4
Definition: ram18p_var_w_var_r.v:527
ram18p_var_w_var_r.ram18p_32w_32r
ram_i ram18p_32w_32r[generate]
Definition: ram18p_var_w_var_r.v:114
ram18p_32w_lt32r.RAMB18E1
RAMB36E1_i RAMB18E1
Definition: ram18p_var_w_var_r.v:475
ram18p_32w_32r.11692PWIDTH_RD
11692PWIDTH_RD36
Definition: ram18p_var_w_var_r.v:216
ram18p_var_w_var_r.11679data_in
[9 << LOG2WIDTH_WR-3-1:0] 11679data_in
Definition: ram18p_var_w_var_r.v:104
ram18p_lt32w_32r.11733WIDTH_WRP
11733WIDTH_WRP1 << (LOG2WIDTH_WR-3
Definition: ram18p_var_w_var_r.v:386
ram18p_lt32w_lt32r.11716datap_in_ext
11716datap_in_extwire[WIDTH_WRP+1:0]
Definition: ram18p_var_w_var_r.v:306
ram18p_32w_lt32r.11745wclk
11745wclk
Definition: ram18p_var_w_var_r.v:462
ram18p_lt32w_32r.11728web
[ 3:0] 11728web
Definition: ram18p_var_w_var_r.v:379
ram18p_32w_32r.11688we
11688we
Definition: ram18p_var_w_var_r.v:211
ram18p_32w_lt32r.11742ren
11742ren
Definition: ram18p_var_w_var_r.v:458
ram18p_32w_32r.11686wclk
11686wclk
Definition: ram18p_var_w_var_r.v:209
ram18p_lt32w_32r.11732WIDTH_WR
11732WIDTH_WR1 << LOG2WIDTH_WR
Definition: ram18p_var_w_var_r.v:385
ram18p_var_w_var_r.11678web
[ 3:0] 11678web
Definition: ram18p_var_w_var_r.v:103
ram18p_32w_lt32r.11751PWIDTH_RD
11751PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
Definition: ram18p_var_w_var_r.v:469
ram18p_32w_32r.11689web
[ 3:0] 11689web
Definition: ram18p_var_w_var_r.v:212
ram18p_32w_lt32r.11747we
11747we
Definition: ram18p_var_w_var_r.v:464
ram18p_lt32w_32r.11730PWIDTH_WR
11730PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR
Definition: ram18p_var_w_var_r.v:383
ram18p_lt32w_32r.11725wclk
11725wclk
Definition: ram18p_var_w_var_r.v:376
ram18p_32w_lt32r.11743regen
11743regen
Definition: ram18p_var_w_var_r.v:459
ram18p_32w_lt32r
Definition: ram18p_var_w_var_r.v:445
ram18p_lt32w_lt32r.RAMB18E1
RAMB36E1_i RAMB18E1
Definition: ram18p_var_w_var_r.v:309
ram18p_lt32w_lt32r.11706PWIDTH_WR
11706PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR
Definition: ram18p_var_w_var_r.v:293
ram18p_lt32w_32r.11724data_out
[35:0] 11724data_out
Definition: ram18p_var_w_var_r.v:374
ram18p_32w_32r.11684regen
11684regen
Definition: ram18p_var_w_var_r.v:206
ram18p_var_w_var_r.ram18p_dummy
ram18p_dummy_i ram18p_dummy[generate]
Definition: ram18p_var_w_var_r.v:108
ram18p_32w_lt32r.11755datap_out2
11755datap_out2wire[1:0]
Definition: ram18p_var_w_var_r.v:473
ram18p_lt32w_32r.11721raddr
[8:0] 11721raddr
Definition: ram18p_var_w_var_r.v:371
ram18p_32w_lt32r.11744data_out
[9 << LOG2WIDTH_RD-3-1:0] 11744data_out
Definition: ram18p_var_w_var_r.v:460
ram18p_lt32w_lt32r.11709WIDTH_WRP
11709WIDTH_WRP1 << (LOG2WIDTH_WR-3
Definition: ram18p_var_w_var_r.v:296
ram18p_lt32w_lt32r.11701wclk
11701wclk
Definition: ram18p_var_w_var_r.v:287
ram18p_lt32w_32r.11736datap_in_ext
11736datap_in_extwire[WIDTH_WRP+1:0]
Definition: ram18p_var_w_var_r.v:391
ram18p_32w_lt32r.11740rclk
11740rclk
Definition: ram18p_var_w_var_r.v:456
ram18p_var_w_var_r
Definition: ram18p_var_w_var_r.v:81
ram18p_lt32w_32r.RAMB18E1
RAMB36E1_i RAMB18E1
Definition: ram18p_var_w_var_r.v:394
ram18p_var_w_var_r.ram18p_lt32w_lt32r
ram_i ram18p_lt32w_lt32r[generate]
Definition: ram18p_var_w_var_r.v:170
ram18p_lt32w_lt32r.11700data_out
[9 << LOG2WIDTH_RD-3-1:0] 11700data_out
Definition: ram18p_var_w_var_r.v:285
ram18p_var_w_var_r.11677we
11677we
Definition: ram18p_var_w_var_r.v:102
ram18p_var_w_var_r.11668LOG2WIDTH_RD
integer 11668LOG2WIDTH_RD5
Definition: ram18p_var_w_var_r.v:85
ram18p_32w_32r.11687waddr
[ 8:0] 11687waddr
Definition: ram18p_var_w_var_r.v:210
ram18p_var_w_var_r.11667LOG2WIDTH_WR
integer 11667LOG2WIDTH_WR5
Definition: ram18p_var_w_var_r.v:84
ram18p_var_w_var_r.11674data_out
[9 << LOG2WIDTH_RD-3-1:0] 11674data_out
Definition: ram18p_var_w_var_r.v:98
ram18p_var_w_var_r.11672ren
11672ren
Definition: ram18p_var_w_var_r.v:96
ram18p_32w_32r.11682raddr
[8:0] 11682raddr
Definition: ram18p_var_w_var_r.v:204
ram18p_lt32w_lt32r.11714data_in_ext
11714data_in_extwire[WIDTH_WR+15:0]
Definition: ram18p_var_w_var_r.v:304
ram18p_lt32w_32r.11723regen
11723regen
Definition: ram18p_var_w_var_r.v:373
ram18p_32w_32r.RAMB18E1
RAMB36E1_i RAMB18E1
Definition: ram18p_var_w_var_r.v:218
ram18p_lt32w_lt32r.11703we
11703we
Definition: ram18p_var_w_var_r.v:289
ram18p_lt32w_32r
Definition: ram18p_var_w_var_r.v:360
ram18p_32w_32r.11690data_in
[35:0] 11690data_in
Definition: ram18p_var_w_var_r.v:213
ram18p_lt32w_lt32r.11696rclk
11696rclk
Definition: ram18p_var_w_var_r.v:281
ram18p_32w_lt32r.11748web
[ 3:0] 11748web
Definition: ram18p_var_w_var_r.v:465
ram18p_lt32w_lt32r
Definition: ram18p_var_w_var_r.v:270
ram18p_32w_lt32r.11746waddr
[8:0] 11746waddr
Definition: ram18p_var_w_var_r.v:463
ram18p_var_w_var_r.ram18p_lt32w_32r
ram_i ram18p_lt32w_32r[generate]
Definition: ram18p_var_w_var_r.v:151
ram18p_lt32w_32r.11737datap_in2
11737datap_in2wire[1:0]
Definition: ram18p_var_w_var_r.v:392
ram18p_lt32w_32r.11735data_in16
11735data_in16wire[15:0]
Definition: ram18p_var_w_var_r.v:389
ram18p_lt32w_32r.11734data_in_ext
11734data_in_extwire[WIDTH_WR+15:0]
Definition: ram18p_var_w_var_r.v:388
ram18p_lt32w_lt32r.11708WIDTH_WR
11708WIDTH_WR1 << LOG2WIDTH_WR
Definition: ram18p_var_w_var_r.v:295
ram18p_lt32w_lt32r.11710WIDTH_RD
11710WIDTH_RD1 << LOG2WIDTH_RD
Definition: ram18p_var_w_var_r.v:297
ram18p_lt32w_lt32r.11715data_in16
11715data_in16wire[15:0]
Definition: ram18p_var_w_var_r.v:305
ram18p_lt32w_lt32r.11713datap_out2
11713datap_out2wire[1:0]
Definition: ram18p_var_w_var_r.v:301
ram18p_lt32w_lt32r.11704web
[ 3:0] 11704web
Definition: ram18p_var_w_var_r.v:290
ram18p_var_w_var_r.11671raddr
[13-LOG2WIDTH_RD:0] 11671raddr
Definition: ram18p_var_w_var_r.v:95
ram18p_lt32w_lt32r.11705data_in
[9 << LOG2WIDTH_WR-3-1:0] 11705data_in
Definition: ram18p_var_w_var_r.v:291
ram18p_32w_lt32r.11753WIDTH_RDP
11753WIDTH_RDP1 << (LOG2WIDTH_RD-3
Definition: ram18p_var_w_var_r.v:471
ram18p_dummy
Definition: ram18p_var_w_var_r.v:525
ram18p_lt32w_32r.11727we
11727we
Definition: ram18p_var_w_var_r.v:378
ram18p_lt32w_lt32r.11694LOG2WIDTH_WR
integer 11694LOG2WIDTH_WR4
Definition: ram18p_var_w_var_r.v:273
ram18p_lt32w_32r.11729data_in
[9 << LOG2WIDTH_WR-3-1:0] 11729data_in
Definition: ram18p_var_w_var_r.v:380
ram18p_32w_lt32r.11749data_in
[35:0] 11749data_in
Definition: ram18p_var_w_var_r.v:466
ram18p_var_w_var_r.11670rclk
11670rclk
Definition: ram18p_var_w_var_r.v:93
ram18p_var_w_var_r.11676waddr
[13-LOG2WIDTH_WR:0] 11676waddr
Definition: ram18p_var_w_var_r.v:101
ram18p_32w_lt32r.11741raddr
[13-LOG2WIDTH_RD:0] 11741raddr
Definition: ram18p_var_w_var_r.v:457
ram18p_lt32w_lt32r.11711WIDTH_RDP
11711WIDTH_RDP1 << (LOG2WIDTH_RD-3
Definition: ram18p_var_w_var_r.v:298
ram18p_dummy.11757data_out
[9 << LOG2WIDTH_RD-3-1:0] 11757data_out
Definition: ram18p_var_w_var_r.v:530