x393
1.0
FPGAcodeforElphelNC393camera
quantizer393.v
Go to the documentation of this file.
1
38
77
// This file may be used to define same pre-processor macros to be included into each parsed file
78
`ifndef
SYSTEM_DEFINES
79
`define
SYSTEM_DEFINES
80
// TODO: Later compare instantiate/infer
81
`define
INSTANTIATE_DSP48E1
82
`define
DEBUG_DCT1D// undefine after debugging is over
// `define USE_OLD_DCT
83
84
// Parameters from x393_sata project
85
`define
USE_DRP
86
`define
ALIGN_CLOCKS
87
// `define STRAIGHT_XCLK
88
`define
USE_DATASCOPE
89
// `define DATASCOPE_INCOMING_RAW
90
`define
PRELOAD_BRAMS
91
// `define AHCI_SATA 1
92
// `define DEBUG_ELASTIC
93
// End of parameters from x393_sata project
94
95
`define
PRELOAD_BRAMS
96
`define
DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
97
`define
HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// `define USE_OLD_XDCT393
98
// `define USE_PCLK2X
99
// `define USE_XCLK2X
100
`define
REVERSE_LANES 1
`define
DEBUG_RING 1
`define
USE_HARD_CURPARAMS// Adjustment of actual hardware may break simulation
// `define DEBUG_SENS_MEM_PAGES 1
101
// `define MCLK_VCO_MULT 16
102
// DDR3 memory speed grade and density
103
`define
sg25 1
// `define sg15E 1
104
// `define sg187E 1
105
`define
den4096Mb 1
106
`define
MCLK_VCO_MULT 16
// `define MCLK_VCO_MULT 18
107
// `define MCLK_VCO_MULT 20
108
109
`define
MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
110
`ifdef
IVERILOG
111
`define
SIMULATION
112
`define
OPEN_SOURCE_ONLY
113
`endif
114
115
`ifdef
COCOTB
116
`define
SIMULATION
117
`define
OPEN_SOURCE_ONLY
118
`endif
119
120
`ifdef
CVC
121
`define
SIMULATION
122
`define
OPEN_SOURCE_ONLY
123
`endif
// CVC
124
125
// will not use simultaneous reset in shift registers, just and input data with ~rst
126
`define
SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch
127
`undef
INFER_LATCHES
128
// define when using CDC - it does not support them
129
`undef
IGNORE_ATTR
130
//`define MEMBRIDGE_DEBUG_READ 1
131
`define
use200Mhz 1
`define
USE_CMD_ENCOD_TILED_32_RD 1
// chn 0 is read from memory and write to memory
132
`define
def_enable_mem_chn0
133
`define
def_read_mem_chn0
134
`define
def_write_mem_chn0
135
`undef
def_scanline_chn0
136
`undef
def_tiled_chn0
137
138
// chn 1 is scanline r+w
139
`define
def_enable_mem_chn1
140
`define
def_read_mem_chn1
141
`define
def_write_mem_chn1
142
`define
def_scanline_chn1
143
`undef
def_tiled_chn1
144
145
// chn 2 is tiled r+w
146
`define
def_enable_mem_chn2
147
`define
def_read_mem_chn2
148
`define
def_write_mem_chn2
149
`undef
def_scanline_chn2
150
`define
def_tiled_chn2
151
152
// chn 3 is scanline r+w (reuse later)
153
`define
def_enable_mem_chn3
154
`define
def_read_mem_chn3
155
`define
def_write_mem_chn3
156
`define
def_scanline_chn3
157
`undef
def_tiled_chn3
158
159
// chn 4 is tiled r+w (reuse later)
160
`define
def_enable_mem_chn4
161
`define
def_read_mem_chn4
162
`define
def_write_mem_chn4
163
`undef
def_scanline_chn4
164
`define
def_tiled_chn4
165
166
// chn 5 is disabled
167
`undef
def_enable_mem_chn5
168
169
// chn 6 is disabled
170
`undef
def_enable_mem_chn6
171
172
// chn 7 is disabled
173
`undef
def_enable_mem_chn7
174
175
// chn 8 is scanline w (sensor channel 0)
176
`define
def_enable_mem_chn8
177
`undef
def_read_mem_chn8
178
`define
def_write_mem_chn8
179
`define
def_scanline_chn8
180
`undef
def_tiled_chn8
181
182
// chn 9 is scanline w (sensor channel 1)
183
`define
def_enable_mem_chn9
184
`undef
def_read_mem_chn9
185
`define
def_write_mem_chn9
186
`define
def_scanline_chn9
187
`undef
def_tiled_chn9
188
189
// chn 10 is scanline w (sensor channel 2)
190
`define
def_enable_mem_chn10
191
`undef
def_read_mem_chn10
192
`define
def_write_mem_chn10
193
`define
def_scanline_chn10
194
`undef
def_tiled_chn10
195
196
// chn 11 is scanline w (sensor channel 3)
197
`define
def_enable_mem_chn11
198
`undef
def_read_mem_chn11
199
`define
def_write_mem_chn11
200
`define
def_scanline_chn11
201
`undef
def_tiled_chn11
202
203
// chn 12 is tiled read (compressor channel 0)
204
`define
def_enable_mem_chn12
205
`define
def_read_mem_chn12
206
`undef
def_write_mem_chn12
207
`undef
def_scanline_chn12
208
`define
def_tiled_chn12
209
210
// chn 12 is tiled read (compressor channel 1)
211
`define
def_enable_mem_chn13
212
`define
def_read_mem_chn13
213
`undef
def_write_mem_chn13
214
`undef
def_scanline_chn13
215
`define
def_tiled_chn13
216
217
// chn 12 is tiled read (compressor channel 2)
218
`define
def_enable_mem_chn14
219
`define
def_read_mem_chn14
220
`undef
def_write_mem_chn14
221
`undef
def_scanline_chn14
222
`define
def_tiled_chn14
223
224
// chn 12 is tiled read (compressor channel 3)
225
`define
def_enable_mem_chn15
226
`define
def_read_mem_chn15
227
`undef
def_write_mem_chn15
228
`undef
def_scanline_chn15
229
`define
def_tiled_chn15
230
`endif
231
232
`timescale 1ns/1ps
233
234
// will add extracted DC (8 bits) to data from DCT here that will make data 12 bits (signed) long.
235
// It will be possible to make a sequintial multiplier for DC - but I'll skip this now.
236
module
quantizer393
(
237
input
clk
,
// pixel clock, posedge
238
input
en
,
// enable (0 resets counter)
239
input
mclk
,
// system clock to write tables
240
input
tser_qe
,
// enable write to a quantization table
241
input
tser_ce
,
// enable write to a coring table
242
input
tser_a_not_d
,
// address/not data distributed to submodules
243
input
[
7
:
0
]
tser_d
,
// byte-wide serialized tables address/data to submodules
244
input
ctypei
,
// component type input (Y/C)
245
input
[
8
:
0
]
dci
,
// [7:0] - average value in a block - subtracted before DCT. now normal signed number
246
input
first_stb
,
//this is first stb pulse in a frame
247
input
stb
,
// strobe that writes ctypei, dci
248
input
[
2
:
0
]
tsi
,
// table (quality) select [2:0]
249
input
pre_start
,
// marks first input pixel (one before)
250
input
first_in
,
// first block in (valid @ start)
251
output
reg
first_out
,
// valid @ ds
252
input
[
12
:
0
]
di
,
// [11:0] pixel data in (signed)
253
output
reg
[
12
:
0
]
do
,
// [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
254
output
dv
,
// data out valid
255
output
ds
,
// data out strobe (one ahead of the start of dv)
256
output
reg
[
15
:
0
]
dc_tdo
,
//[15:0], MSB aligned coefficient for the DC component (used in focus module)
257
input
dcc_en
,
// enable dcc (sync to beginning of a new frame)
258
input
[
2
:
0
]
hfc_sel
,
// hight frequency components select [2:0] (includes components with both numbers >=hfc_sel
259
// hfc_sel == 3'h7 - now high frequency output - just 3 words - brightness and 2 color diffs
260
input
color_first
,
// first MCU in a frame
261
input
[
2
:
0
]
coring_num
,
// coring table pair number (0..7)
262
output
reg
dcc_vld
,
// single cycle when dcc_data is valid
263
output
[
15
:
0
]
dcc_data
,
// [15:0] dc component data out (for reading by software)
264
input
[
7
:
0
]
n000
,
// input [7:0] number of zero pixels (255 if 256) - to be multiplexed with dcc
265
input
[
7
:
0
]
n255
);
// input [7:0] number of 0xff pixels (255 if 256) - to be multiplexed with dcc
266
267
268
wire
[
3
:
0
]
tdco
;
// coring table output
269
reg
[
3
:
0
]
tbac
;
// coring memory table number (LSB - color)
270
reg
coring_range
;
// input <16, use coring LUT
271
wire
[
15
:
0
]
tdo
;
272
reg
[
9
:
0
]
tba
;
// table output (use) address
273
wire
[
15
:
0
]
zigzag_q
;
274
reg
wpage
;
275
reg
rpage
;
276
wire
[
5
:
0
]
zwa
;
277
reg
[
5
:
0
]
zra
;
278
reg
[
12
:
0
]
qdo
;
279
reg
[
12
:
0
]
qdo0
;
280
reg
zwe
;
281
reg
[
12
:
0
]
d1
;
282
reg
[
12
:
0
]
d2
,
d3
;
// registered data in, converted to sign+ absolute value
283
wire
[
27
:
0
]
qmul
;
284
wire
start_a
;
285
reg
[
15
:
0
]
tdor
;
286
reg
[
20
:
0
]
qmulr
;
// added 7 bits to total8 fractional for biasing/zero bin
287
wire
start_out
;
288
wire
start_z
;
289
reg
[
8
:
0
]
dc1
;
// registered DC average - with restored sign
290
291
// for fifo for ctype, dc
292
wire
ctype
;
293
wire
[
8
:
0
]
dc
;
294
// wire next_dv;
295
// reg [ 2:0] last_dv; // last dv cycle (will turn of unless new ds)
296
reg
[
2
:
0
]
ds_r
;
297
reg
[
3
:
0
]
ren
;
298
299
reg
[
5
:
0
]
start
;
300
wire
dcc_stb
;
301
reg
dcc_run
;
302
reg
dcc_first
;
303
reg
dcc_Y
;
304
reg
[
1
:
0
]
ctype_prev
;
305
reg
[
12
:
0
]
dcc_acc
;
306
reg
[
12
:
0
]
hfc_acc
;
307
wire
hfc_en
;
308
reg
hfc_copy
;
// copy hfc_acc to dcc_acc
309
wire
[
10
:
0
]
d2_dct
;
// 11 bits enough, convetred to positive (before - 0 was in the middle - pixel value 128) - dcc only
310
reg
sel_satnum
;
// select saturation numbers - dcc only
311
reg
[
15
:
0
]
pre_dc_tdo
;
312
wire
copy_dc_tdo
;
313
314
reg
first_interm
;
// valid @ ds
315
316
wire
[
2
:
0
]
ts
;
317
wire
[
2
:
0
]
coring_sel
;
318
319
reg
[
2
:
0
]
block_mem_ra
;
320
reg
[
2
:
0
]
block_mem_wa
;
321
reg
[
2
:
0
]
block_mem_wa_save
;
322
reg
[
15
:
0
]
block_mem_ram
[
0
:
7
];
323
wire
[
15
:
0
]
block_mem_o
=
block_mem_ram
[
block_mem_ra
[
2
:
0
]];
324
325
assign
dc
[
8
:
0
] =
block_mem_o
[
8
:
0
];
326
assign
ctype
=
block_mem_o
[
9
];
327
assign
ts
[
2
:
0
] =
block_mem_o
[
12
:
10
];
328
assign
coring_sel
[
2
:
0
] =
block_mem_o
[
15
:
13
];
329
330
assign
start_a
=
start
[
5
];
331
assign
start_z
=
start
[
4
];
332
assign
dcc_stb
=
start
[
2
];
333
assign
ds
=
ds_r
[
2
];
334
assign
dv
=
ren
[
3
];
335
always
@ (
posedge
clk
)
begin
336
if
(
stb
)
block_mem_ram
[
block_mem_wa
[
2
:
0
]] <= {
coring_num
[
2
:
0
],
tsi
[
2
:
0
],
ctypei
,
dci
[
8
:
0
]};
337
338
if
(!
en
)
block_mem_wa
[
2
:
0
] <=
3'h0
;
339
else
if
(
stb
)
block_mem_wa
[
2
:
0
] <=
block_mem_wa
[
2
:
0
] +
1
;
340
341
if
(
stb
&&
first_stb
)
block_mem_wa_save
[
2
:
0
] <=
block_mem_wa
[
2
:
0
];
342
343
if
(!
en
)
block_mem_ra
[
2
:
0
] <=
3'h0
;
344
else
if
(
pre_start
)
block_mem_ra
[
2
:
0
] <=
first_in
?
block_mem_wa_save
[
2
:
0
]:(
block_mem_ra
[
2
:
0
] +
1
);
345
end
346
347
assign
d2_dct
[
10
:
0
]={!
d2
[
11
] ^
ctype_prev
[
0
],
d2
[
9
:
0
]};
348
349
assign
dcc_data
[
15
:
0
]=
sel_satnum
?
350
{
n255
[
7
:
0
],
n000
[
7
:
0
]}:
351
{
dcc_first
|| (!
dcc_Y
&&
dcc_acc
[
12
]) ,(!
dcc_Y
&&
dcc_acc
[
12
]), (!
dcc_Y
&&
dcc_acc
[
12
]),
dcc_acc
[
12
:
0
]};
352
// assign do[12:0]=zigzag_q[12:0];
353
assign
qmul
[
27
:
0
]=
tdor
[
15
:
0
]*
d3
[
11
:
0
];
354
355
assign
start_out
=
zwe
&& (
zwa
[
5
:
0
]==
6'h3f
);
//adjust?
356
assign
copy_dc_tdo
=
zwe
&& (
zwa
[
5
:
0
]==
6'h37
);
// not critical
357
358
// assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
359
always
@ (
posedge
clk
)
begin
360
d1
[
12
:
0
] <=
di
[
12
:
0
];
361
//inv_sign
362
dc1
[
8
:
0
] <=
start
[
0
]?
dc
[
8
:
0
]:
9'b0
;
// sync to d1[8:0]ctype valid at start, not later
363
d2
[
12
:
0
] <= {
dc1
[
8
],
dc1
[
8
:
0
],
3'b0
} +
d1
[
12
:
0
];
364
d3
[
12
] <=
d2
[
12
];
365
d3
[
11
:
0
] <=
d2
[
12
]? -
d2
[
11
:
0
]:
d2
[
11
:
0
];
366
367
if
(
start
[
0
] || !
en
)
tba
[
9
:
6
] <= {
ts
[
2
:
0
],
ctype
};
368
369
/// TODO - make sure ctype switches at needed time (compensate if needed) *****************************************
370
if
(
start
[
3
] || !
en
)
tbac
[
3
:
0
] <= {
coring_sel
[
2
:
0
],
ctype
};
// table number to use
371
372
if
(
start
[
0
])
tba
[
5
:
0
] <=
6'b0
;
373
else
if
(
tba
[
5
:
0
]!=
6'h3f
)
tba
[
5
:
0
] <=
tba
[
5
:
0
]+
1
;
374
375
tdor
[
15
:
0
] <=
tdo
[
15
:
0
];
// registered table data out
376
377
if
(
start
[
3
])
pre_dc_tdo
[
15
:
0
] <=
tdor
[
15
:
0
];
//16-bit q. tables)
378
379
if
(
copy_dc_tdo
)
dc_tdo
[
15
:
0
] <=
pre_dc_tdo
[
15
:
0
];
380
381
qmulr
[
19
:
0
] <=
qmul
[
27
:
8
];
// absolute value
382
qmulr
[
20
] <=
d3
[
12
];
// sign
383
qdo0
[
12
] <=
qmulr
[
20
];
// sign
384
385
// tdco[3:0] - same timing as qdo0;
386
// use lookup table from 8 bits of absolute value (4.4 - 4 fractional) to calculate 4 bit coring output that would replace output
387
// if input is less thahn 16. For larger values the true rounding will be used.
388
389
// Absolute values here have quantization coefficients already applied, so we can use the same coring table for all DCT coefficients.
390
// there are be 16 tables - 8 Y/C pairs to switch
391
qdo0
[
11
:
0
] <=
qmulr
[
19
:
8
] +
qmulr
[
7
];
// true rounding of the absolute value
392
coring_range
<= !(|
qmulr
[
19
:
12
]) && !(&
qmulr
[
11
:
7
]) ;
// valid with qdo0
393
qdo
[
11
:
0
] <=
coring_range
? (
qdo0
[
12
]?-{
8'h0
,
tdco
[
3
:
0
]}:{
8'h0
,
tdco
[
3
:
0
]}):(
qdo0
[
12
]?-
qdo0
[
11
:
0
]:
qdo0
[
11
:
0
]);
394
qdo
[
12
] <=
qdo0
[
12
] && (!
coring_range
|| (
tdco
[
3
:
0
]!=
4'h0
));
395
396
if
(
start_out
)
rpage
<=
wpage
;
397
398
// last_dv <= {last_dv[1:0], en && (zra[5:0] == 6'h3f)};
399
400
if
(
start_out
)
zra
[
5
:
0
] <=
6'b0
;
401
// else if (zra[5:0]!=6'h3f) zra[5:0] <= zra[5:0]+1; // conserving energy
402
else
if
(
ren
[
0
])
zra
[
5
:
0
] <=
zra
[
5
:
0
]+
1
;
// conserving energy
403
404
ds_r
<= {
ds_r
[
1
:
0
],
en
&&
start_out
};
405
406
if
(!
en
)
ren
[
0
] <=
0
;
407
else
if
(
start_out
)
ren
[
0
] <=
1
;
408
else
if
((
zra
[
5
:
0
] ==
6'h3f
))
ren
[
0
] <=
0
;
409
410
if
(!
en
)
ren
[
3
:
1
] <=
0
;
411
else
ren
[
3
:
1
] <=
ren
[
2
:
0
];
412
413
if
(
ren
[
2
])
do
[
12
:
0
] <=
zigzag_q
[
12
:
0
];
414
415
if
(
start_a
)
first_interm
<=
first_in
;
416
if
(
start_out
)
first_out
<=
first_interm
;
417
// zwe???
418
zwe
<=
en
&& (
start_a
|| (
zwe
&& (
zwa
[
5
:
0
]!=
6'h3f
)));
419
if
(!
en
)
wpage
<=
1'b0
;
420
else
if
(
start_a
)
wpage
<= ~
wpage
;
421
end
422
423
424
always
@ (
posedge
clk
)
begin
425
sel_satnum
<=
dcc_run
&& (
start
[
0
]? (
ctype_prev
[
1
:
0
]==
2'b10
):
sel_satnum
);
426
427
hfc_copy
<=
dcc_run
&& (
hfc_sel
[
2
:
0
]!=
3'h7
) && (
tba
[
5
:
0
]==
6'h1f
) &&
ctype_prev
[
0
] &&
ctype_prev
[
1
];
428
429
start
[
5
:
0
] <= {
start
[
4
:
0
],
pre_start
};
// needed?
430
431
if
(!
dcc_en
)
dcc_run
<=
1'b0
;
432
else
if
(
start
[
0
])
dcc_run
<=
1'b1
;
433
434
if
(!
dcc_en
)
ctype_prev
[
1
:
0
] <=
2'b11
;
435
else
if
(
start
[
0
])
ctype_prev
[
1
:
0
] <= {
ctype_prev
[
0
],
ctype
&&
dcc_run
};
436
437
if
(
dcc_stb
||
hfc_copy
)
dcc_acc
[
12
:
0
] <=
hfc_copy
?
438
hfc_acc
[
12
:
0
]:
439
{(
d2_dct
[
10
]&&
ctype_prev
[
0
]),(
d2_dct
[
10
]&&
ctype_prev
[
0
]),
d2_dct
[
10
:
0
]}+((
ctype_prev
[
0
] ||
ctype_prev
[
1
])?
13'h0
:
dcc_acc
[
12
:
0
]);
440
441
if
(!
dcc_run
||
hfc_copy
)
hfc_acc
<=
13'b0
;
442
else
if
(
hfc_en
)
hfc_acc
<=
hfc_acc
+ {
2'b0
,
d3
[
10
:
0
]};
443
444
if
(
dcc_stb
)
dcc_first
<=
color_first
&&
dcc_run
&&
dcc_stb
&&
ctype
&& !
ctype_prev
[
0
];
445
446
if
(
dcc_stb
)
dcc_Y
<=
dcc_run
&&
dcc_stb
&&
ctype
&& !
ctype_prev
[
0
];
447
448
dcc_vld
<= (
dcc_run
&&
dcc_stb
&& (
ctype
||
ctype_prev
[
0
] ||
sel_satnum
)) ||
hfc_copy
;
449
end
450
451
wire
twqe
;
452
wire
twce
;
453
wire
[
15
:
0
]
tdi
;
454
wire
[
22
:
0
]
ta
;
455
456
457
table_ad_receive
#(
// here may be changed to 8-bit from 16-bit
458
.
MODE_16_BITS
(
1
),
459
.
NUM_CHN
(
2
)
460
)
table_ad_receive_i
(
461
.
clk
(
mclk
),
// input
462
.
a_not_d
(
tser_a_not_d
),
// input
463
.
ser_d
(
tser_d
),
// input[7:0]
464
.
dv
({
tser_ce
,
tser_qe
}),
// input[1:0]
465
.
ta
(
ta
),
// output[22:0]
466
.
td
(
tdi
),
// output[15:0]
467
.
twe
({
twce
,
twqe
})
// output[1:0]
468
);
469
470
471
// SRL16 i_hfc_en (.Q(hfc_en), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(clk),
472
// .D(((tba[2:0]>hfc_sel[2:0]) || (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0])); // dly=1+1
473
dly_16
#(.
WIDTH
(
1
))
i_hfc_en
(
474
.
clk
(
clk
),
475
.
rst
(
1'b0
),
476
.
dly
(
4'd1
),
477
.
din
(((
tba
[
2
:
0
]>
hfc_sel
[
2
:
0
]) || (
tba
[
5
:
3
]>
hfc_sel
[
2
:
0
])) &&
dcc_run
&& !
ctype_prev
[
0
]),
478
.
dout
(
hfc_en
));
// dly=1+1
479
480
zigzag393
i_zigzag
( .
clk
(
clk
),
481
.
start
(
start_z
),
482
.
q
(
zwa
[
5
:
0
]));
483
484
// All memories below are non-registered, see if they can be made registered
485
ram18_var_w_var_r
#(
486
.
REGISTERS
(
0
),
487
.
LOG2WIDTH_WR
(
4
),
488
.
LOG2WIDTH_RD
(
4
),
489
.
DUMMY
(
0
)
490
`ifdef
PRELOAD_BRAMS, .INIT_00 (
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
491
, .
INIT_01
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
492
, .
INIT_02
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
493
, .
INIT_03
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
494
, .
INIT_04
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
495
, .
INIT_05
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
496
, .
INIT_06
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
497
, .
INIT_07
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
)
498
, .
INIT_08
(
256'h174615551555333340005555800080001555199A200033335555800080005555
)
499
, .
INIT_09
(
256'h155510000F0F199A2AAB40005555555517461249174620003333555555555555
)
500
, .
INIT_0A
(
256'h0E390B210C31100013B117462492333311110C310BA312491746249240004000
)
501
, .
INIT_0B
(
256'h0CCD0C310CCD0BA30CCD0D790E3912490CCD0AAB0AAB0C310F0F100013B1199A
)
502
, .
INIT_0C
(
256'h0CCD0CCD0CCD0CCD13B13333400040000CCD0CCD0CCD0CCD1C72333340005555
)
503
, .
INIT_0D
(
256'h0CCD0CCD0CCD0CCD0CCD0CCD13B11C720CCD0CCD0CCD0CCD0CCD174633333333
)
504
, .
INIT_0E
(
256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD
)
505
, .
INIT_0F
(
256'h0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD0CCD
)
506
507
`endif
508
)
i_quant_table
(
509
.
rclk
(
clk
),
// input
510
.
raddr
({
tba
[
9
:
6
],
tba
[
2
:
0
],
tba
[
5
:
3
]}),
// input[8:0]
511
.
ren
(
1'b1
),
// input
512
.
regen
(
1'b1
),
// input
513
.
data_out
(
tdo
[
15
:
0
]),
// output[15:0]
514
.
wclk
(
mclk
),
// input
515
.
waddr
(
ta
[
9
:
0
]),
// input[8:0]
516
.
we
(
twqe
),
// input
517
.
web
(
4'hf
),
// input[3:0]
518
.
data_in
(
tdi
[
15
:
0
])
// input[15:0]
519
);
520
521
ram18_var_w_var_r
#(
522
.
REGISTERS
(
0
),
523
.
LOG2WIDTH_WR
(
4
),
524
.
LOG2WIDTH_RD
(
2
),
525
.
DUMMY
(
0
)
526
`ifdef
PRELOAD_BRAMS, .INIT_00 (
256'h4444444433333333333333332222222222222222111111111111111100000000
)
527
, .
INIT_01
(
256'h8888888877777777777777776666666666666666555555555555555544444444
)
528
, .
INIT_02
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
529
, .
INIT_03
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
530
, .
INIT_04
(
256'h4444444433333333333333332222222222222222111111111111111100000000
)
531
, .
INIT_05
(
256'h8888888877777777777777776666666666666666555555555555555544444444
)
532
, .
INIT_06
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
533
, .
INIT_07
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
534
, .
INIT_08
(
256'h4444444433333333333333322222222222222221111111111111100000000000
)
535
, .
INIT_09
(
256'h8888888877777777777777776666666666666666555555555555555544444444
)
536
, .
INIT_0A
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
537
, .
INIT_0B
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
538
, .
INIT_0C
(
256'h4444444433333333333333322222222222222221111111111111100000000000
)
539
, .
INIT_0D
(
256'h8888888877777777777777776666666666666666555555555555555544444444
)
540
, .
INIT_0E
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
541
, .
INIT_0F
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
542
, .
INIT_10
(
256'h4444444333333333333333322222222222222211111111111000000000000000
)
543
, .
INIT_11
(
256'h8888888877777777777777776666666666666666555555555555555444444444
)
544
, .
INIT_12
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
545
, .
INIT_13
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
546
, .
INIT_14
(
256'h4444444333333333333333322222222222222211111111111000000000000000
)
547
, .
INIT_15
(
256'h8888888877777777777777776666666666666666555555555555555444444444
)
548
, .
INIT_16
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
549
, .
INIT_17
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
550
, .
INIT_18
(
256'h4444443333333333333222222222211111111111100000000000000000000000
)
551
, .
INIT_19
(
256'h8888888877777777777777766666666666666665555555555555555444444444
)
552
, .
INIT_1A
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
553
, .
INIT_1B
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
554
, .
INIT_1C
(
256'h4444443333333333333222222222211111111111100000000000000000000000
)
555
, .
INIT_1D
(
256'h8888888877777777777777766666666666666665555555555555555444444444
)
556
, .
INIT_1E
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999988888888
)
557
, .
INIT_1F
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
558
, .
INIT_20
(
256'h3333333332222222222211111111111111000000000000000000000000000000
)
559
, .
INIT_21
(
256'h8888888777777777777777766666666666666665555555555555544444444444
)
560
, .
INIT_22
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999888888888
)
561
, .
INIT_23
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
562
, .
INIT_24
(
256'h3333333332222222222211111111111111000000000000000000000000000000
)
563
, .
INIT_25
(
256'h8888888777777777777777766666666666666665555555555555544444444444
)
564
, .
INIT_26
(
256'hCCCCCCCCBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA999999999999999888888888
)
565
, .
INIT_27
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
566
, .
INIT_28
(
256'h2222222222211111111111111110000000000000000000000000000000000000
)
567
, .
INIT_29
(
256'h8888888777777777777777666666666666655555555554444444443333333333
)
568
, .
INIT_2A
(
256'hCCCCCCCCBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA9999999999999999888888888
)
569
, .
INIT_2B
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
570
, .
INIT_2C
(
256'h2222222222211111111111111110000000000000000000000000000000000000
)
571
, .
INIT_2D
(
256'h8888888777777777777777666666666666655555555554444444443333333333
)
572
, .
INIT_2E
(
256'hCCCCCCCCBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAA9999999999999999888888888
)
573
, .
INIT_2F
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCC
)
574
, .
INIT_31
(
256'h5555444444443333333333322222222222221111111111111111111111110000
)
575
, .
INIT_32
(
256'hCCCCCCCBBBBBBBBBBBBBBAAAAAAAAA9999999998888888777777766666665555
)
576
, .
INIT_33
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCCC
)
577
, .
INIT_35
(
256'h5555444444443333333333322222222222221111111111111111111111110000
)
578
, .
INIT_36
(
256'hCCCCCCCBBBBBBBBBBBBBBAAAAAAAAA9999999998888888777777766666665555
)
579
, .
INIT_37
(
256'hFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDCCCCCCCCC
)
580
, .
INIT_3B
(
256'hFFFFFFFFFEEDCBA9987766555444333332222222211111111111111111111100
)
581
, .
INIT_3F
(
256'hFFFFFFFFFEEDCBA9987766555444333332222222211111111111111111111100
)
582
583
`endif
584
)
i_coring_table
(
585
.
rclk
(
clk
),
// input
586
.
raddr
({
tbac
[
3
:
0
],
qmulr
[
11
:
4
]}),
// input[10:0]
587
.
ren
(
1'b1
),
// input
588
.
regen
(
1'b1
),
// input
589
.
data_out
(
tdco
[
3
:
0
]),
// output[3:0]
590
.
wclk
(
mclk
),
// input
591
.
waddr
(
ta
[
9
:
0
]),
// input[9:0]
592
.
we
(
twce
),
// input
593
.
web
(
4'hf
),
// input[3:0]
594
.
data_in
(
tdi
[
15
:
0
])
// input[15:0]
595
);
596
597
ram18_var_w_var_r
#(
598
.
REGISTERS
(
1
),
599
.
LOG2WIDTH_WR
(
4
),
600
.
LOG2WIDTH_RD
(
4
),
601
.
DUMMY
(
0
)
602
)
i_zigzagbuf
(
603
.
rclk
(
clk
),
// input
604
.
raddr
({
3'b0
,
rpage
,
zra
[
5
:
0
]}),
// input[9:0]
605
.
ren
(
ren
[
0
]),
// input
606
.
regen
(
ren
[
1
]),
// input
607
.
data_out
(
zigzag_q
[
15
:
0
]),
// output[15:0]
608
.
wclk
(
clk
),
// input
609
.
waddr
({
3'b0
,
wpage
,
zwa
[
5
:
0
]}),
// input[9:0]
610
.
we
(
zwe
),
// input
611
.
web
(
4'hf
),
// input[3:0]
612
.
data_in
({
3'b0
,
qdo
[
12
:
0
]})
// input[15:0]
613
);
614
615
616
endmodule
617
618
module
zigzag393
(
619
input
clk
,
// system clock, posedge
620
input
start
,
621
output
reg
[
5
:
0
]
q
);
622
623
reg
[
5
:
0
]
a
;
624
wire
[
4
:
0
]
rom_a
;
625
reg
[
5
:
0
]
rom_q
;
626
627
assign
rom_a
[
4
:
0
]=
a
[
5
]?(~
a
[
4
:
0
]):
a
[
4
:
0
];
628
629
always
@ (
posedge
clk
)
begin
630
if
(
start
)
a
[
5
:
0
] <=
6'b0
;
631
else
if
(
a
[
5
:
0
]!=
6'h3f
)
a
[
5
:
0
] <=
a
[
5
:
0
]+
1
;
632
end
633
634
// ROM (combinatorial)
635
always
@(
rom_a
)
case
(
rom_a
)
636
5'h00
:
rom_q
<=
6'h00
;
637
5'h01
:
rom_q
<=
6'h02
;
638
5'h02
:
rom_q
<=
6'h03
;
639
5'h03
:
rom_q
<=
6'h09
;
640
5'h04
:
rom_q
<=
6'h0a
;
641
5'h05
:
rom_q
<=
6'h14
;
642
5'h06
:
rom_q
<=
6'h15
;
643
5'h07
:
rom_q
<=
6'h23
;
644
5'h08
:
rom_q
<=
6'h01
;
645
5'h09
:
rom_q
<=
6'h04
;
646
5'h0a
:
rom_q
<=
6'h08
;
647
5'h0b
:
rom_q
<=
6'h0b
;
648
5'h0c
:
rom_q
<=
6'h13
;
649
5'h0d
:
rom_q
<=
6'h16
;
650
5'h0e
:
rom_q
<=
6'h22
;
651
5'h0f
:
rom_q
<=
6'h24
;
652
5'h10
:
rom_q
<=
6'h05
;
653
5'h11
:
rom_q
<=
6'h07
;
654
5'h12
:
rom_q
<=
6'h0c
;
655
5'h13
:
rom_q
<=
6'h12
;
656
5'h14
:
rom_q
<=
6'h17
;
657
5'h15
:
rom_q
<=
6'h21
;
658
5'h16
:
rom_q
<=
6'h25
;
659
5'h17
:
rom_q
<=
6'h30
;
660
5'h18
:
rom_q
<=
6'h06
;
661
5'h19
:
rom_q
<=
6'h0d
;
662
5'h1a
:
rom_q
<=
6'h11
;
663
5'h1b
:
rom_q
<=
6'h18
;
664
5'h1c
:
rom_q
<=
6'h20
;
665
5'h1d
:
rom_q
<=
6'h26
;
666
5'h1e
:
rom_q
<=
6'h2f
;
667
5'h1f
:
rom_q
<=
6'h31
;
668
endcase
669
// add symmetrical part
670
always
@ (
posedge
clk
)
q
[
5
:
0
] <=
a
[
5
]? (~
rom_q
[
5
:
0
]):
rom_q
[
5
:
0
];
671
endmodule
672
quantizer393.2920tser_qe
2920tser_qe
Definition:
quantizer393.v:48
ram18_var_w_var_r.11591regen
11591regen
Definition:
ram18_var_w_var_r.v:114
quantizer393.2949tba
2949tbareg[9:0]
Definition:
quantizer393.v:80
quantizer393.2951wpage
2951wpagereg
Definition:
quantizer393.v:82
quantizer393.2927stb
2927stb
Definition:
quantizer393.v:55
quantizer393.2996tdi
2996tdiwire[15:0]
Definition:
quantizer393.v:261
quantizer393.2967dc1
2967dc1reg[8:0]
Definition:
quantizer393.v:97
quantizer393.2992block_mem_ram
[0:7] 2992block_mem_ramreg[15:0]
Definition:
quantizer393.v:130
quantizer393.2955qdo
2955qdoreg[12:0]
Definition:
quantizer393.v:86
dly_16.10332clk
10332clk
Definition:
dly_16.v:44
quantizer393.2990block_mem_wa
2990block_mem_wareg[2:0]
Definition:
quantizer393.v:128
quantizer393.2968ctype
2968ctypewire
Definition:
quantizer393.v:100
quantizer393.2977ctype_prev
2977ctype_prevreg[1:0]
Definition:
quantizer393.v:112
quantizer393.2944n255
[ 7:0] 2944n255
Definition:
quantizer393.v:73
table_ad_receive.11054twe
[NUM_CHN-1:0] 11054twe
Definition:
table_ad_receive.v:51
quantizer393.2966start_z
2966start_zwire
Definition:
quantizer393.v:96
quantizer393.2924ctypei
2924ctypei
Definition:
quantizer393.v:52
quantizer393.2995twce
2995twcewire
Definition:
quantizer393.v:260
quantizer393.2970ds_r
2970ds_rreg[2:0]
Definition:
quantizer393.v:104
table_ad_receive.11049a_not_d
11049a_not_d
Definition:
table_ad_receive.v:46
quantizer393.2989block_mem_ra
2989block_mem_rareg[2:0]
Definition:
quantizer393.v:127
quantizer393.2973dcc_stb
2973dcc_stbwire
Definition:
quantizer393.v:108
zigzag393.3001a
3001areg[5:0]
Definition:
quantizer393.v:361
ram18_var_w_var_r.11597data_in
[1 << LOG2WIDTH_WR-1:0] 11597data_in
Definition:
ram18_var_w_var_r.v:121
quantizer393.2991block_mem_wa_save
2991block_mem_wa_savereg[2:0]
Definition:
quantizer393.v:129
quantizer393.2960d3
2960d3reg[12:0]
Definition:
quantizer393.v:90
ram18_var_w_var_r.11592data_out
[1 << LOG2WIDTH_RD-1:0] 11592data_out
Definition:
ram18_var_w_var_r.v:115
quantizer393.2956qdo0
2956qdo0reg[12:0]
Definition:
quantizer393.v:87
quantizer393.2952rpage
2952rpagereg
Definition:
quantizer393.v:83
quantizer393.2962start_a
2962start_awire
Definition:
quantizer393.v:92
quantizer393.2997ta
2997tawire[22:0]
Definition:
quantizer393.v:262
ram18_var_w_var_r.11589raddr
[13-LOG2WIDTH_RD:0] 11589raddr
Definition:
ram18_var_w_var_r.v:112
quantizer393.2930first_in
2930first_in
Definition:
quantizer393.v:58
quantizer393.2928tsi
[ 2:0] 2928tsi
Definition:
quantizer393.v:56
quantizer393.2940coring_num
[ 2:0] 2940coring_num
Definition:
quantizer393.v:69
quantizer393.2922tser_a_not_d
2922tser_a_not_d
Definition:
quantizer393.v:50
zigzag393.3002rom_a
3002rom_awire[4:0]
Definition:
quantizer393.v:362
quantizer393.2942dcc_data
[15:0] 2942dcc_data
Definition:
quantizer393.v:71
quantizer393.dly_16
i_hfc_en dly_16
Definition:
quantizer393.v:281
quantizer393.2943n000
[ 7:0] 2943n000
Definition:
quantizer393.v:72
quantizer393.2937dcc_en
2937dcc_en
Definition:
quantizer393.v:65
quantizer393.2947coring_range
2947coring_rangereg
Definition:
quantizer393.v:78
quantizer393.2946tbac
2946tbacreg[3:0]
Definition:
quantizer393.v:77
quantizer393.2929pre_start
2929pre_start
Definition:
quantizer393.v:57
quantizer393.2978dcc_acc
2978dcc_accreg[12:0]
Definition:
quantizer393.v:113
quantizer393.2931first_out
reg 2931first_out
Definition:
quantizer393.v:59
quantizer393.2969dc
2969dcwire[8:0]
Definition:
quantizer393.v:101
zigzag393.3000q
reg [5:0] 3000q
Definition:
quantizer393.v:359
dly_16.10336dout
[WIDTH-1:0] 10336dout
Definition:
dly_16.v:48
quantizer393.2986first_interm
2986first_intermreg
Definition:
quantizer393.v:122
quantizer393.2917clk
2917clk
Definition:
quantizer393.v:45
table_ad_receive.11053td
[MODE_16_BITS?15:7:0] 11053td
Definition:
table_ad_receive.v:50
ram18_var_w_var_r.11588rclk
11588rclk
Definition:
ram18_var_w_var_r.v:110
quantizer393.2950zigzag_q
2950zigzag_qwire[15:0]
Definition:
quantizer393.v:81
ram18_var_w_var_r.11596web
[ 3:0] 11596web
Definition:
ram18_var_w_var_r.v:120
quantizer393.table_ad_receive
table_ad_receive_i table_ad_receive
Definition:
quantizer393.v:265
quantizer393.2921tser_ce
2921tser_ce
Definition:
quantizer393.v:49
quantizer393.2981hfc_copy
2981hfc_copyreg
Definition:
quantizer393.v:116
quantizer393.2976dcc_Y
2976dcc_Yreg
Definition:
quantizer393.v:111
quantizer393.2987ts
2987tswire[2:0]
Definition:
quantizer393.v:124
quantizer393.2984pre_dc_tdo
2984pre_dc_tdoreg[15:0]
Definition:
quantizer393.v:119
table_ad_receive.11050ser_d
[7:0] 11050ser_d
Definition:
table_ad_receive.v:47
quantizer393.2983sel_satnum
2983sel_satnumreg
Definition:
quantizer393.v:118
quantizer393.2919mclk
2919mclk
Definition:
quantizer393.v:47
quantizer393.2959d2
2959d2reg[12:0]
Definition:
quantizer393.v:90
quantizer393.2954zra
2954zrareg[5:0]
Definition:
quantizer393.v:85
dly_16.10335din
[WIDTH-1:0] 10335din
Definition:
dly_16.v:47
quantizer393.2963tdor
2963tdorreg[15:0]
Definition:
quantizer393.v:93
quantizer393.2923tser_d
[ 7:0] 2923tser_d
Definition:
quantizer393.v:51
quantizer393.2965start_out
2965start_outwire
Definition:
quantizer393.v:95
ram18_var_w_var_r.11590ren
11590ren
Definition:
ram18_var_w_var_r.v:113
quantizer393.ram18_var_w_var_r
i_zigzagbuf ram18_var_w_var_r
Definition:
quantizer393.v:335
quantizer393.2953zwa
2953zwawire[5:0]
Definition:
quantizer393.v:84
ram18_var_w_var_r.11595we
11595we
Definition:
ram18_var_w_var_r.v:119
quantizer393.zigzag393
i_zigzag zigzag393
Definition:
quantizer393.v:288
quantizer393.2980hfc_en
2980hfc_enwire
Definition:
quantizer393.v:115
quantizer393.2941dcc_vld
reg 2941dcc_vld
Definition:
quantizer393.v:70
quantizer393.2938hfc_sel
[ 2:0] 2938hfc_sel
Definition:
quantizer393.v:66
quantizer393.2945tdco
2945tdcowire[3:0]
Definition:
quantizer393.v:76
table_ad_receive.11052ta
[23-MODE_16_BITS:0] 11052ta
Definition:
table_ad_receive.v:49
zigzag393.3003rom_q
3003rom_qreg[5:0]
Definition:
quantizer393.v:363
quantizer393.2948tdo
2948tdowire[15:0]
Definition:
quantizer393.v:79
ram18_var_w_var_r.11594waddr
[13-LOG2WIDTH_WR:0] 11594waddr
Definition:
ram18_var_w_var_r.v:118
quantizer393.2988coring_sel
2988coring_selwire[2:0]
Definition:
quantizer393.v:125
quantizer393.2993block_mem_o
2993block_mem_owire[15:0]
Definition:
quantizer393.v:131
quantizer393.2925dci
[ 8:0] 2925dci
Definition:
quantizer393.v:53
quantizer393.2974dcc_run
2974dcc_runreg
Definition:
quantizer393.v:109
quantizer393.2975dcc_first
2975dcc_firstreg
Definition:
quantizer393.v:110
quantizer393.2982d2_dct
2982d2_dctwire[10:0]
Definition:
quantizer393.v:117
quantizer393.2935ds
2935ds
Definition:
quantizer393.v:63
quantizer393.2972start
2972startreg[5:0]
Definition:
quantizer393.v:107
quantizer393.2971ren
2971renreg[3:0]
Definition:
quantizer393.v:105
quantizer393.2958d1
2958d1reg[12:0]
Definition:
quantizer393.v:89
quantizer393.2926first_stb
2926first_stb
Definition:
quantizer393.v:54
quantizer393.2979hfc_acc
2979hfc_accreg[12:0]
Definition:
quantizer393.v:114
quantizer393.2934dv
2934dv
Definition:
quantizer393.v:62
quantizer393.2932di
[12:0] 2932di
Definition:
quantizer393.v:60
quantizer393.2936dc_tdo
reg [15:0] 2936dc_tdo
Definition:
quantizer393.v:64
zigzag393.2999start
2999start
Definition:
quantizer393.v:358
zigzag393.2998clk
2998clk
Definition:
quantizer393.v:357
quantizer393.2933do
reg [12:0] 2933do
Definition:
quantizer393.v:61
dly_16.10333rst
10333rst
Definition:
dly_16.v:45
quantizer393.2918en
2918en
Definition:
quantizer393.v:46
quantizer393.2939color_first
2939color_first
Definition:
quantizer393.v:68
quantizer393.2985copy_dc_tdo
2985copy_dc_tdowire
Definition:
quantizer393.v:120
quantizer393.2961qmul
2961qmulwire[27:0]
Definition:
quantizer393.v:91
table_ad_receive.11051dv
[NUM_CHN-1:0] 11051dv
Definition:
table_ad_receive.v:48
table_ad_receive.11048clk
11048clk
Definition:
table_ad_receive.v:45
quantizer393.2964qmulr
2964qmulrreg[20:0]
Definition:
quantizer393.v:94
ram18_var_w_var_r.11593wclk
11593wclk
Definition:
ram18_var_w_var_r.v:117
quantizer393
Definition:
quantizer393.v:44
quantizer393.2994twqe
2994twqewire
Definition:
quantizer393.v:259
quantizer393.2957zwe
2957zwereg
Definition:
quantizer393.v:88
dly_16.10334dly
[3:0] 10334dly
Definition:
dly_16.v:46
compressor_jp
quantizer393.v
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