675
5371xfer_limited_by_mem_page_rreg
5362window_heightreg[FRAME_HEIGHT_BITS:0]
5274NUM_RC_BURST_BITSADDRESS_NUMBER+COLADDR_NUMBER-3
5237MCONTR_LINTILE_EXTRAPG_BITS2
5356frame_number_cntrreg[LAST_FRAME_BITS-1:0]
5363window_x0reg[FRAME_WIDTH_BITS-1:0]
cmd_deser_32bit_i cmd_deser
[COLADDR_NUMBER-4:0] 5266xfer_col
5292line_start_page_leftreg[COLADDR_NUMBER-4:0]
5294remainder_in_xferwire[COLADDR_NUMBER-3:0]
5219MCNTRL_SCANLINE_ADDR'h120
5241MCONTR_LINTILE_DIS_NEED11
5359frame_start_rreg[4:0]
5285mul_rsltreg[MPY_WIDTH-1:0]
5228MCNTRL_SCANLINE_WINDOW_X0Y0'h7
5376frame_start_pendingreg
[LAST_FRAME_BITS-1:0] 5257frame_number
5312cmd_extra_pageswire[1:0]
5354start_addrreg[NUM_RC_BURST_BITS-1:0]
5347set_window_start_wwire
5344set_frame_width_wwire
5302par_mod_rreg[PAR_MOD_LATENCY-1:0]
[NUM_XFER_BITS-1:0] 5267xfer_num128
5238MCONTR_LINTILE_RST_FRAME8
5242MCONTR_LINTILE_SKIP_LATE12
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
5296leftoverreg[NUM_XFER_BITS-1:0]
5222MCNTRL_SCANLINE_STATUS_CNTRL'h1
5377frame_start_pending_longreg[1:0]
5229MCNTRL_SCANLINE_WINDOW_STARTXY'h8
5288mul_rslt_wwire[FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0]
5352frame_sizereg[NUM_RC_BURST_BITS-1:0]
5381start_not_partialwire
[FRAME_HEIGHT_BITS-1:0] 5255line_unfinished
5293lim_by_xferreg[NUM_XFER_BITS:0]
5351start_range_addrreg[NUM_RC_BURST_BITS-1:0]
5284frame_full_width_rreg[FRAME_WIDTH_BITS:0]
5279next_yreg[FRAME_HEIGHT_BITS:0]
5364window_y0reg[FRAME_HEIGHT_BITS-1:0]
5278curr_yreg[FRAME_HEIGHT_BITS-1:0]
5231MCNTRL_SCANLINE_PENDING_CNTR_BITS2
status_generate_i status_generate
5289row_leftreg[FRAME_WIDTH_BITS:0]
5280line_start_addrreg[NUM_RC_BURST_BITS-1:0]
5379frame_start_delayedwire
[DATA_WIDTH-1:0] 9934data
5303recalc_rreg[PAR_MOD_LATENCY-1:0]
5365start_xreg[FRAME_WIDTH_BITS-1:0]
5226MCNTRL_SCANLINE_FRAME_FULL_WIDTH'h5
5232MCNTRL_SCANLINE_FRAME_PAGE_RESET1'b0
5275MPY_WIDTHNUM_RC_BURST_BITS
5319rst_frame_num_rreg[1:0]
5329pending_xfersreg[MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0]
5332line_unfinished_rreg[FRAME_HEIGHT_BITS-1:0]
5221MCNTRL_SCANLINE_MODE'h0
5346set_window_x0y0_wwire
5366start_yreg[FRAME_HEIGHT_BITS-1:0]
[ADDR_WIDTH-1:0] 9933addr
[COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] 5368EXTRA_BITS0
5223MCNTRL_SCANLINE_STARTADDR'h2
5277curr_xreg[FRAME_WIDTH_BITS-1:0]
5370xfer_limited_by_mem_pagewire
5360frame_full_widthreg[FRAME_WIDTH_BITS:0]
5283frame_y8_rreg[FRAME_HEIGHT_BITS-4:0]
5291mem_page_leftreg[COLADDR_NUMBER-3:0]
5297xfer_num128_rreg[NUM_XFER_BITS:0]
5361window_widthreg[FRAME_WIDTH_BITS:0]
5282frame_xreg[FRAME_WIDTH_BITS-1:0]
5378xfer_done_skippedwire
5235MCONTR_LINTILE_WRITE2
5331line_unfinished_relw_rreg[FRAME_HEIGHT_BITS-1:0]
5227MCNTRL_SCANLINE_WINDOW_WH'h6
5286start_addr_rreg[NUM_RC_BURST_BITS-1:0]
[ADDRESS_NUMBER-1:0] 5265xfer_row
5230MCNTRL_SCANLINE_STATUS_REG_ADDR'h4
5225MCNTRL_SCANLINE_FRAME_LAST'h4
5281frame_yreg[FRAME_HEIGHT_BITS-1:0]
5236MCONTR_LINTILE_EXTRAPG3
5240MCONTR_LINTILE_REPEAT10
5233MCONTR_LINTILE_NRESET0
[ALL_BITS-1:0] 10777status
5353last_frame_numberreg[LAST_FRAME_BITS-1:0]
5330row_col_rreg[NUM_RC_BURST_BITS-1:0]
5239MCONTR_LINTILE_SINGLE9
5224MCNTRL_SCANLINE_FRAME_SIZE'h3
5357frame_number_currentreg[LAST_FRAME_BITS-1:0]
5220MCNTRL_SCANLINE_MASK'h7f0
5355next_frame_start_addrreg[NUM_RC_BURST_BITS-1:0]