43 // update to eliminate need for a shadow register 44 // each pair of data bits at write cycle control the data and enable in the following way: 45 // bit 1 bit 0 dibit enable data 46 // 0 0 0 - no change - 52 //Unified IO control for the 6 pins that are connected from the FPGA to the inter-board 16-pin connector 53 // those pins were controlled (in models 303, 313, 323 and earlier 333) by the control register, status was 54 // read through the status register. 56 // Now each pin will be controlled by 2 bits (data+enable), total 12 bits that will come from one of 4 sources 57 // selected by bits [13:12] of the new control word: 58 // 0 - use bits [11:0] of the control word 59 // 1 - use channel A (camsync) 60 // 2 - use channel B (tbd) 61 // 3 - use channel C (tbd) 63 // global enable signals (disabled channel will not compete for per-biot access) 64 // next 4 enable signals are controlled by bit pairs (0X - don't change, 10 - disable, 11 - enable) 65 // bit [25:24] - enable software bits (contolled by bits [23:0] (on at powerup) 66 // bit [27:26] - enable chn. A 67 // bit [29:28] - enable chn. B 68 // bit [31:30] - enable chn. C 69 // Enabled bits will be priority encoded (C - highest, software - lowest) 71 parameter GPIO_ADDR =
'h700,
//TODO: assign valid address 80 parameter GPIO_SET_PINS =
0,
// Set GPIO output state, give control for some bits to other modules 82 parameter GPIO_N =
10,
// number of GPIO bits to control 83 parameter GPIO_PORTEN =
24 // bit number to control port enables (up from this) 86 // input rst, // global reset 87 input mclk,
// system clock 88 input mrst,
// @posedge mclk, sync reset 89 input [
7:
0]
cmd_ad,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 90 input cmd_stb,
// strobe (with first byte) for the command a/d 92 output [
7:
0]
status_ad,
// status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] 93 output status_rq,
// input request to send status downstream 94 input status_start,
// Acknowledge of the first status packet byte (address) 96 inout [
GPIO_N-
1:
0]
ext_pins,
// GPIO pins (1.5V): assigned in 10389: [1:0] - i2c, [5:2] - gpio, [GPIO_N-1:6] - sync i/o 97 output [
GPIO_N-
1:
0]
io_pins,
// values on the gpio pins (to use by other modules on ports A,B,C) 108 wire [
GPIO_N-
1:
0]
ds;
// "software" data (programmed by lower 24 bits) 109 wire [
GPIO_N-
1:
0]
ds_en;
// "software" data enable (programmed by lower 24 bits) 110 reg [
3:
0]
ch_en =
0;
// channel enable 141 // 0 0 0 - no change - 163 for (
i=
0;
i <
GPIO_N;
i=
i+
1)
begin:
gpio_block 165 // .rst (rst), // input 182 .
T (
io_t[
i])
// input 195 )
cmd_deser_32bit_i (
196 .
rst (
1'b0),
//rst), // input 210 )
status_generate_i (
211 .
rst (
1'b0),
// rst), // input 226 // input rst, // global reset 227 input clk,
// system clock 228 input srst,
// @posedge clk - sync reset 230 input [
1:
0]
d_in,
// input bits 239 always @ (
posedge clk)
begin
10533ds_enwire[GPIO_N-1:0]
cmd_deser_32bit_i cmd_deser
[GPIO_N-1:0] 10525io_pins
10508GPIO_STATUS_REG_ADDR'h30
integer 10509GPIO_DRIVE12
status_generate_i status_generate
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
10510GPIO_IBUF_LOW_PWR"TRUE"
10544io_twire[GPIO_N-1:0]
10545io_dowire[GPIO_N-1:0]
[GPIO_N-1:0] 10524ext_pins
[DATA_WIDTH-1:0] 9934data
10511GPIO_IOSTANDARD"DEFAULT"
10543dc_en_mwire[GPIO_N-1:0]
[ADDR_WIDTH-1:0] 9933addr
10542db_en_mwire[GPIO_N-1:0]
iobuf_gpio_i iobuf[generate]
10540ds_en_mwire[GPIO_N-1:0]
gpio_bit_i gpio_bit[generate]
[ALL_BITS-1:0] 10777status
10541da_en_mwire[GPIO_N-1:0]