x393  1.0
FPGAcodeforElphelNC393camera
Static Public Member Functions | Public Attributes | List of all members
sens_hispi12l4 Module Reference
Inheritance diagram for sens_hispi12l4:
Inheritance graph
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Collaboration diagram for sens_hispi12l4:
Collaboration graph
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Static Public Member Functions

Always Constructs

ALWAYS_347  ( mclk )
ALWAYS_348  ( ipclk )
ALWAYS_349  ( ipclk )
ALWAYS_350  ( ipclk or prst )
ALWAYS_351  ( ipclk )
ALWAYS_352  ( pclk )

Public Attributes

Inputs

pclk  
prst  
sns_dp   [HISPI_NUMLANES - 1 : 0 ]
sns_dn   [HISPI_NUMLANES - 1 : 0 ]
sns_clkp  
sns_clkn  
mclk  
mrst  
dly_data   [HISPI_NUMLANES * 8 - 1 : 0 ]
set_lanes_map  
set_fifo_dly  
set_idelay   [HISPI_NUMLANES - 1 : 0 ]
ld_idelay  
set_clk_phase  
rst_mmcm  
ignore_embedded  

Outputs

pxd_out   [ 11 : 0 ]
hact_out  
sof  
eof   reg
ps_rdy  
ps_out   [ 7 : 0 ]
locked_pxd_mmcm  
clkin_pxd_stopped_mmcm  
clkfb_pxd_stopped_mmcm  

Parameters

IODELAY_GRP  "IODELAY_SENSOR"
IDELAY_VALUE  integer 0
REFCLK_FREQUENCY  real 200 . 0
HIGH_PERFORMANCE_MODE  "FALSE"
SENS_PHASE_WIDTH   8
SENS_BANDWIDTH  "OPTIMIZED"
CLKIN_PERIOD_SENSOR   3 . 000
CLKFBOUT_MULT_SENSOR   3
CLKFBOUT_PHASE_SENSOR   0 . 000
IPCLK_PHASE   0 . 000
IPCLK2X_PHASE   0 . 000
BUF_IPCLK  "BUFR"
BUF_IPCLK2X  "BUFR"
SENS_DIVCLK_DIVIDE   1
SENS_REF_JITTER1   0 . 010
SENS_REF_JITTER2   0 . 010
SENS_SS_EN  "FALSE"
SENS_SS_MODE  "CENTER_HIGH"
SENS_SS_MOD_PERIOD   10000
DEFAULT_LANE_MAP   8 'b11100100
HISPI_MSB_FIRST   0
HISPI_NUMLANES   4
HISPI_DELAY_CLK  "FALSE"
HISPI_MMCM  "TRUE"
HISPI_KEEP_IRST   5
HISPI_WAIT_ALL_LANES   4 'h8
HISPI_FIFO_DEPTH   4
HISPI_FIFO_START   7
HISPI_CAPACITANCE  "DONT_CARE"
HISPI_DIFF_TERM  "TRUE"
HISPI_UNTUNED_SPLIT  "FALSE"
HISPI_DQS_BIAS  "TRUE"
HISPI_IBUF_DELAY_VALUE  " 0 "
HISPI_IBUF_LOW_PWR  "TRUE"
HISPI_IFD_DELAY_VALUE  "AUTO"
HISPI_IOSTANDARD  "DIFF_SSTL18_I"

GENERATE

GENERATE [380]  

Signals

wire  ipclk
wire  ipclk2x
wire[HISPI_NUMLANES * 4 - 1 : 0 ]  sns_d
reg[HISPI_KEEP_IRST - 1 : 0 ]  irst_r
wire  irst
reg[HISPI_NUMLANES * 2 - 1 : 0 ]  lanes_map
reg[HISPI_NUMLANES * 4 - 1 : 0 ]  logical_lanes4
reg[HISPI_FIFO_DEPTH - 1 : 0 ]  fifo_out_dly_mclk
reg[HISPI_FIFO_DEPTH - 1 : 0 ]  fifo_out_dly
wire[HISPI_NUMLANES * 12 - 1 : 0 ]  hispi_aligned
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_dv
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_embed
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_sof
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_eof
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_sol
wire[HISPI_NUMLANES - 1 : 0 ]  hispi_eol
reg  vact_ipclk
reg[ 1 : 0 ]  vact_pclk_strt
wire[HISPI_NUMLANES - 1 : 0 ]  rd_run
reg  rd_line
reg  rd_line_r
wire  sol_all_dly
reg[HISPI_NUMLANES - 1 : 0 ]  rd_run_d
reg  sof_pclk
wire  sol_pclk
reg  start_fifo_re
reg[HISPI_NUMLANES - 1 : 0 ]  good_lanes
reg[HISPI_NUMLANES - 1 : 0 ]  fifo_re
reg[HISPI_NUMLANES - 1 : 0 ]  fifo_re_r
reg  hact_r
wire[HISPI_NUMLANES * 12 - 1 : 0 ]  fifo_out
wire  hact_on
wire  hact_off
reg  ignore_embedded_ipclk
reg[ 1 : 0 ]  vact_pclk
wire[ 11 : 0 ]  pxd_out_pre

Module Instances

sens_hispi_clock::sens_hispi_clock_i   Module sens_hispi_clock
sens_hispi_din::sens_hispi_din_i   Module sens_hispi_din
dly_16::dly_16_start_line_i   Module dly_16
dly_16::dly_16_hact_on_i   Module dly_16
dly_16::dly_16_hact_off_i   Module dly_16
dly_16::dly_16_pxd_out_i   Module dly_16
sens_hispi_lane::sens_hispi_lane_i   Module sens_hispi_lane [generate]
sens_hispi_fifo::sens_hispi_fifo_i   Module sens_hispi_fifo [generate]

Detailed Description

Definition at line 41 of file sens_hispi12l4.v.

Member Function Documentation

ALWAYS_347 (   mclk  
)
Always Construct

Definition at line 129 of file sens_hispi12l4.v.

ALWAYS_348 (   ipclk  
)
Always Construct

Definition at line 138 of file sens_hispi12l4.v.

ALWAYS_349 (   ipclk  
)
Always Construct

Definition at line 145 of file sens_hispi12l4.v.

ALWAYS_350 (   ipclk or prst  
)
Always Construct

Definition at line 275 of file sens_hispi12l4.v.

ALWAYS_351 (   ipclk  
)
Always Construct

Definition at line 282 of file sens_hispi12l4.v.

ALWAYS_352 (   pclk  
)
Always Construct

Definition at line 291 of file sens_hispi12l4.v.

Member Data Documentation

IODELAY_GRP "IODELAY_SENSOR"
Parameter

Definition at line 42 of file sens_hispi12l4.v.

IDELAY_VALUE 0
Parameter

Definition at line 43 of file sens_hispi12l4.v.

REFCLK_FREQUENCY 200 . 0
Parameter

Definition at line 44 of file sens_hispi12l4.v.

HIGH_PERFORMANCE_MODE "FALSE"
Parameter

Definition at line 45 of file sens_hispi12l4.v.

SENS_PHASE_WIDTH 8
Parameter

Definition at line 46 of file sens_hispi12l4.v.

SENS_BANDWIDTH "OPTIMIZED"
Parameter

Definition at line 48 of file sens_hispi12l4.v.

CLKIN_PERIOD_SENSOR 3 . 000
Parameter

Definition at line 50 of file sens_hispi12l4.v.

CLKFBOUT_MULT_SENSOR 3
Parameter

Definition at line 51 of file sens_hispi12l4.v.

CLKFBOUT_PHASE_SENSOR 0 . 000
Parameter

Definition at line 52 of file sens_hispi12l4.v.

IPCLK_PHASE 0 . 000
Parameter

Definition at line 53 of file sens_hispi12l4.v.

IPCLK2X_PHASE 0 . 000
Parameter

Definition at line 54 of file sens_hispi12l4.v.

BUF_IPCLK "BUFR"
Parameter

Definition at line 55 of file sens_hispi12l4.v.

BUF_IPCLK2X "BUFR"
Parameter

Definition at line 56 of file sens_hispi12l4.v.

SENS_DIVCLK_DIVIDE 1
Parameter

Definition at line 58 of file sens_hispi12l4.v.

SENS_REF_JITTER1 0 . 010
Parameter

Definition at line 59 of file sens_hispi12l4.v.

SENS_REF_JITTER2 0 . 010
Parameter

Definition at line 60 of file sens_hispi12l4.v.

SENS_SS_EN "FALSE"
Parameter

Definition at line 61 of file sens_hispi12l4.v.

SENS_SS_MODE "CENTER_HIGH"
Parameter

Definition at line 62 of file sens_hispi12l4.v.

SENS_SS_MOD_PERIOD 10000
Parameter

Definition at line 63 of file sens_hispi12l4.v.

DEFAULT_LANE_MAP 8 'b11100100
Parameter

Definition at line 65 of file sens_hispi12l4.v.

HISPI_MSB_FIRST 0
Parameter

Definition at line 66 of file sens_hispi12l4.v.

HISPI_NUMLANES 4
Parameter

Definition at line 67 of file sens_hispi12l4.v.

HISPI_DELAY_CLK "FALSE"
Parameter

Definition at line 68 of file sens_hispi12l4.v.

HISPI_MMCM "TRUE"
Parameter

Definition at line 69 of file sens_hispi12l4.v.

HISPI_KEEP_IRST 5
Parameter

Definition at line 70 of file sens_hispi12l4.v.

HISPI_WAIT_ALL_LANES 4 'h8
Parameter

Definition at line 71 of file sens_hispi12l4.v.

HISPI_FIFO_DEPTH 4
Parameter

Definition at line 72 of file sens_hispi12l4.v.

HISPI_FIFO_START 7
Parameter

Definition at line 73 of file sens_hispi12l4.v.

HISPI_CAPACITANCE "DONT_CARE"
Parameter

Definition at line 74 of file sens_hispi12l4.v.

HISPI_DIFF_TERM "TRUE"
Parameter

Definition at line 75 of file sens_hispi12l4.v.

HISPI_UNTUNED_SPLIT "FALSE"
Parameter

Definition at line 76 of file sens_hispi12l4.v.

HISPI_DQS_BIAS "TRUE"
Parameter

Definition at line 77 of file sens_hispi12l4.v.

HISPI_IBUF_DELAY_VALUE " 0 "
Parameter

Definition at line 78 of file sens_hispi12l4.v.

HISPI_IBUF_LOW_PWR "TRUE"
Parameter

Definition at line 79 of file sens_hispi12l4.v.

HISPI_IFD_DELAY_VALUE "AUTO"
Parameter

Definition at line 80 of file sens_hispi12l4.v.

HISPI_IOSTANDARD "DIFF_SSTL18_I"
Parameter

Definition at line 81 of file sens_hispi12l4.v.

pclk
Input

Definition at line 83 of file sens_hispi12l4.v.

prst
Input

Definition at line 84 of file sens_hispi12l4.v.

sns_dp [HISPI_NUMLANES - 1 : 0 ]
Input

Definition at line 86 of file sens_hispi12l4.v.

sns_dn [HISPI_NUMLANES - 1 : 0 ]
Input

Definition at line 87 of file sens_hispi12l4.v.

sns_clkp
Input

Definition at line 88 of file sens_hispi12l4.v.

sns_clkn
Input

Definition at line 89 of file sens_hispi12l4.v.

pxd_out [ 11 : 0 ]
Output

Definition at line 92 of file sens_hispi12l4.v.

hact_out
Output

Definition at line 94 of file sens_hispi12l4.v.

sof
Output

Definition at line 95 of file sens_hispi12l4.v.

eof reg
Output

Definition at line 96 of file sens_hispi12l4.v.

mclk
Input

Definition at line 99 of file sens_hispi12l4.v.

mrst
Input

Definition at line 100 of file sens_hispi12l4.v.

dly_data [HISPI_NUMLANES * 8 - 1 : 0 ]
Input

Definition at line 101 of file sens_hispi12l4.v.

set_lanes_map
Input

Definition at line 102 of file sens_hispi12l4.v.

set_fifo_dly
Input

Definition at line 103 of file sens_hispi12l4.v.

set_idelay [HISPI_NUMLANES - 1 : 0 ]
Input

Definition at line 104 of file sens_hispi12l4.v.

ld_idelay
Input

Definition at line 105 of file sens_hispi12l4.v.

set_clk_phase
Input

Definition at line 106 of file sens_hispi12l4.v.

rst_mmcm
Input

Definition at line 107 of file sens_hispi12l4.v.

ignore_embedded
Input

Definition at line 108 of file sens_hispi12l4.v.

ps_rdy
Output

Definition at line 111 of file sens_hispi12l4.v.

ps_out [ 7 : 0 ]
Output

Definition at line 112 of file sens_hispi12l4.v.

locked_pxd_mmcm
Output

Definition at line 113 of file sens_hispi12l4.v.

clkin_pxd_stopped_mmcm
Output

Definition at line 114 of file sens_hispi12l4.v.

clkfb_pxd_stopped_mmcm
Output

Definition at line 115 of file sens_hispi12l4.v.

ipclk
Signal

Definition at line 118 of file sens_hispi12l4.v.

ipclk2x
Signal

Definition at line 119 of file sens_hispi12l4.v.

sns_d
Signal

Definition at line 120 of file sens_hispi12l4.v.

irst_r
Signal

Definition at line 123 of file sens_hispi12l4.v.

irst
Signal

Definition at line 124 of file sens_hispi12l4.v.

lanes_map
Signal

Definition at line 125 of file sens_hispi12l4.v.

logical_lanes4
Signal

Definition at line 126 of file sens_hispi12l4.v.

fifo_out_dly_mclk
Signal

Definition at line 127 of file sens_hispi12l4.v.

fifo_out_dly
Signal

Definition at line 128 of file sens_hispi12l4.v.

hispi_aligned
Signal

Definition at line 233 of file sens_hispi12l4.v.

hispi_dv
Signal

Definition at line 234 of file sens_hispi12l4.v.

hispi_embed
Signal

Definition at line 235 of file sens_hispi12l4.v.

hispi_sof
Signal

Definition at line 236 of file sens_hispi12l4.v.

hispi_eof
Signal

Definition at line 237 of file sens_hispi12l4.v.

hispi_sol
Signal

Definition at line 238 of file sens_hispi12l4.v.

hispi_eol
Signal

Definition at line 239 of file sens_hispi12l4.v.

vact_ipclk
Signal

Definition at line 243 of file sens_hispi12l4.v.

vact_pclk_strt
Signal

Definition at line 244 of file sens_hispi12l4.v.

rd_run
Signal

Definition at line 245 of file sens_hispi12l4.v.

rd_line
Signal

Definition at line 246 of file sens_hispi12l4.v.

rd_line_r
Signal

Definition at line 247 of file sens_hispi12l4.v.

sol_all_dly
Signal

Definition at line 248 of file sens_hispi12l4.v.

rd_run_d
Signal

Definition at line 249 of file sens_hispi12l4.v.

sof_pclk
Signal

Definition at line 250 of file sens_hispi12l4.v.

sol_pclk
Signal

Definition at line 252 of file sens_hispi12l4.v.

start_fifo_re
Signal

Definition at line 253 of file sens_hispi12l4.v.

good_lanes
Signal

Definition at line 254 of file sens_hispi12l4.v.

fifo_re
Signal

Definition at line 255 of file sens_hispi12l4.v.

fifo_re_r
Signal

Definition at line 256 of file sens_hispi12l4.v.

hact_r
Signal

Definition at line 257 of file sens_hispi12l4.v.

fifo_out
Signal

Definition at line 258 of file sens_hispi12l4.v.

hact_on
Signal

Definition at line 259 of file sens_hispi12l4.v.

hact_off
Signal

Definition at line 260 of file sens_hispi12l4.v.

ignore_embedded_ipclk
Signal

Definition at line 261 of file sens_hispi12l4.v.

vact_pclk
Signal

Definition at line 262 of file sens_hispi12l4.v.

pxd_out_pre
Signal

Definition at line 263 of file sens_hispi12l4.v.

dly_16 dly_16_start_line_i
Module Instance

Definition at line 332 of file sens_hispi12l4.v.

dly_16 dly_16_hact_on_i
Module Instance

Definition at line 342 of file sens_hispi12l4.v.

dly_16 dly_16_hact_off_i
Module Instance

Definition at line 355 of file sens_hispi12l4.v.

dly_16 dly_16_pxd_out_i
Module Instance

Definition at line 368 of file sens_hispi12l4.v.

GENERATE [380]
GENERATE

Definition at line 380 of file sens_hispi12l4.v.

sens_hispi_clock sens_hispi_clock_i
Module Instance

Definition at line 149 of file sens_hispi12l4.v.

sens_hispi_din sens_hispi_din_i
Module Instance

Definition at line 198 of file sens_hispi12l4.v.

sens_hispi_fifo sens_hispi_fifo_i
Module Instance

Definition at line 397 of file sens_hispi12l4.v.

sens_hispi_lane sens_hispi_lane_i
Module Instance

Definition at line 383 of file sens_hispi12l4.v.

The documentation for this Module was generated from the following files: