sens_hispi_fifo Module Reference

Inheritance diagram for sens_hispi_fifo:

Collaboration diagram for sens_hispi_fifo:

Static Public Member Functions

Always Constructs
ALWAYS_353	( ipclk )
ALWAYS_354	( pclk )

Public Attributes

Inputs
ipclk
irst
we
sol
eol
din	[DATA_WIDTH - 1 : 0 ]
out_dly	[DATA_DEPTH - 1 : 0 ]
pclk
prst
re

Outputs
dout	reg [DATA_WIDTH - 1 : 0 ]
run

Parameters
DATA_WIDTH	12
DATA_DEPTH	4

Signals
reg[DATA_WIDTH - 1 : 0 ]	fifo_ram [ 0 :1<<DATA_DEPTH- 1 ]
reg[DATA_DEPTH : 0 ]	wa
reg[DATA_DEPTH : 0 ]	ra
wire	line_start_pclk
reg	line_run_ipclk
reg	line_run_ipclk_d
reg	line_run_pclk
reg	run_r
reg	start_sent
reg	start_out_ipclk

Module Instances
pulse_cross_clock::pulse_cross_clock_line_start_i	Module pulse_cross_clock

Detailed Description

Definition at line 41 of file sens_hispi_fifo.v.

Member Function Documentation

ALWAYS_353 (   ipclk   )

Always Construct

Definition at line 73 of file sens_hispi_fifo.v.

ALWAYS_354 (   pclk   )

Always Construct

Definition at line 92 of file sens_hispi_fifo.v.

Member Data Documentation

DATA_WIDTH 12

Parameter

Definition at line 43 of file sens_hispi_fifo.v.

DATA_DEPTH 4

Parameter

Definition at line 44 of file sens_hispi_fifo.v.

ipclk

Input

Definition at line 46 of file sens_hispi_fifo.v.

irst

Input

Definition at line 47 of file sens_hispi_fifo.v.

we

Input

Definition at line 48 of file sens_hispi_fifo.v.

sol

Input

Definition at line 49 of file sens_hispi_fifo.v.

eol

Input

Definition at line 50 of file sens_hispi_fifo.v.

din [DATA_WIDTH - 1 : 0 ]

Input

Definition at line 51 of file sens_hispi_fifo.v.

out_dly [DATA_DEPTH - 1 : 0 ]

Input

Definition at line 52 of file sens_hispi_fifo.v.

pclk

Input

Definition at line 53 of file sens_hispi_fifo.v.

prst

Input

Definition at line 54 of file sens_hispi_fifo.v.

re

Input

Definition at line 55 of file sens_hispi_fifo.v.

dout reg [DATA_WIDTH - 1 : 0 ]

Output

Definition at line 56 of file sens_hispi_fifo.v.

run

Output

Definition at line 57 of file sens_hispi_fifo.v.

fifo_ram [ 0 :1<<DATA_DEPTH- 1 ]

Signal

Definition at line 59 of file sens_hispi_fifo.v.

wa

Signal

Definition at line 60 of file sens_hispi_fifo.v.

ra

Signal

Definition at line 61 of file sens_hispi_fifo.v.

line_start_pclk

Signal

Definition at line 62 of file sens_hispi_fifo.v.

line_run_ipclk

Signal

Definition at line 63 of file sens_hispi_fifo.v.

line_run_ipclk_d

Signal

Definition at line 64 of file sens_hispi_fifo.v.

line_run_pclk

Signal

Definition at line 65 of file sens_hispi_fifo.v.

run_r

Signal

Definition at line 66 of file sens_hispi_fifo.v.

start_sent

Signal

Definition at line 67 of file sens_hispi_fifo.v.

start_out_ipclk

Signal

Definition at line 68 of file sens_hispi_fifo.v.

pulse_cross_clock pulse_cross_clock_line_start_i

Module Instance

Definition at line 106 of file sens_hispi_fifo.v.

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The documentation for this Module was generated from the following files:

• sensor/sens_hispi_fifo.v