dct2d8x8_chen Member List

This is the complete list of members for dct2d8x8_chen, including all inherited members.

clk	dly01_16	Input
rst	dly01_16	Input
dly	dly01_16	Input
din	dly01_16	Input
dout	dly01_16	Output
sr	dly01_16	Signal
WIDTH	dct1d_chen	Parameter
OUT_WIDTH	dct1d_chen	Parameter
B_WIDTH	dct1d_chen	Parameter
A_WIDTH	dct1d_chen	Parameter
P_WIDTH	dct1d_chen	Parameter
ROUND_OUT	dct1d_chen	Parameter
COSINE_SHIFT	dct1d_chen	Parameter
COS_1_16	dct1d_chen	Parameter
COS_2_16	dct1d_chen	Parameter
COS_3_16	dct1d_chen	Parameter
COS_4_16	dct1d_chen	Parameter
COS_5_16	dct1d_chen	Parameter
COS_6_16	dct1d_chen	Parameter
COS_7_16	dct1d_chen	Parameter
clk	dct1d_chen	Input
rst	dct1d_chen	Input
en	dct1d_chen	Input
d10_32_76_54	dct1d_chen	Input
start	dct1d_chen	Input
dout	dct1d_chen	Output
pre2_start_out	dct1d_chen	Output
en_out	dct1d_chen	Output
TOTAL_RSHIFT	dct1d_chen	Parameter
BEFORE_SAT_WIDTH	dct1d_chen	Parameter
dsp_ma_bin	dct1d_chen	Signal
dsp_ma_ceb1_1	dct1d_chen	Signal
dsp_ma_ceb2_1	dct1d_chen	Signal
dsp_ma_selb_1	dct1d_chen	Signal
dsp_ma_ain_1	dct1d_chen	Signal
dsp_ma_cea1_1	dct1d_chen	Signal
dsp_ma_cea2_1	dct1d_chen	Signal
dsp_ma_din_1	dct1d_chen	Signal
dsp_ma_ced_1	dct1d_chen	Signal
dsp_ma_sela_1	dct1d_chen	Signal
dsp_ma_en_a_1	dct1d_chen	Signal
dsp_ma_en_d_1	dct1d_chen	Signal
dsp_ma_sub_a_1	dct1d_chen	Signal
dsp_ma_neg_m_1	dct1d_chen	Signal
dsp_ma_accum_1	dct1d_chen	Signal
dsp_ma_p_1	dct1d_chen	Signal
dsp_ma_ceb1_2	dct1d_chen	Signal
dsp_ma_ceb2_2	dct1d_chen	Signal
dsp_ma_selb_2	dct1d_chen	Signal
dsp_ma_ain_2	dct1d_chen	Signal
dsp_ma_cea1_2	dct1d_chen	Signal
dsp_ma_cea2_2	dct1d_chen	Signal
dsp_ma_din_2	dct1d_chen	Signal
dsp_ma_ced_2	dct1d_chen	Signal
dsp_ma_sela_2	dct1d_chen	Signal
dsp_ma_seld_2	dct1d_chen	Signal
dsp_ma_neg_m_2	dct1d_chen	Signal
dsp_ma_accum_2	dct1d_chen	Signal
dsp_ma_p_2	dct1d_chen	Signal
dsp_ma_p_mux	dct1d_chen	Signal
dsp_ma_ain24_1	dct1d_chen	Signal
dsp_ma_din24_1	dct1d_chen	Signal
dsp_ma_ain24_2	dct1d_chen	Signal
dsp_ma_din24_2	dct1d_chen	Signal
simd_a0	dct1d_chen	Signal
simd_a1	dct1d_chen	Signal
simd_a2	dct1d_chen	Signal
simd_a3	dct1d_chen	Signal
simd_a4	dct1d_chen	Signal
simd_a5	dct1d_chen	Signal
simd_b0	dct1d_chen	Signal
simd_b1	dct1d_chen	Signal
simd_b2	dct1d_chen	Signal
simd_b3	dct1d_chen	Signal
simd_b4	dct1d_chen	Signal
simd_b5	dct1d_chen	Signal
simd_p0	dct1d_chen	Signal
simd_p1	dct1d_chen	Signal
simd_p2	dct1d_chen	Signal
simd_p3	dct1d_chen	Signal
simd_p4	dct1d_chen	Signal
simd_p5	dct1d_chen	Signal
simd_cea01	dct1d_chen	Signal
simd_cea23	dct1d_chen	Signal
simd_cea45	dct1d_chen	Signal
simd_ceb01	dct1d_chen	Signal
simd_ceb23	dct1d_chen	Signal
simd_ceb45	dct1d_chen	Signal
simd_sub01	dct1d_chen	Signal
simd_sub23	dct1d_chen	Signal
simd_sub45	dct1d_chen	Signal
simd_cep01	dct1d_chen	Signal
simd_cep23	dct1d_chen	Signal
simd_cep45	dct1d_chen	Signal
phase	dct1d_chen	Signal
phase_cnt	dct1d_chen	Signal
dout_r	dct1d_chen	Signal
dout_round_c	dct1d_chen	Signal
dout_round_w	dct1d_chen	Signal
dout_round_r	dct1d_chen	Signal
dout_sat_w	dct1d_chen	Signal
dout_round	dct1d_chen	Signal
per_type	dct1d_chen	Signal
pre3_start_out	dct1d_chen	Signal
pre_en_out	dct1d_chen	Signal
TRIM_MSB	dct1d_chen	Parameter
WIDTH	dct1d_chen_reorder_in	Parameter
clk	dct1d_chen_reorder_in	Input
rst	dct1d_chen_reorder_in	Input
en	dct1d_chen_reorder_in	Input
din	dct1d_chen_reorder_in	Input
start	dct1d_chen_reorder_in	Input
dout_10_32_76_54	dct1d_chen_reorder_in	Output
start_out	dct1d_chen_reorder_in	Output
en_out	dct1d_chen_reorder_in	Output
last_r	dct1d_chen_reorder_in	Signal
cntr_in	dct1d_chen_reorder_in	Signal
raddr	dct1d_chen_reorder_in	Signal
restart	dct1d_chen_reorder_in	Signal
we	dct1d_chen_reorder_in	Signal
waddr	dct1d_chen_reorder_in	Signal
bufl_ram	dct1d_chen_reorder_in	Signal
bufh_ram	dct1d_chen_reorder_in	Signal
dout_10_32_76_54_r	dct1d_chen_reorder_in	Signal
first_period	dct1d_chen_reorder_in	Signal
en_out_r	dct1d_chen_reorder_in	Signal
last_out	dct1d_chen_reorder_in	Signal
re_r	dct1d_chen_reorder_in	Signal
WIDTH	dct1d_chen_reorder_out	Parameter
clk	dct1d_chen_reorder_out	Input
rst	dct1d_chen_reorder_out	Input
en	dct1d_chen_reorder_out	Input
din	dct1d_chen_reorder_out	Input
pre2_start	dct1d_chen_reorder_out	Input
dout	dct1d_chen_reorder_out	Output
start_out	dct1d_chen_reorder_out	Output
dv	dct1d_chen_reorder_out	Output
en_out	dct1d_chen_reorder_out	Output
reord_buf_ram	dct1d_chen_reorder_out	Signal
dout_r	dct1d_chen_reorder_out	Signal
cntr_in	dct1d_chen_reorder_out	Signal
pre_we_r	dct1d_chen_reorder_out	Signal
we_r	dct1d_chen_reorder_out	Signal
ina_rom	dct1d_chen_reorder_out	Signal
waddr	dct1d_chen_reorder_out	Signal
raddr	dct1d_chen_reorder_out	Signal
per_type	dct1d_chen_reorder_out	Signal
start_out_r	dct1d_chen_reorder_out	Signal
en_out_r	dct1d_chen_reorder_out	Signal
stop_out	dct1d_chen_reorder_out	Signal
INPUT_WIDTH	dct2d8x8_chen
OUTPUT_WIDTH	dct2d8x8_chen
STAGE1_SAFE_BITS	dct2d8x8_chen
STAGE2_SAFE_BITS	dct2d8x8_chen
TRANSPOSE_WIDTH	dct2d8x8_chen
TRIM_STAGE_1	dct2d8x8_chen
TRIM_STAGE_2	dct2d8x8_chen
DSP_WIDTH	dct2d8x8_chen
DSP_B_WIDTH	dct2d8x8_chen
DSP_A_WIDTH	dct2d8x8_chen
DSP_P_WIDTH	dct2d8x8_chen
clk	dct2d8x8_chen
rst	dct2d8x8_chen
start	dct2d8x8_chen
xin	dct2d8x8_chen
last_in	dct2d8x8_chen
pre_first_out	dct2d8x8_chen
dv	dct2d8x8_chen
d_out	dct2d8x8_chen
REPLICATE_IN_STAGE1	dct2d8x8_chen
PAD_IN_STAGE1	dct2d8x8_chen
REPLICATE_IN_STAGE2	dct2d8x8_chen
PAD_IN_STAGE2	dct2d8x8_chen
ROUND_STAGE1	dct2d8x8_chen
ROUND_STAGE2	dct2d8x8_chen
xin_r	dct2d8x8_chen
start_in_r	dct2d8x8_chen
cntr_in	dct2d8x8_chen
en_in_r	dct2d8x8_chen
dct1in_h	dct2d8x8_chen
dct1in_l	dct2d8x8_chen
dct1_start	dct2d8x8_chen
dct1_en	dct2d8x8_chen
dct1in_pad_h	dct2d8x8_chen
dct1in_pad_l	dct2d8x8_chen
dct1_out	dct2d8x8_chen
stage1_pre2_start_out	dct2d8x8_chen
transpose_din	dct2d8x8_chen
transpose_douth	dct2d8x8_chen
transpose_doutl	dct2d8x8_chen
transpose_start_out	dct2d8x8_chen
transpose_en_out	dct2d8x8_chen
dct2in_pad_h	dct2d8x8_chen
dct2in_pad_l	dct2d8x8_chen
dct2_out	dct2d8x8_chen
stage2_pre2_start_out	dct2d8x8_chen
stage2_pre2_en_out	dct2d8x8_chen
dbg_stage1_pre2_en_out	dct2d8x8_chen
WIDTH	dct_chen_transpose	Parameter
clk	dct_chen_transpose	Input
rst	dct_chen_transpose	Input
din	dct_chen_transpose	Input
pre2_start	dct_chen_transpose	Input
dout_10_32_76_54	dct_chen_transpose	Output
start_out	dct_chen_transpose	Output
en_out	dct_chen_transpose	Output
wcntr	dct_chen_transpose	Signal
wrow	dct_chen_transpose	Signal
wcol	dct_chen_transpose	Signal
wpage	dct_chen_transpose	Signal
wcol13	dct_chen_transpose	Signal
wrow_mod	dct_chen_transpose	Signal
wcol01_mod	dct_chen_transpose	Signal
waddr	dct_chen_transpose	Signal
pre2_stop	dct_chen_transpose	Signal
transpose_ram	dct_chen_transpose	Signal
pre_we_r	dct_chen_transpose	Signal
we_r	dct_chen_transpose	Signal
rcntr	dct_chen_transpose	Signal
raddr	dct_chen_transpose	Signal
re_r	dct_chen_transpose	Signal
regen_r	dct_chen_transpose	Signal
ram_reg	dct_chen_transpose	Signal
ram_reg2	dct_chen_transpose	Signal
pre_rstart_w	dct_chen_transpose	Signal
rstop_r	dct_chen_transpose	Signal
first_after_pause	dct_chen_transpose	Signal
ALWAYS_197 clk	dct1d_chen	Always Construct
ALWAYS_198 clk	dct1d_chen_reorder_in	Always Construct
ALWAYS_199 clk	dct1d_chen_reorder_out	Always Construct
ALWAYS_200 clk	dct2d8x8_chen	Always Construct
ALWAYS_201 clk	dct_chen_transpose	Always Construct
ALWAYS_498 clk	dly01_16	Always Construct
dct1d_chen	dct2d8x8_chen
dct1d_chen	dct2d8x8_chen
dct1d_chen_reorder_in	dct2d8x8_chen
dct1d_chen_reorder_out	dct2d8x8_chen
dct_chen_transpose	dct2d8x8_chen
dct_chen_transpose.dly01_16	dct_chen_transpose	Module Instance
dct1d_chen_reorder_out.dly01_16	dct1d_chen_reorder_out	Module Instance
dsp_addsub_simd	dct1d_chen	Module Instance
dsp_addsub_simd	dct1d_chen	Module Instance
dsp_addsub_simd	dct1d_chen	Module Instance
dsp_ma	dct1d_chen	Module Instance
dsp_ma_preadd	dct1d_chen	Module Instance
GENERATE [287]	dct1d_chen	GENERATE