dly01_16 Module Reference

Inheritance diagram for dly01_16:

Static Public Member Functions

Always Constructs
ALWAYS_498	( clk )

Public Attributes

Inputs
clk
rst
dly	[ 3 : 0 ]
din

Outputs
dout

Signals
reg[ 15 : 0 ]	sr

Detailed Description

Definition at line 41 of file dly01_16.v.

Member Function Documentation

ALWAYS_498 (   clk   )

Always Construct

Definition at line 50 of file dly01_16.v.

Member Data Documentation

clk

Input

Definition at line 42 of file dly01_16.v.

rst

Input

Definition at line 43 of file dly01_16.v.

dly [ 3 : 0 ]

Input

Definition at line 44 of file dly01_16.v.

din

Input

Definition at line 45 of file dly01_16.v.

dout

Output

Definition at line 46 of file dly01_16.v.

sr

Signal

Definition at line 48 of file dly01_16.v.

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The documentation for this Module was generated from the following files:

• util_modules/dly01_16.v