x393  1.0
FPGAcodeforElphelNC393camera
Static Public Member Functions | Public Attributes | List of all members
fifo_cross_clocks Module Reference
Inheritance diagram for fifo_cross_clocks:
Inheritance graph
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Static Public Member Functions

Always Constructs

ALWAYS_504  ( wclk or rst )
ALWAYS_505  ( rclk or rst )
ALWAYS_506  ( rclk )
ALWAYS_507  ( wclk )

Public Attributes

Inputs

rst  
rrst  
wrst  
rclk  
wclk  
we  
re  
data_in   [DATA_WIDTH - 1 : 0 ]

Outputs

data_out   [DATA_WIDTH - 1 : 0 ]
nempty  
half_empty  

Parameters

DATA_WIDTH  integer 16
DATA_DEPTH  integer 4
DATA_2DEPTH  integer (1<<DATA_DEPTH)- 1

Signals

reg[DATA_WIDTH - 1 : 0 ]  ram [ 0 :DATA_2DEPTH ]
reg[DATA_DEPTH - 1 : 0 ]  raddr
reg[DATA_DEPTH - 1 : 0 ]  waddr
reg[DATA_DEPTH - 1 : 0 ]  waddr_gray
reg[DATA_DEPTH - 1 : 0 ]  waddr_gray_rclk
wire[DATA_DEPTH - 1 : 0 ]  waddr_plus1
wire[DATA_DEPTH - 1 : 0 ]  waddr_plus1_gray
wire[DATA_DEPTH - 1 : 0 ]  raddr_gray
wire[DATA_DEPTH - 1 : 0 ]  raddr_plus1
wire[ 2 : 0 ]  raddr_plus1_gray_top3
reg[ 2 : 0 ]  raddr_gray_top3
reg[ 2 : 0 ]  raddr_gray_top3_wclk
wire[ 2 : 0 ]  raddr_top3_wclk
wire[ 2 : 0 ]  waddr_top3
wire[ 2 : 0 ]  addr_diff

Detailed Description

Definition at line 41 of file fifo_cross_clocks.v.

Member Function Documentation

ALWAYS_504 (   wclk or rst  
)
Always Construct

Definition at line 91 of file fifo_cross_clocks.v.

ALWAYS_505 (   rclk or rst  
)
Always Construct

Definition at line 102 of file fifo_cross_clocks.v.

ALWAYS_506 (   rclk  
)
Always Construct

Definition at line 113 of file fifo_cross_clocks.v.

ALWAYS_507 (   wclk  
)
Always Construct

Definition at line 118 of file fifo_cross_clocks.v.

Member Data Documentation

DATA_WIDTH 16
Parameter

Definition at line 43 of file fifo_cross_clocks.v.

DATA_DEPTH 4
Parameter

Definition at line 44 of file fifo_cross_clocks.v.

rst
Input

Definition at line 46 of file fifo_cross_clocks.v.

rrst
Input

Definition at line 47 of file fifo_cross_clocks.v.

wrst
Input

Definition at line 48 of file fifo_cross_clocks.v.

rclk
Input

Definition at line 49 of file fifo_cross_clocks.v.

wclk
Input

Definition at line 50 of file fifo_cross_clocks.v.

we
Input

Definition at line 51 of file fifo_cross_clocks.v.

re
Input

Definition at line 52 of file fifo_cross_clocks.v.

data_in [DATA_WIDTH - 1 : 0 ]
Input

Definition at line 53 of file fifo_cross_clocks.v.

data_out [DATA_WIDTH - 1 : 0 ]
Output

Definition at line 54 of file fifo_cross_clocks.v.

nempty
Output

Definition at line 55 of file fifo_cross_clocks.v.

half_empty
Output

Definition at line 56 of file fifo_cross_clocks.v.

DATA_2DEPTH (1<<DATA_DEPTH)- 1
Parameter

Definition at line 58 of file fifo_cross_clocks.v.

ram [ 0 :DATA_2DEPTH ]
Signal

Definition at line 59 of file fifo_cross_clocks.v.

raddr
Signal

Definition at line 60 of file fifo_cross_clocks.v.

waddr
Signal

Definition at line 61 of file fifo_cross_clocks.v.

waddr_gray
Signal

Definition at line 62 of file fifo_cross_clocks.v.

waddr_gray_rclk
Signal

Definition at line 63 of file fifo_cross_clocks.v.

waddr_plus1
Signal

Definition at line 64 of file fifo_cross_clocks.v.

waddr_plus1_gray
Signal

Definition at line 65 of file fifo_cross_clocks.v.

raddr_gray
Signal

Definition at line 67 of file fifo_cross_clocks.v.

raddr_plus1
Signal

Definition at line 68 of file fifo_cross_clocks.v.

raddr_plus1_gray_top3
Signal

Definition at line 69 of file fifo_cross_clocks.v.

raddr_gray_top3
Signal

Definition at line 70 of file fifo_cross_clocks.v.

raddr_gray_top3_wclk
Signal

Definition at line 71 of file fifo_cross_clocks.v.

raddr_top3_wclk
Signal

Definition at line 72 of file fifo_cross_clocks.v.

waddr_top3
Signal

Definition at line 76 of file fifo_cross_clocks.v.

addr_diff
Signal

Definition at line 77 of file fifo_cross_clocks.v.

The documentation for this Module was generated from the following files: