ahci_dma Member List

This is the complete list of members for ahci_dma, including all inherited members.

ahci_dma_wr_fifo.EXTRA_DLY	pulse_cross_clock	Parameter
pulse_cross_clock.EXTRA_DLY	pulse_cross_clock	Parameter
ahci_dma_wr_fifo.rst	pulse_cross_clock	Input
pulse_cross_clock.rst	pulse_cross_clock	Input
ahci_dma_wr_fifo.src_clk	pulse_cross_clock	Input
pulse_cross_clock.src_clk	pulse_cross_clock	Input
ahci_dma_wr_fifo.dst_clk	pulse_cross_clock	Input
pulse_cross_clock.dst_clk	pulse_cross_clock	Input
ahci_dma_wr_fifo.in_pulse	pulse_cross_clock	Input
pulse_cross_clock.in_pulse	pulse_cross_clock	Input
ahci_dma_wr_fifo.out_pulse	pulse_cross_clock	Output
pulse_cross_clock.out_pulse	pulse_cross_clock	Output
ahci_dma_wr_fifo.busy	pulse_cross_clock	Output
pulse_cross_clock.busy	pulse_cross_clock	Output
ahci_dma_wr_fifo.EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
pulse_cross_clock.EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
ahci_dma_wr_fifo.in_reg	pulse_cross_clock	Signal
pulse_cross_clock.in_reg	pulse_cross_clock	Signal
ahci_dma_wr_fifo.out_reg	pulse_cross_clock	Signal
pulse_cross_clock.out_reg	pulse_cross_clock	Signal
ahci_dma_wr_fifo.busy_r	pulse_cross_clock	Signal
pulse_cross_clock.busy_r	pulse_cross_clock	Signal
mrst	ahci_dma
hrst	ahci_dma
mclk	ahci_dma
hclk	ahci_dma
ctba	ahci_dma
ctba_ld	ahci_dma
prdtl	ahci_dma
dev_wr	ahci_dma
cmd_start	ahci_dma
prd_start	ahci_dma
cmd_abort	ahci_dma
axi_wr_cache_mode	ahci_dma
axi_rd_cache_mode	ahci_dma
set_axi_wr_cache_mode	ahci_dma
set_axi_rd_cache_mode	ahci_dma
ct_busy	ahci_dma
ct_addr	ahci_dma
ct_re	ahci_dma
ct_data	ahci_dma
prd_done	ahci_dma
prd_irq_clear	ahci_dma
prd_irq_pend	ahci_dma
cmd_busy	ahci_dma
cmd_done	ahci_dma
abort_busy	ahci_dma
abort_done	ahci_dma
axi_mismatch	ahci_dma
sys_out	ahci_dma
sys_dav	ahci_dma
sys_re	ahci_dma
last_h2d_data	ahci_dma
sys_in	ahci_dma
sys_nfull	ahci_dma
sys_we	ahci_dma
extra_din	ahci_dma
afi_awaddr	ahci_dma
afi_awvalid	ahci_dma
afi_awready	ahci_dma
afi_awid	ahci_dma
afi_awlock	ahci_dma
afi_awcache	ahci_dma
afi_awprot	ahci_dma
afi_awlen	ahci_dma
afi_awsize	ahci_dma
afi_awburst	ahci_dma
afi_awqos	ahci_dma
afi_wdata	ahci_dma
afi_wvalid	ahci_dma
afi_wready	ahci_dma
afi_wid	ahci_dma
afi_wlast	ahci_dma
afi_wstrb	ahci_dma
afi_bvalid	ahci_dma
afi_bready	ahci_dma
afi_bid	ahci_dma
afi_bresp	ahci_dma
afi_wcount	ahci_dma
afi_wacount	ahci_dma
afi_wrissuecap1en	ahci_dma
afi_araddr	ahci_dma
afi_arvalid	ahci_dma
afi_arready	ahci_dma
afi_arid	ahci_dma
afi_arlock	ahci_dma
afi_arcache	ahci_dma
afi_arprot	ahci_dma
afi_arlen	ahci_dma
afi_arsize	ahci_dma
afi_arburst	ahci_dma
afi_arqos	ahci_dma
afi_rdata	ahci_dma
afi_rvalid	ahci_dma
afi_rready	ahci_dma
afi_rid	ahci_dma
afi_rlast	ahci_dma
afi_rresp	ahci_dma
afi_rcount	ahci_dma
afi_racount	ahci_dma
afi_rdissuecap1en	ahci_dma
debug_out	ahci_dma
debug_out1	ahci_dma
debug_dma_h2d	ahci_dma
SAFE_RD_BITS	ahci_dma
ct_data_ram	ahci_dma
int_data_addr	ahci_dma
ctba_r	ahci_dma
prdtl_mclk	ahci_dma
cmd_start_hclk	ahci_dma
prd_start_r	ahci_dma
prd_start_hclk	ahci_dma
prd_start_hclk_r	ahci_dma
cmd_abort_hclk	ahci_dma
prd_enabled	ahci_dma
ct_over_prd_enabled	ahci_dma
ct_maddr	ahci_dma
ct_done	ahci_dma
first_prd_fetch	ahci_dma
afi_addr	ahci_dma
axi_set_raddr_ready	ahci_dma
axi_set_waddr_ready	ahci_dma
axi_set_raddr_w	ahci_dma
axi_set_waddr_w	ahci_dma
axi_set_addr_data_w	ahci_dma
axi_set_raddr_r	ahci_dma
axi_set_waddr_r	ahci_dma
is_ct_addr	ahci_dma
is_prd_addr	ahci_dma
is_data_addr	ahci_dma
data_addr	ahci_dma
data_len	ahci_dma
data_irq	ahci_dma
wcount	ahci_dma
wcount_set	ahci_dma
qwcount	ahci_dma
qwcount_done	ahci_dma
qw_datawr_left	ahci_dma
qw_datawr_burst	ahci_dma
qw_datawr_last	ahci_dma
data_afi_re	ahci_dma
prds_left	ahci_dma
last_prd	ahci_dma
afi_rd_ctl	ahci_dma
ct_busy_r	ahci_dma
prd_rd_busy	ahci_dma
dev_wr_mclk	ahci_dma
dev_wr_hclk	ahci_dma
prd_wr	ahci_dma
prd_rd	ahci_dma
afi_wstb4	ahci_dma
done_dev_wr	ahci_dma
done_dev_rd	ahci_dma
prd_done_hclk	ahci_dma
done_flush	ahci_dma
cmd_done_hclk	ahci_dma
ct_done_mclk	ahci_dma
afi_alen	ahci_dma
afi_wcount_many	ahci_dma
data_next_burst	ahci_dma
raddr_prd_rq	ahci_dma
raddr_prd_pend	ahci_dma
raddr_ct_rq	ahci_dma
raddr_ct_pend	ahci_dma
addr_data_rq_w	ahci_dma
addr_data_rq_r	ahci_dma
waddr_data_rq	ahci_dma
raddr_data_rq	ahci_dma
waddr_data_pend	ahci_dma
raddr_data_pend	ahci_dma
ct_id	ahci_dma
prd_id	ahci_dma
dev_wr_id	ahci_dma
dev_rd_id	ahci_dma
afi_id	ahci_dma
fifo_nempty_mclk	ahci_dma
en_extra_din_r	ahci_dma
ct_data_reg	ahci_dma
hrst_r	ahci_dma
abort_or_reset	ahci_dma
afi_dirty	ahci_dma
afi_dirty_mclk	ahci_dma
abort_done_hclk	ahci_dma
abort_done_mclk	ahci_dma
abort_done_unneeded	ahci_dma
aborting	ahci_dma
afi_wvalid_data	ahci_dma
afi_wvalid_abort	ahci_dma
afi_wid_abort	ahci_dma
afi_rready_abort	ahci_dma
afi_wlast_abort	ahci_dma
abort_rq_mclk	ahci_dma
abort_busy_mclk	ahci_dma
abort_debug	ahci_dma
rwaddr_rq_r	ahci_dma
debug_01	ahci_dma
debug_02	ahci_dma
debug_03	ahci_dma
wcount_plus_data_addr	ahci_dma
dbg_afi_awvalid_cntr	ahci_dma
dbg_qwcount	ahci_dma
dbg_qwcount_cntr	ahci_dma
dbg_set_raddr_count	ahci_dma
dbg_set_waddr_count	ahci_dma
dbg_was_mismatch	ahci_dma
WCNT_BITS	ahci_dma_rd_fifo	Parameter
ADDRESS_BITS	ahci_dma_rd_fifo	Parameter
mrst	ahci_dma_rd_fifo	Input
hrst	ahci_dma_rd_fifo	Input
mclk	ahci_dma_rd_fifo	Input
hclk	ahci_dma_rd_fifo	Input
wcnt	ahci_dma_rd_fifo	Input
woffs	ahci_dma_rd_fifo	Input
start	ahci_dma_rd_fifo	Input
din	ahci_dma_rd_fifo	Input
din_av	ahci_dma_rd_fifo	Input
din_av_many	ahci_dma_rd_fifo	Input
last_prd	ahci_dma_rd_fifo	Input
din_re	ahci_dma_rd_fifo	Output
done	ahci_dma_rd_fifo	Output
done_flush	ahci_dma_rd_fifo	Output
dout	ahci_dma_rd_fifo	Output
dout_vld	ahci_dma_rd_fifo	Output
dout_re	ahci_dma_rd_fifo	Input
last_DW	ahci_dma_rd_fifo	Output
debug_dma_h2d	ahci_dma_rd_fifo	Output
ADDRESS_NUM	ahci_dma_rd_fifo	Parameter
waddr	ahci_dma_rd_fifo	Signal
raddr_r	ahci_dma_rd_fifo	Signal
raddr_w	ahci_dma_rd_fifo	Signal
din_prev	ahci_dma_rd_fifo	Signal
qwcntr	ahci_dma_rd_fifo	Signal
busy	ahci_dma_rd_fifo	Signal
end_offs	ahci_dma_rd_fifo	Signal
fifo_ram	ahci_dma_rd_fifo	Signal
vld_ram	ahci_dma_rd_fifo	Signal
fifo_full	ahci_dma_rd_fifo	Signal
fifo_nempty	ahci_dma_rd_fifo	Signal
fifo_wr	ahci_dma_rd_fifo	Signal
fifo_rd	ahci_dma_rd_fifo	Signal
fifo_rd_r	ahci_dma_rd_fifo	Signal
mrst_hclk	ahci_dma_rd_fifo	Signal
fifo_full2	ahci_dma_rd_fifo	Signal
fifo_dav	ahci_dma_rd_fifo	Signal
fifo_dav2_w	ahci_dma_rd_fifo	Signal
fifo_dav2	ahci_dma_rd_fifo	Signal
fifo_half_hclk	ahci_dma_rd_fifo	Signal
woffs_r	ahci_dma_rd_fifo	Signal
fifo_di	ahci_dma_rd_fifo	Signal
fifo_di_vld	ahci_dma_rd_fifo	Signal
fifo_do_r	ahci_dma_rd_fifo	Signal
fifo_do_vld_r	ahci_dma_rd_fifo	Signal
din_av_safe_r	ahci_dma_rd_fifo	Signal
en_fifo_wr	ahci_dma_rd_fifo	Signal
last_mask	ahci_dma_rd_fifo	Signal
done_flush_mclk	ahci_dma_rd_fifo	Signal
flushing_hclk	ahci_dma_rd_fifo	Signal
flushing_mclk	ahci_dma_rd_fifo	Signal
last_fifo_wr	ahci_dma_rd_fifo	Signal
debug_waddr	ahci_dma_rd_fifo	Signal
debug_raddr	ahci_dma_rd_fifo	Signal
raddr	ahci_dma_rd_fifo	Signal
fifo_do	ahci_dma_rd_fifo	Signal
fifo_do_vld	ahci_dma_rd_fifo	Signal
WCNT_BITS	ahci_dma_wr_fifo	Parameter
ADDRESS_BITS	ahci_dma_wr_fifo	Parameter
mrst	ahci_dma_wr_fifo	Input
hrst	ahci_dma_wr_fifo	Input
mclk	ahci_dma_wr_fifo	Input
hclk	ahci_dma_wr_fifo	Input
wcnt	ahci_dma_wr_fifo	Input
woffs	ahci_dma_wr_fifo	Input
init	ahci_dma_wr_fifo	Input
start	ahci_dma_wr_fifo	Input
dout	ahci_dma_wr_fifo	Output
dout_av_many	ahci_dma_wr_fifo	Input
last_prd	ahci_dma_wr_fifo	Input
dout_we	ahci_dma_wr_fifo	Output
dout_wstb	ahci_dma_wr_fifo	Output
done	ahci_dma_wr_fifo	Output
busy	ahci_dma_wr_fifo	Output
fifo_nempty_mclk	ahci_dma_wr_fifo	Output
din	ahci_dma_wr_fifo	Input
din_rdy	ahci_dma_wr_fifo	Output
din_avail	ahci_dma_wr_fifo	Input
ADDRESS_NUM	ahci_dma_wr_fifo	Parameter
fifo0_ram	ahci_dma_wr_fifo	Signal
fifo1_ram	ahci_dma_wr_fifo	Signal
init_mclk	ahci_dma_wr_fifo	Signal
init_confirm	ahci_dma_wr_fifo	Signal
en_fifo_rd	ahci_dma_wr_fifo	Signal
en_fifo_wr	ahci_dma_wr_fifo	Signal
flush_hclk	ahci_dma_wr_fifo	Signal
flush_mclk	ahci_dma_wr_fifo	Signal
raddr	ahci_dma_wr_fifo	Signal
waddr	ahci_dma_wr_fifo	Signal
fifo_do_prev	ahci_dma_wr_fifo	Signal
fifo_full	ahci_dma_wr_fifo	Signal
fifo_nempty	ahci_dma_wr_fifo	Signal
fifo_wr	ahci_dma_wr_fifo	Signal
fifo_full2	ahci_dma_wr_fifo	Signal
hrst_mclk	ahci_dma_wr_fifo	Signal
fifo_dav	ahci_dma_wr_fifo	Signal
fifo_dav2	ahci_dma_wr_fifo	Signal
fifo_half_mclk	ahci_dma_wr_fifo	Signal
fifo_do	ahci_dma_wr_fifo	Signal
dout_we_w	ahci_dma_wr_fifo	Signal
dout_we_r	ahci_dma_wr_fifo	Signal
wp	ahci_dma_wr_fifo	Signal
fp	ahci_dma_wr_fifo	Signal
wl	ahci_dma_wr_fifo	Signal
mx0	ahci_dma_wr_fifo	Signal
mx1	ahci_dma_wr_fifo	Signal
mx2	ahci_dma_wr_fifo	Signal
mx3	ahci_dma_wr_fifo	Signal
pm	ahci_dma_wr_fifo	Signal
fifo_rd	ahci_dma_wr_fifo	Signal
fifo_rd_r	ahci_dma_wr_fifo	Signal
nfp	ahci_dma_wr_fifo	Signal
swl	ahci_dma_wr_fifo	Signal
need_fifo	ahci_dma_wr_fifo	Signal
busy_r	ahci_dma_wr_fifo	Signal
is_last_prd	ahci_dma_wr_fifo	Signal
wcntr	ahci_dma_wr_fifo	Signal
next_wcntr	ahci_dma_wr_fifo	Signal
flushing	ahci_dma_wr_fifo	Signal
last_qword	ahci_dma_wr_fifo	Signal
done_w	ahci_dma_wr_fifo	Signal
axi_ready	ahci_dma_wr_fifo	Signal
fifo_out_ready	ahci_dma_wr_fifo	Signal
hclk	axi_hp_abort	Input
hrst	axi_hp_abort	Input
abort	axi_hp_abort	Input
busy	axi_hp_abort	Output
done	axi_hp_abort	Output
afi_awvalid	axi_hp_abort	Input
afi_awready	axi_hp_abort	Input
afi_awid	axi_hp_abort	Input
afi_awlen	axi_hp_abort	Input
afi_wvalid_in	axi_hp_abort	Input
afi_wready	axi_hp_abort	Input
afi_wvalid	axi_hp_abort	Output
afi_wid	axi_hp_abort	Output
afi_arvalid	axi_hp_abort	Input
afi_arready	axi_hp_abort	Input
afi_arlen	axi_hp_abort	Input
afi_rready_in	axi_hp_abort	Input
afi_rvalid	axi_hp_abort	Input
afi_rready	axi_hp_abort	Output
afi_wlast	axi_hp_abort	Output
afi_racount	axi_hp_abort	Input
afi_rcount	axi_hp_abort	Input
afi_wacount	axi_hp_abort	Input
afi_wcount	axi_hp_abort	Input
dirty	axi_hp_abort	Output
axi_mismatch	axi_hp_abort	Output
debug	axi_hp_abort	Output
busy_r	axi_hp_abort	Signal
done_w	axi_hp_abort	Signal
aw_lengths_ram	axi_hp_abort	Signal
aw_lengths_waddr	axi_hp_abort	Signal
aw_lengths_raddr	axi_hp_abort	Signal
aw_count	axi_hp_abort	Signal
w_count	axi_hp_abort	Signal
r_count	axi_hp_abort	Signal
adav	axi_hp_abort	Signal
arwr	axi_hp_abort	Signal
drd	axi_hp_abort	Signal
awr	axi_hp_abort	Signal
ard_r	axi_hp_abort	Signal
ard	axi_hp_abort	Signal
wwr	axi_hp_abort	Signal
afi_rready_r	axi_hp_abort	Signal
afi_wlast_r	axi_hp_abort	Signal
busy_aborting	axi_hp_abort	Signal
reset_counters	axi_hp_abort	Signal
ahci_dma_rd_fifo	ahci_dma
ahci_dma_rd_stuff	ahci_dma_rd_fifo	Module Instance
ahci_dma_wr_fifo	ahci_dma
ahci_dma_wr_fifo.ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
pulse_cross_clock.ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ahci_dma_wr_fifo.ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
pulse_cross_clock.ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_574 mclk	ahci_dma	Always Construct
ALWAYS_575 hclk	ahci_dma	Always Construct
ALWAYS_576 hclk	ahci_dma	Always Construct
ALWAYS_577 hclk	ahci_dma_rd_fifo	Always Construct
ALWAYS_578 mclk	ahci_dma_rd_fifo	Always Construct
ALWAYS_580 hclk	ahci_dma_wr_fifo	Always Construct
ALWAYS_581 mclk	ahci_dma_wr_fifo	Always Construct
ALWAYS_582 **	ahci_dma_wr_fifo	Always Construct
ALWAYS_601 hclk	axi_hp_abort	Always Construct
ALWAYS_602 hclk	axi_hp_abort	Always Construct
axi_hp_abort	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma
pulse_cross_clock	ahci_dma