x393  1.0
FPGAcodeforElphelNC393camera
ahci_dma_rd_fifo Module Reference
Inheritance diagram for ahci_dma_rd_fifo:
Collaboration diagram for ahci_dma_rd_fifo:

Static Public Member Functions

Always Constructs

ALWAYS_577  ( hclk )
ALWAYS_578  ( mclk )

Public Attributes

Inputs

mrst  
hrst  
mclk  
hclk  
wcnt   [WCNT_BITS - 1 : 0 ]
woffs   [ 1 : 0 ]
start  
din   [ 63 : 0 ]
din_av  
din_av_many  
last_prd  
dout_re  

Outputs

din_re  
done   reg
done_flush  
dout   [ 31 : 0 ]
dout_vld  
last_DW  
debug_dma_h2d   [ 31 : 0 ]

Parameters

WCNT_BITS   21
ADDRESS_BITS   3
ADDRESS_NUM  (1<<ADDRESS_BITS

Signals

reg[ADDRESS_BITS : 0 ]  waddr
reg[ADDRESS_BITS + 1 : 0 ]  raddr_r
wire[ADDRESS_BITS + 1 : 0 ]  raddr_w
reg[ 63 : 16 ]  din_prev
reg[WCNT_BITS - 3 : 0 ]  qwcntr
reg  busy
wire[ 2 : 0 ]  end_offs
reg[ 63 : 0 ]  fifo_ram [ 0 :ADDRESS_NUM - 1 ]
reg[ 3 : 0 ]  vld_ram [ 0 :ADDRESS_NUM - 1 ]
reg[1<<ADDRESS_BITS- 1 : 0 ]  fifo_full
reg[1<<ADDRESS_BITS- 1 : 0 ]  fifo_nempty
wire  fifo_wr
wire  fifo_rd
reg[ 1 : 0 ]  fifo_rd_r
reg  mrst_hclk
wire[1<<ADDRESS_BITS- 1 : 0 ]  fifo_full2
reg  fifo_dav
wire  fifo_dav2_w
reg  fifo_dav2
reg  fifo_half_hclk
reg[ 1 : 0 ]  woffs_r
wire[ 63 : 0 ]  fifo_di
wire[ 3 : 0 ]  fifo_di_vld
reg[ 63 : 0 ]  fifo_do_r
reg[ 3 : 0 ]  fifo_do_vld_r
reg  din_av_safe_r
reg  en_fifo_wr
reg[ 3 : 0 ]  last_mask
wire  done_flush_mclk
reg  flushing_hclk
reg  flushing_mclk
wire  last_fifo_wr
wire[ 2 : 0 ]  debug_waddr
wire[ 2 : 0 ]  debug_raddr
wire[ADDRESS_BITS + 1 : 0 ]  raddr
wire[ 63 : 0 ]  fifo_do
wire[ 3 : 0 ]  fifo_do_vld

Module Instances

ahci_dma_rd_stuff::ahci_dma_rd_stuff_i   Module ahci_dma_rd_stuff
pulse_cross_clock::done_flush_i   Module pulse_cross_clock

Detailed Description

Definition at line 43 of file ahci_dma_rd_fifo.v.

Member Function Documentation

ALWAYS_577 (   hclk  
)
Always Construct

Definition at line 137 of file ahci_dma_rd_fifo.v.

ALWAYS_578 (   mclk  
)
Always Construct

Definition at line 183 of file ahci_dma_rd_fifo.v.

Member Data Documentation

WCNT_BITS 21
Parameter

Definition at line 44 of file ahci_dma_rd_fifo.v.

ADDRESS_BITS 3
Parameter

Definition at line 45 of file ahci_dma_rd_fifo.v.

mrst
Input

Definition at line 47 of file ahci_dma_rd_fifo.v.

hrst
Input

Definition at line 48 of file ahci_dma_rd_fifo.v.

mclk
Input

Definition at line 49 of file ahci_dma_rd_fifo.v.

hclk
Input

Definition at line 50 of file ahci_dma_rd_fifo.v.

wcnt [WCNT_BITS - 1 : 0 ]
Input

Definition at line 52 of file ahci_dma_rd_fifo.v.

woffs [ 1 : 0 ]
Input

Definition at line 53 of file ahci_dma_rd_fifo.v.

start
Input

Definition at line 54 of file ahci_dma_rd_fifo.v.

din [ 63 : 0 ]
Input

Definition at line 55 of file ahci_dma_rd_fifo.v.

din_av
Input

Definition at line 56 of file ahci_dma_rd_fifo.v.

din_av_many
Input

Definition at line 57 of file ahci_dma_rd_fifo.v.

last_prd
Input

Definition at line 58 of file ahci_dma_rd_fifo.v.

din_re
Output

Definition at line 60 of file ahci_dma_rd_fifo.v.

done reg
Output

Definition at line 61 of file ahci_dma_rd_fifo.v.

done_flush
Output

Definition at line 63 of file ahci_dma_rd_fifo.v.

dout [ 31 : 0 ]
Output

Definition at line 65 of file ahci_dma_rd_fifo.v.

dout_vld
Output

Definition at line 66 of file ahci_dma_rd_fifo.v.

dout_re
Input

Definition at line 67 of file ahci_dma_rd_fifo.v.

last_DW
Output

Definition at line 68 of file ahci_dma_rd_fifo.v.

debug_dma_h2d [ 31 : 0 ]
Output

Definition at line 69 of file ahci_dma_rd_fifo.v.

ADDRESS_NUM (1<<ADDRESS_BITS
Parameter

Definition at line 72 of file ahci_dma_rd_fifo.v.

waddr
Signal

Definition at line 73 of file ahci_dma_rd_fifo.v.

raddr_r
Signal

Definition at line 75 of file ahci_dma_rd_fifo.v.

raddr_w
Signal

Definition at line 76 of file ahci_dma_rd_fifo.v.

din_prev
Signal

Definition at line 77 of file ahci_dma_rd_fifo.v.

qwcntr
Signal

Definition at line 78 of file ahci_dma_rd_fifo.v.

busy
Signal

Definition at line 79 of file ahci_dma_rd_fifo.v.

end_offs
Signal

Definition at line 80 of file ahci_dma_rd_fifo.v.

fifo_ram [ 0 :ADDRESS_NUM - 1 ]
Signal

Definition at line 82 of file ahci_dma_rd_fifo.v.

vld_ram [ 0 :ADDRESS_NUM - 1 ]
Signal

Definition at line 83 of file ahci_dma_rd_fifo.v.

fifo_full
Signal

Definition at line 84 of file ahci_dma_rd_fifo.v.

fifo_nempty
Signal

Definition at line 85 of file ahci_dma_rd_fifo.v.

fifo_wr
Signal

Definition at line 86 of file ahci_dma_rd_fifo.v.

fifo_rd
Signal

Definition at line 87 of file ahci_dma_rd_fifo.v.

fifo_rd_r
Signal

Definition at line 88 of file ahci_dma_rd_fifo.v.

mrst_hclk
Signal

Definition at line 89 of file ahci_dma_rd_fifo.v.

fifo_full2
Signal

Definition at line 91 of file ahci_dma_rd_fifo.v.

fifo_dav
Signal

Definition at line 92 of file ahci_dma_rd_fifo.v.

fifo_dav2_w
Signal

Definition at line 93 of file ahci_dma_rd_fifo.v.

fifo_dav2
Signal

Definition at line 94 of file ahci_dma_rd_fifo.v.

Definition at line 96 of file ahci_dma_rd_fifo.v.

woffs_r
Signal

Definition at line 97 of file ahci_dma_rd_fifo.v.

fifo_di
Signal

Definition at line 99 of file ahci_dma_rd_fifo.v.

fifo_di_vld
Signal

Definition at line 101 of file ahci_dma_rd_fifo.v.

fifo_do_r
Signal

Definition at line 104 of file ahci_dma_rd_fifo.v.

fifo_do_vld_r
Signal

Definition at line 105 of file ahci_dma_rd_fifo.v.

din_av_safe_r
Signal

Definition at line 106 of file ahci_dma_rd_fifo.v.

en_fifo_wr
Signal

Definition at line 107 of file ahci_dma_rd_fifo.v.

last_mask
Signal

Definition at line 108 of file ahci_dma_rd_fifo.v.

Definition at line 109 of file ahci_dma_rd_fifo.v.

flushing_hclk
Signal

Definition at line 110 of file ahci_dma_rd_fifo.v.

flushing_mclk
Signal

Definition at line 111 of file ahci_dma_rd_fifo.v.

last_fifo_wr
Signal

Definition at line 113 of file ahci_dma_rd_fifo.v.

debug_waddr
Signal

Definition at line 120 of file ahci_dma_rd_fifo.v.

debug_raddr
Signal

Definition at line 121 of file ahci_dma_rd_fifo.v.

raddr
Signal

Definition at line 123 of file ahci_dma_rd_fifo.v.

fifo_do
Signal

Definition at line 124 of file ahci_dma_rd_fifo.v.

fifo_do_vld
Signal

Definition at line 125 of file ahci_dma_rd_fifo.v.

ahci_dma_rd_stuff ahci_dma_rd_stuff_i
Module Instance

Definition at line 210 of file ahci_dma_rd_fifo.v.

pulse_cross_clock done_flush_i
Module Instance

Definition at line 229 of file ahci_dma_rd_fifo.v.


The documentation for this Module was generated from the following files: