51 input [
1:
0]
awlock,
// verify the correct values are here 52 input [
3:
0]
awcache,
// verify the correct values are here 53 input [
2:
0]
awprot,
// verify the correct values are here 57 input [
3:
0]
awqos,
// verify the correct values are here 71 // Simulation signals - use same aclk 75 input sim_wr_ready,
// simulation may pause this channel by keeping this signal inactive 82 localparam AW_FIFO_DEPTH =
3;
// FIFO number of address bits to fit AW_FIFO_NUM (number is one bit wider) 83 localparam W_FIFO_DEPTH =
3;
// FIFO number of address bits to fit W_FIFO_NUM 95 http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Accessing-DDR-from-PL-on-Zynq/m-p/324877#M8413 97 To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port. 98 The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post. 104 reg [
11:
0]
next_wr_address_w;
// bits that are incremented in 32-bit mode (higher are kept according to AXI 4KB inc. limit) 110 wire [
5:
0]
awid_out;
// verify it matches wid_out when outputting data 123 reg [
1:
0]
wburst;
// registered burst type 124 reg [
3:
0]
wlen;
// registered awlen type (for wrapped over transfers) 139 // documentation sais : "When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher 140 // priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted 141 assign aresetn= ~
rst;
// probably not needed at all - docs say "do not use" 144 // generate ready signals for address and data 145 // assign wready= !wcount[7] && (!(&wcount[6:0]) || !fifo_data_we_d); 151 // assign awready= !wacount[5] && (!(&wacount[4:0]) || !fifo_addr_we_d); 158 // Count full data bursts ready in FIFO 177 // AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer) 178 // in 64 bit mode - low 3 bits are preserved, next 9 are incremented 212 $display (
"%m: at time %t ERROR: awid=%h, wid=%h",
$time,
awid_out,
wid_out);
258 // localparam AW_FIFO_NUM = 8; // Maximal number of words in AW FIFO 8-words 259 // localparam W_FIFO_NUM = 8; // Maximal number of words in AW 8-words 273 .
under (),
// waddr_under), // output reg 274 .
over (),
// waddr_over), // output reg 275 .
wcount (),
// waddr_wcount), // output[3:0] reg 276 .
rcount (),
// waddr_rcount), // output[3:0] reg 291 .
under (),
//wdata_under), // output reg 292 .
over (),
//wdata_over), // output reg 293 .
wcount (),
//wdata_wcount), // output[3:0] reg 294 .
rcount (),
//wdata_rcount), // output[3:0] reg 298 // **** Write response channel **** 305 // input [ 3:0] sim_bresp_latency, // latency in writing data outside of the module 317 // first FIFO for bresp - latency outside of the module 318 // wresp per burst, not per item ! 330 .
under (),
//wresp_under), // output reg 331 .
over (),
//wresp_over), // output reg 332 .
wcount (),
//wresp_wcount), // output[3:0] reg 333 .
rcount (),
//wresp_rcount), // output[3:0] reg 344 // second wresp FIFO (does it exist in the actual module)? 351 .
re (
wresp_re),
// not allowing RE next cycle after bvalid 356 .
under (),
//wresp_under), // output reg 357 .
over (),
//wresp_over), // output reg 358 .
wcount (),
//wresp_wcount), // output[3:0] reg 359 .
rcount (),
//wresp_rcount), // output[3:0] reg
9268VALID_AWCACHE_MASK4'b0011
9299wcountwire[W_FIFO_DEPTH:0]
9294num_full_datareg[7:0]
[31:0] 9251sim_wr_address
9267VALID_AWLOCK_MASK2'b11
[DATA_WIDTH-1:0] 10452data_in
9298wacountwire[AW_FIFO_DEPTH:0]
[AW_FIFO_DEPTH:0] 9262AW_FIFO_NUM8
9275last_confirmed_writewire
[W_FIFO_DEPTH:0] 9263W_FIFO_NUM8
9269VALID_AWPROT_MASK3'b010
reg [DATA_DEPTH-1:0] 10459rcount
[DATA_DEPTH: 0] 10460wnum_in_fifo
reg [DATA_DEPTH-1:0] 10458wcount
9292write_in_progress_wwire
9273write_addressreg[31:0]
[DATA_WIDTH-1:0] 10453data_out
[ 3:0] 9258sim_bresp_latency
9291start_write_burst_wwire
9295wresp_num_in_fifowire[5:0]
wresp_i fifo_same_clock_fill
[DATA_DEPTH: 0] 10461rnum_in_fifo
9272next_wr_address_wreg[11:0]