45 parameter integer LATENCY=
0,
// minimal delay between inout and output ( 0 - next cycle) 46 parameter integer DEPTH=
8,
// maximal number of commands in FIFO 70 input set_cmd,
// latch all other input data at posedge of clock 71 output ready // command/data FIFO can accept command 94 .
LATENCY(
LATENCY),
// minimal delay between inout and output ( 0 - next cycle) 95 .
DEPTH(
DEPTH)
// maximal number of commands in FIFO 96 // parameter OUT_DELAY = 3.5,
integer 9112ADDRESS_WIDTH32
9137awid_outwire[ID_WIDTH-1:0]
[ADDRESS_WIDTH-1:0] 9120awaddr_in
simul_axi_fifo_i simul_axi_fifo
[ADDRESS_WIDTH-1:0] 9127awaddr
[ID_WIDTH-1:0] 9119awid_in
9138awaddr_outwire[ADDRESS_WIDTH-1:0]