46 parameter integer LATENCY=
0,
// minimal delay between inout and output ( 0 - next cycle) 47 parameter integer DEPTH=
8,
// maximal number of commands in FIFO 51 // parameter integer DATA_2DEPTH=(1<<DATA_DEPTH)-1 73 input set_cmd,
// latch all other input data at posedge of clock 74 output ready // command/data FIFO can accept command 97 .
LATENCY(
LATENCY),
// minimal delay between inout and output ( 0 - next cycle) 98 .
DEPTH(
DEPTH)
// maximal number of commands in FIFO 99 // parameter OUT_DELAY = 3.5,
[ADDRESS_WIDTH-1:0] 9060araddr_in
integer 9052ADDRESS_WIDTH32
[ADDRESS_WIDTH-1:0] 9067araddr
simul_axi_fifo_i simul_axi_fifo
9078araddr_outwire[ADDRESS_WIDTH-1:0]
[ID_WIDTH-1:0] 9059arid_in
9077arid_outwire[ID_WIDTH-1:0]