53 input [
1:
0]
awlock,
// verify the correct values are here 54 input [
3:
0]
awcache,
// verify the correct values are here 55 input [
2:
0]
awprot,
// verify the correct values are here 59 input [
3:
0]
awqos,
// verify the correct values are here 72 // PL extra (non-AXI) signals 74 output [
5:
0]
wacount,
// racount has only 3 bits 76 // Simulation signals - use same aclk 80 input sim_wr_ready,
// simulation may pause this channel by keeping this signal inactive 93 // localparam ADDRESS_BITS=32; 108 http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Accessing-DDR-from-PL-on-Zynq/m-p/324877#M8413 110 To make it work, I set the (AR/AW)CACHE=0x11 and (AR/AW)PROT=0x00. In the CDMA datasheet, these were the recommended values, which I confirmed with ChipScope, when attached to CDMA's master port. 111 The default values set by VHLS were 0x00 and 0x10 respectively, which is also the case in the last post. 113 UPDATE: Xilinx docs say that (AR/AW)CACHE is ignored 133 wire [
11:
3]
next_wr_address;
// bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit) 135 reg [
5:
0]
awid_r;
// awid registered with write_address 140 wire [
5:
0]
awid_out;
// verify it matches wid_out when outputting data 153 reg [
1:
0]
wburst;
// registered burst type 154 reg [
3:
0]
wlen;
// registered awlen type (for wrapped over transfers) 167 // documentation sais : "When set, allows the priority of a transaction at the head of the WrCmdQ to be promoted if higher 168 // priority transactions are backed up behind it." Whqt about demotion? Assuming it is not demoted 172 //awqos & {4{awvalid}} 173 assign aresetn= ~
rst;
// probably not needed at all - docs say "do not use" 174 // Supported control register fields 218 // generate ready signals for address and data 230 // Count full data bursts ready in FIFO 250 // AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer) 251 // in 64 bit mode - low 3 bits are preserved, next 9 are incremented 264 $display (
"%m: at time %t ERROR: awid=%h, wid=%h",
$time,
awid_out,
wid_out);
270 $display (
"%m: at time %t ERROR: awsize_out=%h, currently only 'h3 (8 bytes) is valid",
$time,
awsize_out);
328 .
under (),
//waddr_under), // output reg 329 .
over (),
//waddr_over), // output reg 330 .
wcount (),
//waddr_wcount), // output[3:0] reg 331 .
rcount (),
//waddr_rcount), // output[3:0] reg 346 .
under (),
//wdata_under), // output reg 347 .
over (),
//wdata_over), // output reg 348 .
wcount (),
//wdata_wcount), // output[3:0] reg 349 .
rcount (),
//wdata_rcount), // output[3:0] reg 353 // **** Write response channel **** 360 // input [ 3:0] sim_bresp_latency, // latency in writing data outside of the module 372 // first FIFO for bresp - latency outside of the module 373 // wresp per burst, not per item ! 385 .
under (),
//wresp_under), // output reg 386 .
over (),
//wresp_over), // output reg 387 .
wcount (),
//wresp_wcount), // output[3:0] reg 388 .
rcount (),
//wresp_rcount), // output[3:0] reg 399 // second wresp FIFO (does it exist in the actual module)? 406 .
re (
wresp_re),
// not allowing RE next cycle after bvalid 411 .
under (),
//wresp_under), // output reg 412 .
over (),
//wresp_over), // output reg 413 .
wcount (),
//wresp_wcount), // output[3:0] reg 414 .
rcount (),
//wresp_rcount), // output[3:0] reg
9023last_confirmed_writewire
9040write_in_progress_wwire
9039start_write_burst_rreg
wresp_i fifo_same_clock_fill
9004VALID_AWPROT_MASK3'b010
9045num_full_datareg[7:0]
[DATA_WIDTH-1:0] 10452data_in
[31:0] 8978sim_wr_address
[ 3:0] 8984sim_bresp_latency
9003VALID_AWCACHE_MASK4'b0011
9019next_wr_addresswire[11:3]
9006WrCmdReleaseModereg[1:0]
reg [DATA_DEPTH-1:0] 10459rcount
[DATA_DEPTH: 0] 10460wnum_in_fifo
reg [DATA_DEPTH-1:0] 10458wcount
8995AFI_WRCHAN_ISSUINGCAPAFI_BASECTRL + 'h18
[DATA_WIDTH-1:0] 10453data_out
8997AFI_WRDATAFIFO_LEVELAFI_BASECTRL + 'h20
8994AFI_WRCHAN_CTRLAFI_BASECTRL + 'h14
9046inc_num_full_datawire
9042wresp_num_in_fifowire[5:0]
8993AFI_BASECTRL32'hf8008000+ (HP_PORT << 12
9005WrDataThresholdreg[3:0]
8998AFI_WRDEBUGAFI_BASECTRL + 'h24
9020write_addressreg[31:0]
9038start_write_burst_wwire
8996AFI_WRQOSAFI_BASECTRL + 'h1c
9002VALID_AWLOCK_MASK2'b11
[DATA_DEPTH: 0] 10461rnum_in_fifo