44 // 2 locations reserved for control/status (if they will be needed) 45 parameter SENS_SYNC_MULT =
'h2,
// relative register address to write number of frames to combine in one (minus 1, '0' - each farme) 47 parameter SENS_SYNC_FBITS =
16,
// number of bits in a frame counter for linescan mode 48 parameter SENS_SYNC_LBITS =
16,
// number of bits in a line counter for sof_late output (limited by eof) 54 // input rst, // global reset 55 input pclk,
// global clock input, pixel rate (96MHz for MT9P006) 56 input mclk,
// global system clock, synchronizes commands 57 input mrst,
// @mclk sync reset 58 input prst,
// @mclk sync reset 59 input en,
// @pclk enable channel (0 resets counters) 60 input sof_in,
// @pclk start of frame input, single-cycle 61 input eof_in,
// @pclk end of frame input, single-cycle (to limit sof_late 62 input hact,
// @pclk (use to count lines for delayed pulse) 63 input trigger_mode,
// @mclk - 1 - triggered mode, 0 - free running mode 64 input trig_in,
// @mclk - single-cycle trigger input 65 output trig,
// @pclk trigger signal to the sensor - from trig_in until SOF 66 output reg sof_out_pclk,
// @pclk - use in the same sensor_channel module 67 output sof_out,
// @mclk - single-cycle frame sync (no delay) 68 output sof_late,
// @mclk - single-cycle frame sync (delayed) 70 input [
7:
0]
cmd_ad,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 71 input cmd_stb // strobe (with first byte) for the command a/d 95 reg en_vacts_free=
1'b1;
// register to allow only one vacts after trigger in triggered mode. Allows first vacts after mode is set 96 reg overdue;
// generated at camsync to bypass filtering out second vact after trigger. Needed to prevent lock-up 97 // when exposure > triger period (and trigger is operated as divide-by-2) 145 // enforce minimal frame period (applies to both normal and delayed pulse (Make it only in free-running mode?) 166 )
cmd_deser_sens_sync_i (
167 .
rst (
1'b0),
// input
pulse_cross_clock_sof_late_i pulse_cross_clock
7834period_cntrreg[SENS_SYNC_MINBITS-1:0]
cmd_deser_sens_sync_i cmd_deser
7814lines_leftreg[SENS_SYNC_FBITS-1:0]
7791SENS_SYNC_LATE_DFLT15
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
7815cmd_data_rreg[DATA_WIDTH-1:0]
[DATA_WIDTH-1:0] 9934data
7810DATA_WIDTH(SENS_SYNC_FBITS > SENS_SYNC_LBITS) ? SENS_SYNC_FBITS : SENS_SYNC_LBITS
[ADDR_WIDTH-1:0] 9933addr
7812line_dly_pclkreg[SENS_SYNC_LBITS-1:0]
7811sub_frames_pclkreg[SENS_SYNC_FBITS-1:0]
7813sub_frames_leftreg[SENS_SYNC_FBITS-1:0]