39 //`include "oob_dev.v" 44 // initial reset, resets PLL. After pll is locked, an internal sata reset is generated. 46 // sata clk, generated in pll as usrclk2 54 // ref clk from an external source, shall be connected to pads 57 // sata link data pins 90 //wire [31:0] rxdata_out; 91 //wire [31:0] txdata_in; 92 //wire [3:0] txcharisk_in; 93 //wire [3:0] rxcharisk_out; 117 // sata clk = usrclk2 121 // gtx is ready = all resets are done 135 // output data stream to gtx 138 // input data from gtx 142 // shows if channel is ready 168 // tx reset sequence; waves @ ug476 p67 175 // rx reset sequence; waves @ ug476 p77 200 // issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles 211 // generate internal reset after a clock is established 227 USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk 228 It's recommended to use MMCM instead of PLL, whatever 240 .
BANDWIDTH (
"OPTIMIZED"),
242 .
CLKFBOUT_PHASE (
0.000),
243 .
CLKIN1_PERIOD (
6.666),
244 .
CLKIN2_PERIOD (
0.000),
246 .
CLKOUT0_DUTY_CYCLE (
0.500),
247 .
CLKOUT0_PHASE (
0.000),
248 .
CLKOUT1_DIVIDE (
16),
249 .
CLKOUT1_DUTY_CYCLE (
0.500),
250 .
CLKOUT1_PHASE (
0.000),
251 /* .CLKOUT2_DIVIDE = 1, 252 .CLKOUT2_DUTY_CYCLE = 0.500, 253 .CLKOUT2_PHASE = 0.000, 255 .CLKOUT3_DUTY_CYCLE = 0.500, 256 .CLKOUT3_PHASE = 0.000, 258 .CLKOUT4_DUTY_CYCLE = 0.500, 259 .CLKOUT4_PHASE = 0.000, 261 .CLKOUT5_DUTY_CYCLE = 0.500, 262 .CLKOUT5_PHASE = 0.000,**/ 263 .
COMPENSATION (
"ZHOLD"),
265 .
IS_CLKINSEL_INVERTED (
1'b0),
266 .
IS_PWRDWN_INVERTED (
1'b0),
267 .
IS_RST_INVERTED (
1'b0),
268 .
REF_JITTER1 (
0.010),
269 .
REF_JITTER2 (
0.010),
270 .
STARTUP_WAIT (
"FALSE")
298 Padding for an external input clock @ 150 MHz 302 .
CLKRCV_TRST (
"TRUE"),
315 .
SIM_RECEIVER_DETECT_PASS (
"TRUE"),
316 .
SIM_TX_EIDLE_DRIVE_LEVEL (
"X"),
317 .
SIM_RESET_SPEEDUP (
"FALSE"),
318 .
SIM_CPLLREFCLK_SEL (
3'b001),
319 .
SIM_VERSION (
"4.0"),
320 .
ALIGN_COMMA_DOUBLE (
"FALSE"),
321 .
ALIGN_COMMA_ENABLE (
10'b1111111111),
322 .
ALIGN_COMMA_WORD (
1),
323 .
ALIGN_MCOMMA_DET (
"TRUE"),
324 .
ALIGN_MCOMMA_VALUE (
10'b1010000011),
325 .
ALIGN_PCOMMA_DET (
"TRUE"),
326 .
ALIGN_PCOMMA_VALUE (
10'b0101111100),
327 .
SHOW_REALIGN_COMMA (
"TRUE"),
328 .
RXSLIDE_AUTO_WAIT (
7),
329 .
RXSLIDE_MODE (
"OFF"),
330 .
RX_SIG_VALID_DLY (
10),
331 .
RX_DISPERR_SEQ_MATCH (
"TRUE"),
332 .
DEC_MCOMMA_DETECT (
"TRUE"),
333 .
DEC_PCOMMA_DETECT (
"TRUE"),
334 .
DEC_VALID_COMMA_ONLY (
"FALSE"),
335 .
CBCC_DATA_SOURCE_SEL (
"DECODED"),
336 .
CLK_COR_SEQ_2_USE (
"FALSE"),
337 .
CLK_COR_KEEP_IDLE (
"FALSE"),
338 .
CLK_COR_MAX_LAT (
9),
339 .
CLK_COR_MIN_LAT (
7),
340 .
CLK_COR_PRECEDENCE (
"TRUE"),
341 .
CLK_COR_REPEAT_WAIT (
0),
342 .
CLK_COR_SEQ_LEN (
1),
343 .
CLK_COR_SEQ_1_ENABLE (
4'b1111),
344 .
CLK_COR_SEQ_1_1 (
10'b0100000000),
345 .
CLK_COR_SEQ_1_2 (
10'b0000000000),
346 .
CLK_COR_SEQ_1_3 (
10'b0000000000),
347 .
CLK_COR_SEQ_1_4 (
10'b0000000000),
348 .
CLK_CORRECT_USE (
"FALSE"),
349 .
CLK_COR_SEQ_2_ENABLE (
4'b1111),
350 .
CLK_COR_SEQ_2_1 (
10'b0100000000),
351 .
CLK_COR_SEQ_2_2 (
10'b0000000000),
352 .
CLK_COR_SEQ_2_3 (
10'b0000000000),
353 .
CLK_COR_SEQ_2_4 (
10'b0000000000),
354 .
CHAN_BOND_KEEP_ALIGN (
"FALSE"),
355 .
CHAN_BOND_MAX_SKEW (
1),
356 .
CHAN_BOND_SEQ_LEN (
1),
357 .
CHAN_BOND_SEQ_1_1 (
10'b0000000000),
358 .
CHAN_BOND_SEQ_1_2 (
10'b0000000000),
359 .
CHAN_BOND_SEQ_1_3 (
10'b0000000000),
360 .
CHAN_BOND_SEQ_1_4 (
10'b0000000000),
361 .
CHAN_BOND_SEQ_1_ENABLE (
4'b1111),
362 .
CHAN_BOND_SEQ_2_1 (
10'b0000000000),
363 .
CHAN_BOND_SEQ_2_2 (
10'b0000000000),
364 .
CHAN_BOND_SEQ_2_3 (
10'b0000000000),
365 .
CHAN_BOND_SEQ_2_4 (
10'b0000000000),
366 .
CHAN_BOND_SEQ_2_ENABLE (
4'b1111),
367 .
CHAN_BOND_SEQ_2_USE (
"FALSE"),
368 .
FTS_DESKEW_SEQ_ENABLE (
4'b1111),
369 .
FTS_LANE_DESKEW_CFG (
4'b1111),
370 .
FTS_LANE_DESKEW_EN (
"FALSE"),
371 .
ES_CONTROL (
6'b000000),
372 .
ES_ERRDET_EN (
"FALSE"),
373 .
ES_EYE_SCAN_EN (
"TRUE"),
374 .
ES_HORZ_OFFSET (
12'h000),
375 .
ES_PMA_CFG (
10'b0000000000),
376 .
ES_PRESCALE (
5'b00000),
377 .
ES_QUALIFIER (
80'h00000000000000000000),
378 .
ES_QUAL_MASK (
80'h00000000000000000000),
379 .
ES_SDATA_MASK (
80'h00000000000000000000),
380 .
ES_VERT_OFFSET (
9'b000000000),
382 .
OUTREFCLK_SEL_INV (
2'b11),
383 .
PMA_RSV (
32'h00018480),
384 .
PMA_RSV2 (
16'h2050),
386 .
PMA_RSV4 (
32'h00000000),
387 .
RX_BIAS_CFG (
12'b000000000100),
388 .
DMONITOR_CFG (
24'h000A00),
390 .
RX_CM_TRIM (
3'b010),
391 .
RX_DEBUG_CFG (
12'b000000000000),
392 .
RX_OS_CFG (
13'b0000010000000),
393 .
TERM_RCAL_CFG (
5'b10000),
394 .
TERM_RCAL_OVRD (
1'b0),
395 .
TST_RSV (
32'h00000000),
399 .
PCS_PCIE_EN (
"FALSE"),
400 .
PCS_RSVD_ATTR (
48'h0100),
401 .
RXBUF_ADDR_MODE (
"FAST"),
402 .
RXBUF_EIDLE_HI_CNT (
4'b1000),
403 .
RXBUF_EIDLE_LO_CNT (
4'b0000),
405 .
RX_BUFFER_CFG (
6'b000000),
406 .
RXBUF_RESET_ON_CB_CHANGE (
"TRUE"),
407 .
RXBUF_RESET_ON_COMMAALIGN (
"FALSE"),
408 .
RXBUF_RESET_ON_EIDLE (
"FALSE"),
409 .
RXBUF_RESET_ON_RATE_CHANGE (
"TRUE"),
410 .
RXBUFRESET_TIME (
5'b00001),
411 .
RXBUF_THRESH_OVFLW (
61),
412 .
RXBUF_THRESH_OVRD (
"FALSE"),
413 .
RXBUF_THRESH_UNDFLW (
4),
414 .
RXDLY_CFG (
16'h001F),
415 .
RXDLY_LCFG (
9'h030),
416 .
RXDLY_TAP_CFG (
16'h0000),
417 .
RXPH_CFG (
24'h000000),
418 .
RXPHDLY_CFG (
24'h084020),
419 .
RXPH_MONITOR_SEL (
5'b00000),
420 .
RX_XCLK_SEL (
"RXREC"),
421 .
RX_DDI_SEL (
6'b000000),
422 .
RX_DEFER_RESET_BUF_EN (
"TRUE"),
423 .
RXCDR_CFG (
72'h03000023ff10200020),
424 .
RXCDR_FR_RESET_ON_EIDLE (
1'b0),
425 .
RXCDR_HOLD_DURING_EIDLE (
1'b0),
426 .
RXCDR_PH_RESET_ON_EIDLE (
1'b0),
427 .
RXCDR_LOCK_CFG (
6'b010101),
431 .
RXPCSRESET_TIME (
5'b00001),
433 .
RXOOB_CFG (
7'b0000110),
434 .
RXGEARBOX_EN (
"FALSE"),
435 .
GEARBOX_MODE (
3'b000),
436 .
RXPRBS_ERR_LOOPBACK (
1'b0),
437 .
PD_TRANS_TIME_FROM_P2 (
12'h03c),
438 .
PD_TRANS_TIME_NONE_P2 (
8'h3c),
439 .
PD_TRANS_TIME_TO_P2 (
8'h64),
442 .
SATA_BURST_SEQ_LEN (
4'b0111),
443 .
SATA_BURST_VAL (
3'b110),
444 .
SATA_EIDLE_VAL (
3'b110),
451 .
TRANS_TIME_RATE (
8'h0E),
453 .
TXBUF_RESET_ON_RATE_CHANGE (
"TRUE"),
454 .
TXDLY_CFG (
16'h001F),
455 .
TXDLY_LCFG (
9'h030),
456 .
TXDLY_TAP_CFG (
16'h0000),
457 .
TXPH_CFG (
16'h0780),
458 .
TXPHDLY_CFG (
24'h084020),
459 .
TXPH_MONITOR_SEL (
5'b00000),
460 .
TX_XCLK_SEL (
"TXOUT"),
462 .
TX_DEEMPH0 (
5'b00000),
463 .
TX_DEEMPH1 (
5'b00000),
464 .
TX_EIDLE_ASSERT_DELAY (
3'b110),
465 .
TX_EIDLE_DEASSERT_DELAY (
3'b100),
466 .
TX_LOOPBACK_DRIVE_HIZ (
"FALSE"),
467 .
TX_MAINCURSOR_SEL (
1'b0),
468 .
TX_DRIVE_MODE (
"DIRECT"),
469 .
TX_MARGIN_FULL_0 (
7'b1001110),
470 .
TX_MARGIN_FULL_1 (
7'b1001001),
471 .
TX_MARGIN_FULL_2 (
7'b1000101),
472 .
TX_MARGIN_FULL_3 (
7'b1000010),
473 .
TX_MARGIN_FULL_4 (
7'b1000000),
474 .
TX_MARGIN_LOW_0 (
7'b1000110),
475 .
TX_MARGIN_LOW_1 (
7'b1000100),
476 .
TX_MARGIN_LOW_2 (
7'b1000010),
477 .
TX_MARGIN_LOW_3 (
7'b1000000),
478 .
TX_MARGIN_LOW_4 (
7'b1000000),
479 .
TXGEARBOX_EN (
"FALSE"),
480 .
TXPCSRESET_TIME (
5'b00001),
482 .
TX_RXDETECT_CFG (
14'h1832),
483 .
TX_RXDETECT_REF (
3'b100),
484 .
CPLL_CFG (
24'hBC07DC),
487 .
CPLL_INIT_CFG (
24'h00001E),
488 .
CPLL_LOCK_CFG (
16'h01E8),
489 .
CPLL_REFCLK_DIV (
1),
492 .
SATA_CPLL_CFG (
"VCO_3000MHZ"),
494 .
RXLPM_HF_CFG (
14'b00000011110000),
495 .
RXLPM_LF_CFG (
14'b00000011110000),
496 .
RX_DFE_GAIN_CFG (
23'h020FEA),
497 .
RX_DFE_H2_CFG (
12'b000000000000),
498 .
RX_DFE_H3_CFG (
12'b000001000000),
499 .
RX_DFE_H4_CFG (
11'b00011110000),
500 .
RX_DFE_H5_CFG (
11'b00011100000),
501 .
RX_DFE_KL_CFG (
13'b0000011111110),
502 .
RX_DFE_LPM_CFG (
16'h0954),
503 .
RX_DFE_LPM_HOLD_DURING_EIDLE (
1'b0),
504 .
RX_DFE_UT_CFG (
17'b10001111000000000),
505 .
RX_DFE_VP_CFG (
17'b00011111100000011),
506 .
RX_CLKMUX_PD (
1'b1),
507 .
TX_CLKMUX_PD (
1'b1),
508 .
RX_INT_DATAWIDTH (
0),
509 .
TX_INT_DATAWIDTH (
0),
510 .
TX_QPI_STATUS_EN (
1'b0),
511 .
RX_DFE_KL_CFG2 (
32'h301148AC),
512 .
RX_DFE_XYD_CFG (
13'b0000000000000),
513 .
TX_PREDRIVER_MODE (
1'b0)
638 // .RXDFEVSEN (1'b0), 750 // Serial data bit shift to check host alignment 752 //reg [4:0] serial_delay = 0; 760 // align to 4-byte boundary 782 ///assign txn_out = txn; 783 ///assign txp_out = txp; 787 //assign ll_data_out = rxdata_out; 788 //assign ll_charisk_out = rxcharisk_out; 789 //assign txdata_in = ll_data_in; 790 //assign txcharisk_in = ll_charisk_in; 14490RXISCANRESET_TIME5'h1
wire [DATA_BYTE_WIDTH - 1:0] 14386rxcharisk_in
14494txpcsreset_cntreg[3:0]
[1:0] 14502CLKSWING_CFG2'b11
14489RXDFELPMRESET_TIME7'hf
14442rxdata_gtxwire[63:0]
14485txpmareset_cntreg[2:0]
14486RXPMARESET_TIME5'h11
14491RXEYERESET_TIME7'h0 + RXPMARESET_TIME + RXCDRPHRESET_TIME + RXCDRFREQRESET_TIME + RXDFELPMRESET_TIME + RXISCANRESET_TIME
[1:0] 15731RXELECIDLEMODE
[7:0] 15665TXCHARDISPMODE
wire [DATA_BYTE_WIDTH*8 - 1:0] 14383txdata_out
ext_clock_buf IBUFDS_GTE2
wire [DATA_BYTE_WIDTH - 1:0] 14384txcharisk_out
wire [31:0] 14434ll_data_in
wire [DATA_BYTE_WIDTH*8 - 1:0] 14385rxdata_in
gtx_wrapper gtxe2_channel_wrapper
14440txcharisk_oobwire[3:0]
wire 14376rxcomwakedet_in
14450rxnotintable_gtxwire[7:0]
14449rxnotintablewire[7:0]
14488RXCDRFREQRESET_TIME5'h1
wire [3:0] 14435ll_charisk_in
14487RXCDRPHRESET_TIME5'h1
14438txdata_oobwire[31:0]
14444rxcharisk_gtxwire[7:0]
14448rxdisperr_gtxwire[7:0]
[4:0] 15806RXPHSLIPMONITOR
wire [3:0] 14433ll_err_out
[7:0] 14498RST_TIMER_LIMIT8'b1000
wire [3:0] 14432ll_charisk_out
14446rxchariscomma_gtxwire[7:0]
14445rxchariscommawire[7:0]
wire [31:0] 14431ll_data_out
wire 14375rxcominitdet_in
14492rxeyereset_cntreg[6:0]