627
5530line_start_page_leftreg[COLADDR_NUMBER-4:0]
5474MCNTRL_TILED_WINDOW_X0Y0'h7
[FRAME_WIDTH_BITS:0] 5515rowcol_inc
5580pending_xfersreg[MCNTRL_TILED_PENDING_CNTR_BITS-1:0]
5479MCNTRL_TILED_FRAME_PAGE_RESET1'b0
5470MCNTRL_TILED_FRAME_SIZE'h3
5526curr_xreg[FRAME_WIDTH_BITS-1:0]
5484MCONTR_LINTILE_EXTRAPG_BITS2
5489MCONTR_LINTILE_REPEAT10
[MAX_TILE_HEIGHT-1:0] 5517num_cols_m1
5480MCONTR_LINTILE_NRESET0
5535mul_rsltreg[MPY_WIDTH-1:0]
5533frame_y8_rreg[FRAME_HEIGHT_BITS-4:0]
5476MCNTRL_TILED_TILE_WHS'h9
5609next_frame_start_addrreg[NUM_RC_BURST_BITS-1:0]
[COLADDR_NUMBER-3-MAX_TILE_WIDTH-1:0] 5629EXTRA_BITS0
5610frame_number_cntrreg[LAST_FRAME_BITS-1:0]
5483MCONTR_LINTILE_EXTRAPG3
5570rst_frame_num_rreg[1:0]
5552par_mod_rreg[PAR_MOD_LATENCY-1:0]
5469MCNTRL_TILED_STARTADDR'h2
5615tile_rowsreg[MAX_TILE_HEIGHT:0]
5626start_yreg[FRAME_HEIGHT_BITS-1:0]
status_generate_i status_generate
5472MCNTRL_TILED_FRAME_FULL_WIDTH'h5
[LAST_FRAME_BITS-1:0] 5504frame_number
5485MCONTR_LINTILE_KEEP_OPEN5
5531frame_yreg[FRAME_HEIGHT_BITS-1:0]
5605start_range_addrreg[NUM_RC_BURST_BITS-1:0]
5553recalc_rreg[PAR_MOD_LATENCY-1:0]
5632start_not_partialwire
5630xfer_limited_by_mem_pagewire
5465MCNTRL_TILED_ADDR'h120
5581row_col_rreg[NUM_RC_BURST_BITS-1:0]
5541mem_page_leftreg[COLADDR_NUMBER-3:0]
5529line_start_addrreg[NUM_RC_BURST_BITS-1:0]
5621window_widthreg[FRAME_WIDTH_BITS:0]
5631xfer_limited_by_mem_page_rreg
5482MCONTR_LINTILE_WRITE2
5611frame_number_currentreg[LAST_FRAME_BITS-1:0]
5625start_xreg[FRAME_WIDTH_BITS-1:0]
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
5523NUM_RC_BURST_BITSADDRESS_NUMBER+COLADDR_NUMBER-3
5478MCNTRL_TILED_PENDING_CNTR_BITS2
5543remainder_tile_widthwire[COLADDR_NUMBER-3:0]
5545leftover_colsreg[MAX_TILE_WIDTH-1:0]
5468MCNTRL_TILED_STATUS_CNTRL'h1
5620frame_full_widthreg[FRAME_WIDTH_BITS:0]
5532frame_xreg[FRAME_WIDTH_BITS-1:0]
5596set_window_x0y0_wwire
5524MPY_WIDTHNUM_RC_BURST_BITS
[MAX_TILE_WIDTH-1:0] 5516num_rows_m1
5618num_cols_m1_wwire[MAX_TILE_WIDTH:0]
5527curr_yreg[FRAME_HEIGHT_BITS-1:0]
5583line_unfinished_rreg[FRAME_HEIGHT_BITS-1:0]
5466MCNTRL_TILED_MASK'h7f0
5536start_addr_rreg[NUM_RC_BURST_BITS-1:0]
5563cmd_extra_pageswire[1:0]
5613frame_start_rreg[4:0]
5488MCONTR_LINTILE_SINGLE9
5487MCONTR_LINTILE_RST_FRAME8
5473MCNTRL_TILED_WINDOW_WH'h6
[DATA_WIDTH-1:0] 9934data
5608start_addrreg[NUM_RC_BURST_BITS-1:0]
5622window_heightreg[FRAME_HEIGHT_BITS:0]
5490MCONTR_LINTILE_DIS_NEED11
5477MCNTRL_TILED_STATUS_REG_ADDR'h5
5528next_yreg[FRAME_HEIGHT_BITS:0]
5617num_cols_rreg[MAX_TILE_WIDTH:0]
5539row_leftreg[FRAME_WIDTH_BITS:0]
[ADDR_WIDTH-1:0] 9933addr
[COLADDR_NUMBER-4:0] 5514xfer_col
[ADDRESS_NUMBER-1:0] 5513xfer_row
cmd_deser_32bit_i cmd_deser
5624window_y0reg[FRAME_HEIGHT_BITS-1:0]
5486MCONTR_LINTILE_BYTE326
5594set_frame_width_wwire
5471MCNTRL_TILED_FRAME_LAST'h4
[FRAME_HEIGHT_BITS-1:0] 5502line_unfinished
5607last_frame_numberreg[LAST_FRAME_BITS-1:0]
5614tile_colsreg[MAX_TILE_WIDTH:0]
5542lim_by_tile_widthreg[MAX_TILE_WIDTH:0]
5582line_unfinished_relw_rreg[FRAME_HEIGHT_BITS-1:0]
5597set_window_start_wwire
5606frame_sizereg[NUM_RC_BURST_BITS-1:0]
[ALL_BITS-1:0] 10777status
5619num_rows_m1_wwire[MAX_TILE_HEIGHT:0]
5534frame_full_width_rreg[FRAME_WIDTH_BITS:0]
5475MCNTRL_TILED_WINDOW_STARTXY'h8
5616tile_vstepreg[MAX_TILE_HEIGHT:0]
5538mul_rslt_wwire[FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0]
5623window_x0reg[FRAME_WIDTH_BITS-1:0]